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2012-03-09cache-v7: Fix typoDan Willemsen
Change 6dfe0d880a was backported from upstream, but differed from the upstream patch with a typo - CONFIG_PREEMP vs CONFIG_PREEMPT Change-Id: Ib8dea88cfc4d85bc6a3873acd4152bc628c03bb0 Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Reviewed-on: http://git-master/r/85059 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-03-02arm: cache: fix v7 boot with lockdep enabledPrashant Gaikwad
Bootup with lockdep enabled has been broken on v7 since b46c0f74657d ("ARM: 7321/1: cache-v7: Disable preemption when reading CCSIDR"). This is because v7_setup (which is called very early during boot) calls v7_flush_dcache_all, and the save_and_disable_irqs added by that patch ends up attempting to call into lockdep C code (trace_hardirqs_off()) when we are in no position to execute it (no stack, MMU off). Fix this by using a notrace variant of save_and_disable_irqs. The code already uses the notrace variant of restore_irqs. Change-Id: I1110a7e07fa3f96022b2e198488fa698c91e2642 Reviewed-by: Nicolas Pitre <(address hidden)> Acked-by: Stephen Boyd <(address hidden)> Cc: Catalin Marinas <(address hidden)> Cc: stable@vger.kernel.org Signed-off-by: Rabin Vincent <(address hidden)> Reviewed-on: http://git-master/r/86779 Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
2012-02-15cache-v7: Disable preemption when reading CCSIDRStephen Boyd
armv7's flush_cache_all() flushes caches via set/way. To determine the cache attributes (line size, number of sets, etc.) the assembly first writes the CSSELR register to select a cache level and then reads the CCSIDR register. The CSSELR register is banked per-cpu and is used to determine which cache level CCSIDR reads. If the task is migrated between when the CSSELR is written and the CCSIDR is read the CCSIDR value may be for an unexpected cache level (for example L1 instead of L2) and incorrect cache flushing could occur. Disable interrupts across the write and read so that the correct cache attributes are read and used for the cache flushing routine. We disable interrupts instead of disabling preemption because the critical section is only 3 instructions and we want to call v7_dcache_flush_all from __v7_setup which doesn't have a full kernel stack with a struct thread_info. This fixes a problem we see in scm_call() when flush_cache_all() is called from preemptible context and sometimes the L2 cache is not properly flushed out. Signed-off-by: Stephen Boyd <(address hidden)> Acked-by: Catalin Marinas <(address hidden)> Reviewed-by: Nicolas Pitre <(address hidden)> Cc: stable@vger.kernel.org Change-Id: I34a54ac396929d9e4f9abb43fbeaeb71d5514b63 Reviewed-on: http://git-master/r/83094 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
2011-11-30tegra:video:nvmap: optimize cache_maint operation.vdumpa
video:tegra:nvmap: Clean whole L1 instead of cleaning by MVA For large allocations, cleaning each page of the allocation can take a significant amount of time. If an allocation that nvmap needs to clean or invalidate out of the cache is significantly larger than the cache, just flush the entire cache by set/ways. bug 788967 Reviewed-on: http://git-master/r/19354 (cherry picked from commit c01c12e63b1476501204152356867aeb5091fb80) tegra:video:nvmap: optimize cache_maint operation. optimize cache_maint operation for carveout and heap memories. flush carveout memory allocations on memory free. Bug 761637 Reviewed-on: http://git-master/r/21205 Conflicts: drivers/video/tegra/nvmap/nvmap_dev.c drivers/video/tegra/nvmap/nvmap_heap.c drivers/video/tegra/nvmap/nvmap_ioctl.c (cherry picked from commit 731df4df5e895e1d4999359d6d5939fc2095f883) tegra:video:nvmap: optimize cache flush for system heap pages. optimize cache flush for pages allocated from system heap. Bug 788187 Reviewed-on: http://git-master/r/21687 (cherry picked from commit 3f318911ad91410aed53c90494210e2b8f74308b) Original-Change-Id: Ia7b90ba0b50acfef1b88dd8095219c51733e027f Reviewed-on: http://git-master/r/23465 Reviewed-by: Kirill Artamonov <kartamonov@nvidia.com> Tested-by: Kirill Artamonov <kartamonov@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: R04f618f88ed1d2c7a680d51a8c5113f42de3f667
2011-09-17ARM: 7091/1: errata: D-cache line maintenance operation by MVA may not succeedWill Deacon
This patch implements a workaround for erratum 764369 affecting Cortex-A9 MPCore with two or more processors (all current revisions). Under certain timing circumstances, a data cache line maintenance operation by MVA targeting an Inner Shareable memory region may fail to proceed up to either the Point of Coherency or to the Point of Unification of the system. This workaround adds a DSB instruction before the relevant cache maintenance functions and sets a specific bit in the diagnostic control register of the SCU. Cc: <stable@kernel.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-07-07ARM: mm: cache-v7: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-05-26ARM: 6941/1: cache: ensure MVA is cacheline aligned in flush_kern_dcache_areaWill Deacon
The v6 and v7 implementations of flush_kern_dcache_area do not align the passed MVA to the size of a cacheline in the data cache. If a misaligned address is used, only a subset of the requested area will be flushed. This has been observed to cause failures in SMP boot where the secondary_data initialised by the primary CPU is not cacheline aligned, causing the secondary CPUs to read incorrect values for their pgd and stack pointers. This patch ensures that the base address is cacheline aligned before flushing the d-cache. Cc: <stable@kernel.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-03-31Fix common misspellingsLucas De Marchi
Fixes generated by 'codespell' and manually reviewed. Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
2010-12-12ARM: 6528/1: Use CTR for the I-cache line size on ARMv7Catalin Marinas
The current implementation of the v7_coherent_*_range function assumes that the D and I cache lines have the same size, which is incorrect architecturally. This patch adds the icache_line_size macro which reads the CTR register. The main loop in v7_coherent_*_range is split in two independent loops or the D and I caches. This also has the performance advantage that the DSB is moved outside the main loop. Reported-by: Kevin Sapp <ksapp@quicinc.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-10-04ARM: 6405/1: Handle __flush_icache_all for CONFIG_SMP_ON_UPTony Lindgren
Do this by adding flush_icache_all to cache_fns for ARMv6 and 7. As flush_icache_all may neeed to be called from flush_kern_cache_all, add it as the first entry in the cache_fns. Note that now we can remove the ARM_ERRATA_411920 dependency to !SMP so it can be selected on UP ARMv6 processors, such as omap2. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Anand Gadiyar <gadiyar@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-10-04ARM: Allow SMP kernels to boot on UP systemsRussell King
UP systems do not implement all the instructions that SMP systems have, so in order to boot a SMP kernel on a UP system, we need to rewrite parts of the kernel. Do this using an 'alternatives' scheme, where the kernel code and data is modified prior to initialization to replace the SMP instructions, thereby rendering the problematical code ineffectual. We use the linker to generate a list of 32-bit word locations and their replacement values, and run through these replacements when we detect a UP system. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-05-20ARM: 6139/1: ARMv7: Use the Inner Shareable I-cache on MPSantosh Shilimkar
This patch fixes the flush_cache_all for ARMv7 SMP.It was missing from commit b8349b569aae661dea9d59d7d2ee587ccea3336c Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Cc: <stable@kernel.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-05-08ARM: 6112/1: Use the Inner Shareable I-cache and BTB ops on ARMv7 SMPCatalin Marinas
The standard I-cache Invalidate All (ICIALLU) and Branch Predication Invalidate All (BPIALL) operations are not automatically broadcast to the other CPUs in an ARMv7 MP system. The patch adds the Inner Shareable variants, ICIALLUIS and BPIALLIS, if ARMv7 and SMP. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-02-15ARM: dma-mapping: fix for speculative prefetchingRussell King
ARMv6 and ARMv7 CPUs can perform speculative prefetching, which makes DMA cache coherency handling slightly more interesting. Rather than being able to rely upon the CPU not accessing the DMA buffer until DMA has completed, we now must expect that the cache could be loaded with possibly stale data from the DMA buffer. Where DMA involves data being transferred to the device, we clean the cache before handing it over for DMA, otherwise we invalidate the buffer to get rid of potential writebacks. On DMA Completion, if data was transferred from the device, we invalidate the buffer to get rid of any stale speculative prefetches. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-By: Santosh Shilimkar <santosh.shilimkar@ti.com>
2010-02-15ARM: dma-mapping: remove dmac_clean_range and dmac_inv_rangeRussell King
These are now unused, and so can be removed. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-By: Santosh Shilimkar <santosh.shilimkar@ti.com>
2010-02-15ARM: dma-mapping: provide per-cpu type map/unmap functionsRussell King
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-By: Santosh Shilimkar <santosh.shilimkar@ti.com>
2009-12-14ARM: add size argument to __cpuc_flush_dcache_pageRussell King
... and rename the function since it no longer operates on just pages. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-10-07ARM: 5746/1: Handle possible translation errors in ARMv6/v7 coherent_user_rangeCatalin Marinas
This is needed because applications using the sys_cacheflush system call can pass a memory range which isn't mapped yet even though the corresponding vma is valid. The patch also adds unwinding annotations for correct backtraces from the coherent_user_range() functions. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-07-24Thumb-2: Implement the unified arch/arm/mm supportCatalin Marinas
This patch adds the ARM/Thumb-2 unified support to the arch/arm/mm/* files. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2008-11-06ARMv7: Add extra barriers for flush_cache_all compressed/head.SCatalin Marinas
The flush_cache_all function on ARMv7 is implemented as a series of cache operations by set/way. These are not guaranteed to be ordered with previous memory accesses, requiring a DMB. This patch also adds barriers for the TLB operations in compressed/head.S Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2008-09-01[ARM] 5227/1: Add the ENDPROC declarations to the .S filesCatalin Marinas
This declaration specifies the "function" type and size for various assembly functions, mainly needed for generating the correct branch instructions in Thumb-2. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-05-08[ARM] armv7: add support for ARMv7 cores.Catalin Marinas
This patch adds support for the ARMv7 cores. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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