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2014-03-13Merge branch 'linux-3.10.33' into dev-kernel-3.10Deepak Nibade
Bug 1456092 Change-Id: I3021247ec68a3c2dddd9e98cde13d70a45191d53 Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
2014-03-06ARM: 7953/1: mm: ensure TLB invalidation is complete before enabling MMUWill Deacon
commit bae0ca2bc550d1ec6a118fb8f2696f18c4da3d8e upstream. During __v{6,7}_setup, we invalidate the TLBs since we are about to enable the MMU on return to head.S. Unfortunately, without a subsequent dsb instruction, the invalidation is not guaranteed to have completed by the time we write to the sctlr, potentially exposing us to junk/stale translations cached in the TLB. This patch reworks the init functions so that the dsb used to ensure completion of cache/predictor maintenance is also used to ensure completion of the TLB invalidation. Reported-by: Albin Tonnerre <Albin.Tonnerre@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-02-09arch: arm: mm: dynamic check for secure/non-secure mode.Nitin Sehgal
- Replace compile time flag with runtime selection. - Same kernel should work in secure and non secure mode bug 1411345 Change-Id: I7b20121623aa432eaefe00f47115908595590f16 Signed-off-by: Nitin Sehgal <nsehgal@nvidia.com> Reviewed-on: http://git-master/r/362897 Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Tested-by: Varun Wadekar <vwadekar@nvidia.com>
2013-09-14arm: Support for regional clock gating in A15 R3Alex Van Brunt
The Cortx A15 r3 adds additional regional clock gating to save power. This is enabled by setting bit 31 of ACTLR2. So, enable it at boot time and after power-gating Bug 1332608 Change-Id: Id9be4ebe0b8e2c546a20fc8db9215d21b508f5ba Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com> Reviewed-on: http://git-master/r/253139 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bo Yan <byan@nvidia.com> Reviewed-by: Dan Hansen <dhansen@nvidia.com> GVS: Gerrit_Virtual_Submit
2013-09-14ARM: mm: Save and restore event countersAntti P Miettinen
Save and restore event counter selections and counter values over power gating. Change-Id: If9b467781e94cb08b8cf8a980fff00eb5af71250 Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com> Reviewed-on: http://git-master/r/192646 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bo Yan <byan@nvidia.com>
2013-09-14ARM: Tegra: Add CONFIG_TEGRA_USE_SECURE_KERNELJames Zhao
This new config would only be enabled when we enable a secure os implementation. This config would be generic and we can reuse it if/when we change the secure os vendor. Change-Id: I94a0a365d4dc834fafa1137a0c0d9adf1b394c51 Signed-off-by: James Zhao <jamesz@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/211756 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Chris Johnson <cwj@nvidia.com>
2013-09-14ARM errata: Writing ACTLR.SMP when the L2 cache has been idle for an ↵Bo Yan
extended period may not work correctly This workaround is for ARM errata 799270 which is applicable to Cortex-A15 up to revision R2P4. The workaround is to read from a device register and create a data dependency between this read and the modification of ACTLR. Change-Id: I26813f17a8a9c6a90446ddeb943ef318e3c69770 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/212770 (cherry picked from commit 2340401e2dec7228bcc5d9074c310d0146454736) Reviewed-on: http://git-master/r/213135 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2013-09-14ARM: tegra14: enable L1 prefetchBo Yan
Bug 1234168 Change-Id: I61d968955972f129a1be8fdccbdcdf01041d8043 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/199718 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
2013-09-14ARM: mm: Skip I-cache invalidate for Cortex-A15 bootBo Yan
This is not required since cache is invalidated by HW in the reset sequence. Bootloader is supposed to do the same before it hands over control to kernel. Change-Id: I0991de3ba1015a32f2c49a0333fd0b17a51a4f31 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/197028 (cherry picked from commit 9c49ffd08d6da03caa820711db83f561d9333aee) Reviewed-on: http://git-master/r/200854 GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-09-14ARM: tegra11x: Disable L2 prefetch throttleBo Yan
Disable A15's L2 prefetch throttle mechanism to improve performance. bug 1212902 Change-Id: I03a27518b26da3cbf1e7aad96ff2d67187a1ebf6 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/188788 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Hyung Taek Ryoo <hryoo@nvidia.com>
2013-09-14ARM: tegra11x: start L2 clock before enabling SMPBo Yan
Do an external device read to start L2 clock, then change SMP bit in ACTLR. The ACTLR change needs to be done immediately after the device read is done since there are only 256 clock cycles maximum available before the L2 clock can be gated again. bug 1208654 bug 1195192 Change-Id: Ide1c0476d629cbea07f585013ed3b7e79a67c86e Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/187521 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bobby Meeker <bmeeker@nvidia.com>
2013-09-14ARM: mm: Remove unnecessary CMO in Cortex A15 startupBo Yan
Cortex-A15 flush L2 cache after reset, there is no need to do this in software, if L2 is already invalidated in bootloader and cache is disabled. For secondary startup, there is no reason to flush L2 as well. This change assumes the setup code is always entered as the result of CPU reset. Change-Id: I6d58f8b4a638b70acfb35b97c87a09266aceef41 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/170563 Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com> Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>
2013-09-14arm: errata: 761320: Full cache line writes to the same memory region from ↵Krishna Reddy
at least two processors might deadlock processor Under very rare circumstances, full cache line writes from (at least) 2 processors on cache lines in hazard with other requests may cause arbitration issues in the SCU, leading to processor deadlock. This erratum can be worked around by setting bit[21] of the undocumented Diagnostic Control Register to 1. Change-Id: I83f919ead5ef4f90f50fa3f38f2cc31ab6bfc31e Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/170582 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bo Yan <byan@nvidia.com>
2013-09-14ARM: mm: restore counter enable registerBo Yan
Change-Id: I2433e53175e79d558d76a7c37b10de9175d7b1b0 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/167385 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2013-09-14ARM: mm: Enable NCSE feature for A15 onlyBo Yan
Change-Id: If966ee69f1d5e4314f79685238ecff3c44eadac0 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/167879 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
2013-09-14ARM: mm: enable non-cacheable streaming enhancementBo Yan
This is cortex-a15 specific bug 1178938 Change-Id: Id695d89dbe1411d277f2c1296c74586ca9c1584e Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/164168 Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com> Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>
2013-09-14ARM: mm: enable ARM_ERRATA_752520 WAR only for r2p0 to r2p8Vishal Singh
The work around for ARM erratum 752520 was applied for all revisions upto r2p8. But this erratum is present only on r2p0 to r2p8 versions while T20 has r1p1 revision. Making this change to enable the WAR only for revisions from r2p0 to r2p8. Bug 853428 Bug 1045637 Reviewed-on: http://git-master/r/43962 (cherry picked from commit 57a0028d94c7ad71acab0c9ee29f5472e46c55bf) Reviewed-on: http://git-master/r/44540 (cherry picked from commit d7f06b0a1b247f2a1444b3b78bc7dc8b21a5b7dd) Reviewed-on: http://git-master/r/161949 (cherry picked from commit f84777eadee307e605f3accdfbf7114917e5a51c) Change-Id: Id3ab36cb757d45ab9bddfa5b08c0643a00765bb2 Signed-off-by: Vishal Annapurve <vannapurve@nvidia.com> Signed-off-by: Vishal Singh <vissingh@nvidia.com> Reviewed-on: http://git-master/r/165948 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com>
2013-09-14ARM: mm: save/restore some PMU registersBo Yan
Specifically, this change saves and restores registers controlling user space access of ARM performance monitoring unit registers and for PMU interrupt enables. Change-Id: Iac88df17112e2ef2ccf53674c3fa3a74d2d4221f Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/162149 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit
2013-09-14ARM: mm: Add support for ARM debug arch v7.1Scott Williams
Bug 885613 Change-Id: I283f0ed737951e16fbf1cd9b0d0e1f2bc568bf49 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/88856 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Rebase-Id: Rd8b2eb11fc71ec2c55f18403b56de1227ead113f
2013-09-14unknown changes from android-tegra-nv-3.4Dan Willemsen
Rebase-Id: R940fad74c7e91ef3d1d3d589a48064ccb7335541
2013-09-14arm: tegra: add Trusted Foundations hooks and driverChris Johnson
Add CONFIG_TRUSTED_FOUNDATIONS build option and calls to issue SMCs to the TL secure monitor (used when needing to update state not writable by non-secure code). Make security/tf_driver an optional part of the build, which is part of the TL framework to interact with secure services. Bug 883391 Change-Id: I9c6c14ff457fb3a0c612d558fe731a17c2480750 Signed-off-by: Chris Johnson <cwj@nvidia.com> Reviewed-on: http://git-master/r/65616 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R57977499bb6b372ac4faa360e442e8733265e9f3
2013-09-14ARM: errata: 716044: an uncacheable load multiple can cause a deadlock.Krishna Reddy
Under some rare circumstances, an uncacheable load multiple instruction (LDRD, LDM, VLDM, VLD1, VLD2, VLD3, VLD4) can cause a processor deadlock. Change-Id: Ibd79aa8182dce37d0be9892f2310735e1123618a Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/95914 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R87f0be6dfa8d8ac812cb46deb8c4466f622e580c
2013-09-14ARM: mm: Implement complete debug arch v7 save/restoreScott Williams
Implement the complete debug arch v7 save/restore sequence as required by the ARM Architectural Reference Manual. Change-Id: Ia346a87b16e759ae5dbbbd02e77eda1e6d6deb82 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/87865 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Rebase-Id: R961728bfc7e7e0e28c963ee8009fb047e79e8649
2013-09-14ARM: mm: Make CPU debug context save/restore optionalScott Williams
Change-Id: I5a5a26c6fc0a169a004307e07de1223c107e4df7 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/86158 Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Tested-by: Gerrit_Virtual_Submit Rebase-Id: Rf3af25a6871f92887c3e83d0eb1b1ceb64895485
2013-09-14ARM: errata: 752520: Faulty arbitration between PLD and Cacheable TLB ↵vdumpa
requests may create a system deadlock. Under rare circumstances, PLDs may interfere with a Cacheable page table walk, creating a processor deadlock. The erratum can only happen when the Data Cache and MMU are enabled, with the TLB descriptors marked as L1 cacheable, so that Page Table Walks are performed as cache linefills. This workaround sets a bit in the diagnostic register of the Cortex-A9, causing PLD operations treated as NOP. (cherry-picked from b501cafea7328bc578f67e3e846ab9d25b7ec1b0) Change-Id: Ic4039b83de43530bae7ce705162441bea74e1e98 Reviewed-on: http://git-master/r/54095 Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Tested-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: Ra35e48e21c1d62b6480a9d67d1413dd5d0df3f53
2013-09-14ARM: v7: Save CP14 registers across suspendScott Williams
Change-Id: I48bd9ddf9f0a65b1754560bae261d0b3faa69e06 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rbbd2387b98c81919b3a8bf9782828c8b4ef33f45
2013-09-14ARM: v7: Save CP15 diagnostic register across suspendScott Williams
Change-Id: I7d0efeb53e41722f92f9373785045ccc61e56adf Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R6ab8cf0cfe2930330b49d3fccee65d8366ef909d
2013-09-14ARM: Cortex-A9: Enable dynamic clock gatingDan Willemsen
Enable dynamic high level clock gating for Cortex-A9 CPUs, as described in 2.3.3 "Dynamic high level clock gating" of the Cortex-A9 TRM. This may cut the clock of the integer core, system control block, and Data Engine in certain conditions. Add ARM errata 720791 to avoid corrupting the Jazelle instruction stream on earlier Cortex-A9 revisions. Original-Change-Id: I48e51d907e593f26982ea91b0a811553f68e3c86 Signed-off-by: Todd Poynor <toddpoynor@google.com> Rebase-Id: R7ae4d4825e9171bca2471fe776ecf363e75b9ca6
2013-08-11ARM: 7784/1: mm: ensure SMP alternates assemble to exactly 4 bytes with Thumb-2Will Deacon
commit bf3f0f332f76a85ff3a0b393aaded5a8533769c0 upstream. Commit ae8a8b9553bd ("ARM: 7691/1: mm: kill unused TLB_CAN_READ_FROM_L1_CACHE and use ALT_SMP instead") added early function returns for page table cache flushing operations on ARMv7 SMP CPUs. Unfortunately, when targetting Thumb-2, these `mov pc, lr' sequences assemble to 2 bytes which can lead to corruption of the instruction stream after code patching. This patch fixes the alternates to use wide (32-bit) instructions for Thumb-2, therefore ensuring that the patching code works correctly. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-06-24ARM: 7773/1: PJ4B: Add support for errata 4742Gregory CLEMENT
This commit fixes the regression on Armada 370 (the kernal hang during boot) introduced by the commit: "ARM: 7691/1: mm: kill unused TLB_CAN_READ_FROM_L1_CACHE and use ALT_SMP instead". When coming out of either a Wait for Interrupt (WFI) or a Wait for Event (WFE) IDLE states, a specific timing sensitivity exists between the retiring WFI/WFE instructions and the newly issued subsequent instructions. This sensitivity can result in a CPU hang scenario. The workaround is to insert either a Data Synchronization Barrier (DSB) or Data Memory Barrier (DMB) command immediately after the WFI/WFE instruction. This commit was based on the work of Lior Amsalem, but heavily modified to apply the errata fix dynamically according to the processor type thanks to the suggestions of Russell King and Nicolas Pitre. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org> Tested-by: Willy Tarreau <w@1wt.eu> Cc: <stable@vger.kernel.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-06-17ARM: 7754/1: Fix the CPU ID and the mask associated to the PJ4BGregory CLEMENT
This commit fixes the ID and mask for the PJ4B which was too restrictive and didn't match the CPU of the Armada 370 SoC. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Cc: <stable@vger.kernel.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-05-02Merge branches 'devel-stable', 'entry', 'fixes', 'mach-types', 'misc' and ↵Russell King
'smp-hotplug' into for-linus
2013-04-17ARM: 7695/1: mvebu: Enable pj4b on LPAE compilationsGregory CLEMENT
pj4b cpus are LPAE capable so enable them on LPAE compilations Signed-off-by: Lior Amsalem <alior@marvell.com> Tested-by: Franklin <flin@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-04-03ARM: 7691/1: mm: kill unused TLB_CAN_READ_FROM_L1_CACHE and use ALT_SMP insteadWill Deacon
Many ARMv7 cores have hardware page table walkers that can read the L1 cache. This is discoverable from the ID_MMFR3 register, although this can be expensive to access from the low-level set_pte functions and is a pain to cache, particularly with multi-cluster systems. A useful observation is that the multi-processing extensions for ARMv7 require coherent table walks, meaning that we can make use of ALT_SMP patching in proc-v7-* to patch away the cache flush safely for these cores. Reported-by: Albin Tonnerre <Albin.Tonnerre@arm.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-03-22ARM: 7678/1: Work around faulty ISAR0 register in some Krait CPUsStepan Moskovchenko
Some early versions of the Krait CPU design incorrectly indicate that they only support the UDIV and SDIV instructions in Thumb mode when they actually support them in ARM and Thumb mode. It seems that these CPUs follow the DDI0406B ARM ARM which has two possible values for the divide instructions field, instead of the DDI0406C document which has three possible values. Work around this problem by checking the MIDR against Krait CPUs with this faulty ISAR0 register and force the hwcaps to indicate support in both modes. [sboyd: Rewrote commit text to reflect real reasoning now that we autodetect udiv/sdiv] Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-03-22ARM: 7680/1: Detect support for SDIV/UDIV from ISAR0 registerStephen Boyd
The ISAR0 register indicates support for the SDIV and UDIV instructions in both the Thumb and ARM instruction set. Read the register to detect the supported instructions and update the elf_hwcap mask as appropriate. This is better than adding more and more cpuid checks in proc-v7.S for each new cpu variant that supports these instructions. Acked-by: Will Deacon <will.deacon@arm.com> Cc: Stepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-01-06ARM: 7614/1: mm: fix wrong branch from Cortex-A9 to PJ4bHaojian Zhuang
If CONFIG_ARCH_MULTIPLATFORM & CONFIG_ARCH_MVEBU are both enabled, __v7_pj4b_setup is added between __v7_ca9mp_setup and __v7_setup. But there's no jump instruction added. If the chip is Cortex A5/A9, it goes through __v7_pj4b_setup also. It results in system hang. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-01-02ARM: 7609/1: disable errata work-arounds which access secure registersRob Herring
In order to support secure and non-secure platforms in multi-platform kernels, errata work-arounds that access secure only registers need to be disabled. Make all the errata options that fit in this category depend on !CONFIG_ARCH_MULTIPLATFORM. This will effectively remove the errata options as platforms are converted over to multi-platform. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2012-12-14Merge tag 'mvebu' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds
Pull ARM SoC updates for Marvell mvebu/kirkwood from Olof Johansson: "This is a branch with updates for Marvell's mvebu/kirkwood platforms. They came in late-ish, and were heavily interdependent such that it didn't make sense to split them up across the cross-platform topic branches. So here they are (for the second release in a row) in a branch on their own." * tag 'mvebu' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (88 commits) arm: l2x0: add aurora related properties to OF binding arm: mvebu: add Aurora L2 Cache Controller to the DT arm: mvebu: add L2 cache support dma: mv_xor: fix error handling path dma: mv_xor: fix error checking of irq_of_parse_and_map() dma: mv_xor: use request_irq() instead of devm_request_irq() dma: mv_xor: clear the window override control registers arm: mvebu: fix address decoding armada_cfg_base() function ARM: mvebu: update defconfig with I2C and RTC support ARM: mvebu: Add SATA support for OpenBlocks AX3-4 ARM: mvebu: Add support for the RTC in OpenBlocks AX3-4 ARM: mvebu: Add support for I2C on OpenBlocks AX3-4 ARM: mvebu: Add support for I2C controllers in Armada 370/XP arm: mvebu: Add hardware I/O Coherency support arm: plat-orion: Add coherency attribute when setup mbus target arm: dma mapping: Export a dma ops function arm_dma_set_mask arm: mvebu: Add SMP support for Armada XP arm: mm: Add support for PJ4B cpu and init routines arm: mvebu: Add IPI support via doorbells arm: mvebu: Add initial support for power managmement service unit ...
2012-11-21arm: mm: Add support for PJ4B cpu and init routinesGregory CLEMENT
PJ4B is an implementation of the ARMv7 (such as the Cortex A9 for example) released by Marvell. This CPU is currently found in Armada 370 and Armada XP SoCs. This patch provides a support for the specific initialization of this CPU. Signed-off-by: Yehuda Yitschak <yehuday@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
2012-10-18ARM: 7553/1: proc-v7: Ensure correct instruction set after cpu_resetDave Martin
Because mov pc,<Rn> never switches instruction set when executed in Thumb code, Thumb-2 kernels will silently execute the target code after cpu_reset as Thumb code, even if the passed code pointer denotes ARM (bit 0 clear). This patch uses bx instead, ensuring the correct instruction set for the target code. Thumb code in the kernel is not supported prior to ARMv7, so other CPUs are not affected. Signed-off-by: Dave Martin <dave.martin@linaro.org> Acked-by: Will Deacon <will.deacon@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2012-09-25ARM: mm: update __v7_setup() to the new LoUIS cache maintenance APISantosh Shilimkar
The ARMv7 processor setup function __v7_setup() cleans and invalidates the CPU cache before enabling MMU to start the CPU with a clean CPU local cache. But on ARMv7 architectures like Cortex-[A15/A8], this code will end up flushing the L2 caches(up to level of Coherency) which is undesirable and expensive. The setup functions are used in the CPU hotplug scenario too and hence flushing all cache levels should be avoided. This patch replaces the cache flushing call with the newly introduced v7 dcache LoUIS API where only cache levels up to LoUIS are cleaned and invalidated when a processors executes __v7_setup which is the expected behavior. For processors like A9 and A5 where the L2 cache is an outer one the behavior should be unchanged. Reviewed-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Shawn Guo <shawn.guo@linaro.org>
2012-04-15ARM: 7384/1: ThumbEE: Disable userspace TEEHBR access for !CONFIG_ARM_THUMBEEJonathan Austin
Currently when ThumbEE is not enabled (!CONFIG_ARM_THUMBEE) the ThumbEE register states are not saved/restored at context switch. The default state of the ThumbEE Ctrl register (TEECR) allows userspace accesses to the ThumbEE Base Handler register (TEEHBR). This can cause unexpected behaviour when people use ThumbEE on !CONFIG_ARM_THUMBEE kernels, as well as allowing covert communication - eg between userspace tasks running inside chroot jails. This patch sets up TEECR in order to prevent user-space access to TEEHBR when !CONFIG_ARM_THUMBEE. In this case, tasks are sent SIGILL if they try to access TEEHBR. Cc: stable@vger.kernel.org Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Jonathan Austin <jonathan.austin@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2012-02-27ARM: 7345/1: errata: update workaround for A9 erratum #743622Will Deacon
Erratum #743622 affects all r2 variants of the Cortex-A9 processor, so ensure that the workaround is applied regardless of the revision. Cc: <stable@vger.kernel.org> Reported-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2012-01-23ARM: 7296/1: proc-v7.S: remove HARVARD_CACHE preprocessor guardsWill Deacon
On v7, we use the same cache maintenance instructions for data lines as for unified lines. This was not the case for v6, where HARVARD_CACHE was defined to indicate the L1 cache topology. This patch removes the erroneous compile-time check for HARVARD_CACHE in proc-v7.S, ensuring that we perform I-side invalidation at boot. Reported-and-Acked-by: Shawn Guo <shawn.guo@linaro.org> Cc: stable <stable@vger.kernel.org> Acked-by: Catalin Marinas <Catalin.Marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2012-01-23ARM: 7295/1: cortex-a7: move proc_info out of !CONFIG_ARM_LPAE blockWill Deacon
The merging of commits 1b6ba46b ("ARM: LPAE: MMU setup for the 3-level page table format") and b4244738 ("ARM: 7202/1: Add Cortex-A7 proc info") during the merge window ended up putting the Cortex-A7 proc_info into a code block guarded by !CONFIG_ARM_LPAE. This makes Cortex-A7 platforms unbootable when LPAE is enabled. This patch moves the proc_info structure for Cortex-A7 outside of the guarded block. Cc: Pawel Moll <pawel.moll@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2012-01-05Merge branch 'devel-stable' into for-linusRussell King
Conflicts: arch/arm/kernel/setup.c arch/arm/mach-shmobile/board-kota2.c
2012-01-05Merge branches 'fixes' and 'misc' into for-linusRussell King
2011-12-23ARM: 7197/1: errata: Remove SMP dependency for erratum 751472Dave Martin
Activation conditions for a workaround should not be encoded in the workaround's direct dependencies if this makes otherwise reasonable configuration choices impossible. This patches uses the SMP/UP patching facilities instead to compile out the workaround if the configuration means that it is definitely not needed. This means that configs for buggy silicon can simply select ARM_ERRATA_751472, without preventing a UP kernel from being built or duplicatiing knowledge about when to activate the workaround. This seems the correct way to do things, because the erratum is a property of the silicon, irrespective of what the kernel config happens to be. Signed-off-by: Dave Martin <dave.martin@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-12-11ARM: 7202/1: Add Cortex-A7 proc infoPawel Moll
This patch adds processor info for ARM Ltd. Cortex-A7. A7 is architecturally identical to A15 so it shares the same SMP initialization code and hwcaps. Tested-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Pawel Moll <pawel.moll@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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