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2019-12-21arm64: tegra: Fix 'active-low' warning for Jetson TX1 regulatorJon Hunter
commit 1e5e929c009559bd7e898ac8e17a5d01037cb057 upstream. Commit 34993594181d ("arm64: tegra: Enable HDMI on Jetson TX1") added a regulator for HDMI on the Jetson TX1 platform. This regulator has an active high enable, but the GPIO specifier for enabling the regulator incorrectly defines it as active-low. This causes the following warning to occur on boot ... WARNING KERN regulator@10 GPIO handle specifies active low - ignored The fixed-regulator binding does not use the active-low flag from the gpio specifier and purely relies of the presence of the 'enable-active-high' property to determine if it is active high or low (if this property is omitted). Fix this warning by setting the GPIO to active-high in the GPIO specifier which aligns with the presense of the 'enable-active-high' property. Fixes: 34993594181d ("arm64: tegra: Enable HDMI on Jetson TX1") Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-11-25arm64: dts: tegra210-p2180: Correct sdmmc4 vqmmc-supplyAapo Vienamo
[ Upstream commit 6ff7705da8806de45ca1490194f0b4eb07725804 ] On p2180 sdmmc4 is powered from a fixed 1.8 V regulator. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-08-04arm64: tegra: Fix AGIC register rangeJon Hunter
commit ba24eee6686f6ed3738602b54d959253316a9541 upstream. The Tegra AGIC interrupt controller is an ARM GIC400 interrupt controller. Per the ARM GIC device-tree binding, the first address region is for the GIC distributor registers and the second address region is for the GIC CPU interface registers. The address space for the distributor registers is 4kB, but currently this is incorrectly defined as 8kB for the Tegra AGIC and overlaps with the CPU interface registers. Correct the address space for the distributor to be 4kB. Cc: stable@vger.kernel.org Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Fixes: bcdbde433542 ("arm64: tegra: Add AGIC node for Tegra210") Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-08-04arm64: tegra: Update Jetson TX1 GPU regulator timingsJon Hunter
commit ece6031ece2dd64d63708cfe1088016cee5b10c0 upstream. The GPU regulator enable ramp delay for Jetson TX1 is set to 1ms which not sufficient because the enable ramp delay has been measured to be greater than 1ms. Furthermore, the downstream kernels released by NVIDIA for Jetson TX1 are using a enable ramp delay 2ms and a settling delay of 160us. Update the GPU regulator enable ramp delay for Jetson TX1 to be 2ms and add a settling delay of 160us. Cc: stable@vger.kernel.org Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Fixes: 5e6b9a89afce ("arm64: tegra: Add VDD_GPU regulator to Jetson TX1") Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-01-09arm64: tegra: Add VDD_GPU regulator to Jetson TX1Alexandre Courbot
commit 5e6b9a89afceadb1ee45472098f7d20af260335c upstream. Add the VDD_GPU regulator (a GPIO-enabled PWM regulator) to the Jetson TX1 board. This addition allows the GPU to be used provided the bootloader properly enabled the GPU node. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> [as pointed out by Thierry on IRC, nobody has reported a bug in the field, but using a new bootloader with a .dtb that has the incorrect data, it will crash on boot] Fixes: 336f79c7b6d7 ("arm64: tegra: Add NVIDIA Jetson TX1 Developer Kit support") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2016-10-12Merge branch 'next' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linux Pull thermal managament updates from Zhang Rui: - Enhance thermal "userspace" governor to export the reason when a thermal event is triggered and delivered to user space. From Srinivas Pandruvada - Introduce a single TSENS thermal driver for the different versions of the TSENS IP that exist, on different qcom msm/apq SoCs'. Support for msm8916, msm8960, msm8974 and msm8996 families is also added. From Rajendra Nayak - Introduce hardware-tracked trip points support to the device tree thermal sensor framework. The framework supports an arbitrary number of trip points. Whenever the current temperature is changed, the trip points immediately below and above the current temperature are found, driver callback is invoked to program the hardware to get notified when either of the two trip points are triggered. Hardware-tracked trip points support for rockchip thermal driver is also added at the same time. From Sascha Hauer, Caesar Wang - Introduce a new thermal driver, which enables TMU (Thermal Monitor Unit) on QorIQ platform. From Jia Hongtao - Introduce a new thermal driver for Maxim MAX77620. From Laxman Dewangan - Introduce a new thermal driver for Intel platforms using WhiskeyCove PMIC. From Bin Gao - Add mt2701 chip support to MTK thermal driver. From Dawei Chien - Enhance Tegra thermal driver to enable soctherm node and set "critical", "hot" trips, for Tegra124, Tegra132, Tegra210. From Wei Ni - Add resume support for tango thermal driver. From Marc Gonzalez - several small fixes and improvements for rockchip, qcom, imx, rcar, mtk thermal drivers and thermal core code. From Caesar Wang, Keerthy, Rocky Hao, Wei Yongjun, Peter Robinson, Bui Duc Phuc, Axel Lin, Hugh Kang * 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linux: (48 commits) thermal: int3403: Process trip change notification thermal: int340x: New Interface to read trip and notify thermal: user_space gov: Add additional information in uevent thermal: Enhance thermal_zone_device_update for events arm64: tegra: set hot trips for Tegra210 arm64: tegra: set critical trips for Tegra210 arm64: tegra: add soctherm node for Tegra210 arm64: tegra: set hot trips for Tegra132 arm64: tegra: set critical trips for Tegra132 arm64: tegra: use tegra132-soctherm for Tegra132 arm: tegra: set hot trips for Tegra124 arm: tegra: set critical trips for Tegra124 thermal: tegra: add hw-throttle for Tegra132 thermal: tegra: add hw-throttle function of: Add bindings of hw throttle for Tegra soctherm thermal: mtk_thermal: Check return value of devm_thermal_zone_of_sensor_register thermal: Add Mediatek thermal driver for mt2701. dt-bindings: thermal: Add binding document for Mediatek thermal controller thermal: max77620: Add thermal driver for reporting junction temp thermal: max77620: Add DT binding doc for thermal driver ...
2016-09-27arm64: tegra: set hot trips for Tegra210Wei Ni
Enable throttle function for SOC_THERM. Set "hot" trips for cpu and gpu thermal zones, which can trigger the SOC_THERM hardware throttle. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
2016-09-27arm64: tegra: set critical trips for Tegra210Wei Ni
Set general "critical" trip temperatures for cpu, gpu, mem and pllx thermal zones on Tegra210, these trips can trigger shut down or reset. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
2016-09-27arm64: tegra: add soctherm node for Tegra210Wei Ni
Adds soctherm node for Tegra210, and add cpu, gpu, mem, pllx as thermal-zones. Set critical trip temperatures for them. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
2016-09-27arm64: tegra: set hot trips for Tegra132Wei Ni
Enable throttle function for SOC_THERM. Set "hot" trips for cpu and gpu thermal zones, which can trigger the SOC_THERM hardware throttle. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
2016-09-27arm64: tegra: set critical trips for Tegra132Wei Ni
Set general "critical" trip temperatures for cpu, gpu, mem and pllx thermal zones on Tegra132, these trips can trigger shut down or reset. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
2016-09-27arm64: tegra: use tegra132-soctherm for Tegra132Wei Ni
The Tegra132 has the specific settings for soctherm, so change to use campatible "nvidia,tegra132-soctherm" for it. And adds cpu, gpu, mem and pllx thermal zones. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
2016-08-24arm64: tegra: Enable XUSB controller on Tegra210 SmaugJon Hunter
Enable the XUSB controller on Tegra210 Smaug. The Smaug has a USB Type-C connector with one of the USB2.0 lanes and one of the USB3.0 lanes populated. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-08-24arm64: tegra: Add the various audio devices for Tegra210 SmaugJon Hunter
The Tegra210 Smaug includes the Realtek RT5677 audio codec, Nuvoton NAU8825 headset codec and the Maxim MAX98357a audio amplifier. Add the nodes for these devices for the Tegra210 Smaug. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> [treding@nvidia.com: use interrupts property consistently] Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-08-24arm64: tegra: Enable DPAUX for Tegra210 SmaugJon Hunter
The Tegra210 Smaug uses I2C6 for interfacing to various audio chips. I2C6 shares pads with the DPAUX interface and to allow I2C6 to request the pads owned by DPAUX, the DPAUX device needs to be enabled. Enable DPAUX for Tegra210 Smaug. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-08-24arm64: tegra: Add ACONNECT, ADMA and AGIC nodes Tegra210 SmaugJon Hunter
Populate the ACONNECT, ADMA and AGIC nodes for Tegra210 Smaug which are used for audio use-cases. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-08-24arm64: tegra: Add SOR power-domain for Tegra210Jon Hunter
Add node for SOR power-domain for Tegra210 and populate the SOR power-domain phandle for DPAUX, DSI, MIPI-CAL and SOR and nodes that are dependent on this power-domain. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-08-24arm64: tegra: Add ADMA node for Tegra210Jon Hunter
Populate the ADMA node for Tegra210. The ADMA is used by the Audio Processing Engine (APE) on Tegra210 for moving data between the APE and system memory. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-08-24arm64: tegra: Add AGIC node for Tegra210Jon Hunter
Populate the Audio GIC (AGIC) node for Tegra210. This interrupt controller is used by the Audio Processing Engine to route interrupts to the main CPU interrupt controller. The AGIC is based on the ARM GIC400 and so uses the clock name "clk" as specified by the GIC binding document for GIC400 devices. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-08-24arm64: tegra: Drop clock and reset names for XUSB powergatesJon Hunter
Drop the clock and reset names for the Tegra210 XUSB powergates because these are not currently used and not required by the Tegra PMC binding documentation. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-08-16arm64: tegra: Simplify Tegra210 GPIO compatible valueStephen Warren
The compatible value need only include an entry for the specific HW generation, plus the oldest HW version that introduced changes it is backwards-compatible with; intermediate versions aren't necessary. Since Tegra124 GPIO is backwards-compatible with Tegra30 GPIO, there's no need to include the Tegra124 value in the Tegra210 DTS. This makes the kernel DT better match the copy of the DT files included in U-Boot. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-14arm64: tegra: Enable HDMI on Jetson TX1Thierry Reding
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-14arm64: tegra: Add sor1_src clockThierry Reding
The sor1 IP block needs the sor1_src clock to configure the clock tree depending on whether it's running in HDMI or DP mode. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-14arm64: tegra: Add XUSB powergates on Tegra210Jon Hunter
The Tegra210 XUSB subsystem has 3 power partitions which are XUSBA (super-speed logic), XUSBB (USB device logic) and XUSBC (USB host logic). Populate the device-tree nodes for these XUSB partitions. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-14arm64: tegra: Add DPAUX pinctrl bindingsJon Hunter
Add the DPAUX pinctrl states for the DPAUX nodes defining all three possible states of "aux", "i2c" and "off". Also add the 'i2c-bus' node for the DPAUX nodes so that the I2C driver core does not attempt to parse the pinctrl state nodes. Populate the nodes for the pinctrl clients of the DPAUX pin controller. There are two clients for each DPAUX instance, namely the SOR and one of the I2C adapters. The SOR clients may used the DPAUX pins in either AUX or I2C modes and so for these devices we don't define any of the generic pinctrl states (default, idle, etc) because the SOR driver will directly set the state needed. For I2C clients only the I2C mode is used and so we can simplify matters by using the generic pinctrl states for default and idle. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-14arm64: tegra: Add ACONNECT bus node for Tegra210Jon Hunter
Add the ACONNECT bus node for Tegra210 which is used to interface to the various devices in the Audio Processing Engine (APE). Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-14arm64: tegra: Add audio powergate node for Tegra210Jon Hunter
Add the audio powergate for Tegra210. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-14arm64: tegra: Add regulators for Tegra210 SmaugRhyland Klein
Add regulators to the Tegra210 Smaug DTS file including support for the MAX77620 PMIC. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Acked-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-14arm64: tegra: Correct Tegra210 XUSB mailbox interruptJon Hunter
The XUSB mailbox interrupt for Tegra210 is 40 and not 49 which is for the XUSB pad controller. For some Tegra210 boards, this is causing USB connect and disconnect events to go undetected. Fix this by changing the interrupt number for the XUSB mailbox to 40. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-14arm64: tegra: Enable XUSB controller on Jetson TX1Thierry Reding
Enable the XUSB controller on Jetson TX1. One of the USB 3.0 lanes goes to an internal ethernet interface, while a second USB 3.0 lane supports the USB-A receptacle on the I/O board. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-14arm64: tegra: Enable debug serial on Jetson TX1Thierry Reding
Add a chosen node to the device tree that contains a stdout-path property which defines the debug serial port. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-14arm64: tegra: Add Tegra210 XUSB controllerThierry Reding
Add a device tree node for the Tegra XUSB controller. It contains a phandle to the XUSB pad controller for control of the PHYs assigned to the USB ports. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-14arm64: tegra: Add Tegra210 XUSB pad controllerThierry Reding
Add a device tree node for the XUSB pad controller found on Tegra210. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-14arm64: tegra: Add DSI panel on Jetson TX1Thierry Reding
Some variants of the Jetson TX1 ship with a 8.0" WUXGA TFT LCD panel connected via four DSI lanes. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-14arm64: tegra: p2597: Add SDMMC power suppliesThierry Reding
Add power supplies for the SD/MMC card slot. Note that vmmc-supply is currently restricted to 3.3 V because we don't support switching the mode yet. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-14arm64: tegra: Add PMIC support on Jetson TX1Thierry Reding
Add a device tree node for the MAX77620 PMIC found on the p2180 processor module (Jetson TX1). Also add supporting power supplies, such as the main 5 V system supply. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-05-10Merge tag 'tegra-for-4.7-gm20b' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt64 Merge "arm64: tegra: Enable GM20B GPU on Tegra210" from Thierry Reding: Complement the GM20B GPU device tree node on Tegra210 with missing properties to make it usable. * tag 'tegra-for-4.7-gm20b' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: arm64: tegra: Add IOMMU node to GM20B on Tegra210 arm64: tegra: Add reference clock to GM20B on Tegra210 dt-bindings: Add documentation for GM20B GPU dt-bindings: gk20a: Document iommus property dt-bindings: gk20a: Fix typo in compatible name
2016-04-26arm64: tegra: Add IOMMU node to GM20B on Tegra210Alexandre Courbot
The operating system driver can take advantage of the IOMMU to remove the need for physically contiguous memory buffers. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-26arm64: tegra: Add reference clock to GM20B on Tegra210Alexandre Courbot
This clock is required for the GPU to operate. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-15arm64: tegra: Enable cros-ec and charger on SmaugRhyland Klein
Add nodes for the ChromeOS Embedded Controller and for the gas gauge connected to the I2C bus that it controls. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-12arm64: tegra: Add pinmux for Smaug boardRhyland Klein
Add pinmux node for Tegra210 Smaug board. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11arm64: tegra: Add stdout-path for various boardsJon Hunter
For Tegra boards, the device-tree alias serial0 is used for the console and so add the stdout-path information so that the console no longer needs to be passed via the kernel boot parameters. For tegra132-norrin the alias serial0 is not defined and so add this. This has been tested on tegra132-norrin and tegra210-p2371-0000. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11arm64: tegra: Remove unused #power-domain-cells propertyJon Hunter
Remove the "#power-domain-cells" property which was incorrectly included by commit e53095857166 ("arm64: tegra: Add Tegra210 support"). Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11arm64: tegra: Add gpio-keys nodes for SmaugRhyland Klein
Add gpio-keys nodes for the volumn controls, lid switch, tablet mode and power button. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Reviewed-by: Andrew Bresticker <abrestic@chromium.org> [treding@nvidia.com: use symbolic names for input types and codes] [treding@nvidia.com: use wakeup-source instead of gpio-key,wakeup] Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11arm64: tegra: Enable power and volume keys on Jetson TX1Laxman Dewangan
Add a gpio-keys device tree node to represent the Power, Volume Up and Volume Down keys found on Jetson TX1. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11arm64: tegra: Add support for Google Pixel CJon Hunter
Add initial device-tree support for Google Pixel C (a.k.a. Smaug) based upon Tegra210 SoC with 3 GiB of LPDDR4 RAM. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Alexandre Courbot <acourbot@nvidia.com> Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Tested-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11arm64: tegra: Replace legacy *,wakeup property with wakeup-sourceSudeep Holla
Though the keyboard and other driver will continue to support the legacy "gpio-key,wakeup", "nvidia,wakeup-source" boolean property to enable the wakeup source, "wakeup-source" is the new standard binding. This patch replaces all the legacy wakeup properties with the unified "wakeup-source" property in order to avoid any further copy-paste duplication. Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Alexandre Courbot <gnurou@gmail.com> Cc: linux-tegra@vger.kernel.org Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11arm64: tegra: Fix copy/paste typo in several DTS includesThierry Reding
The comment about the 8250 vs. APB DMA-enabled UART devices that was added for Tegra20 and Tegra30 in commit b6551bb933f9 ("ARM: tegra: dts: add aliases and DMA requestor for serial controller") introduced a typo that has since spread to various other DTS include files. Fix all occurrences of this typo. Suggested-by: Ralf Ramsauer <ralf@ramses-pyramidenbau.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11arm64: tegra: Remove 0, prefix from unit-addressesThierry Reding
When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-03-04arm64: Fix misspellings in comments.Adam Buchbinder
Signed-off-by: Adam Buchbinder <adam.buchbinder@gmail.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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