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Do not disable and re-enable clocks after deasserting
PCIE, AFI and PCIEX resets. Deasserting the resets should
be followed by programming the PCIE.
Bug 1521306
Change-Id: Idc43bc9b21cac3818852ed059fe512f4cd75b748
Signed-off-by: Shreshtha SAHU <ssahu@nvidia.com>
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Commit 455bd4c430b0 ("ARM: 7668/1: fix memset-related crashes caused by
recent GCC (4.7.2) optimizations") attempted to fix a compliance issue
with the memset return value. However the memset itself became broken
by that patch for misaligned pointers.
This fixes the above by branching over the entry code from the
misaligned fixup code to avoid reloading the original pointer.
Also, because the function entry alignment is wrong in the Thumb mode
compilation, that fixup code is moved to the end.
While at it, the entry instructions are slightly reworked to help dual
issue pipelines.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Tested-by: Alexander Holler <holler@ahsoftware.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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optimizations
Recent GCC versions (e.g. GCC-4.7.2) perform optimizations based on
assumptions about the implementation of memset and similar functions.
The current ARM optimized memset code does not return the value of
its first argument, as is usually expected from standard implementations.
For instance in the following function:
void debug_mutex_lock_common(struct mutex *lock, struct mutex_waiter *waiter)
{
memset(waiter, MUTEX_DEBUG_INIT, sizeof(*waiter));
waiter->magic = waiter;
INIT_LIST_HEAD(&waiter->list);
}
compiled as:
800554d0 <debug_mutex_lock_common>:
800554d0: e92d4008 push {r3, lr}
800554d4: e1a00001 mov r0, r1
800554d8: e3a02010 mov r2, #16 ; 0x10
800554dc: e3a01011 mov r1, #17 ; 0x11
800554e0: eb04426e bl 80165ea0 <memset>
800554e4: e1a03000 mov r3, r0
800554e8: e583000c str r0, [r3, #12]
800554ec: e5830000 str r0, [r3]
800554f0: e5830004 str r0, [r3, #4]
800554f4: e8bd8008 pop {r3, pc}
GCC assumes memset returns the value of pointer 'waiter' in register r0; causing
register/memory corruptions.
This patch fixes the return value of the assembly version of memset.
It adds a 'mov' instruction and merges an additional load+store into
existing load/store instructions.
For ease of review, here is a breakdown of the patch into 4 simple steps:
Step 1
======
Perform the following substitutions:
ip -> r8, then
r0 -> ip,
and insert 'mov ip, r0' as the first statement of the function.
At this point, we have a memset() implementation returning the proper result,
but corrupting r8 on some paths (the ones that were using ip).
Step 2
======
Make sure r8 is saved and restored when (! CALGN(1)+0) == 1:
save r8:
- str lr, [sp, #-4]!
+ stmfd sp!, {r8, lr}
and restore r8 on both exit paths:
- ldmeqfd sp!, {pc} @ Now <64 bytes to go.
+ ldmeqfd sp!, {r8, pc} @ Now <64 bytes to go.
(...)
tst r2, #16
stmneia ip!, {r1, r3, r8, lr}
- ldr lr, [sp], #4
+ ldmfd sp!, {r8, lr}
Step 3
======
Make sure r8 is saved and restored when (! CALGN(1)+0) == 0:
save r8:
- stmfd sp!, {r4-r7, lr}
+ stmfd sp!, {r4-r8, lr}
and restore r8 on both exit paths:
bgt 3b
- ldmeqfd sp!, {r4-r7, pc}
+ ldmeqfd sp!, {r4-r8, pc}
(...)
tst r2, #16
stmneia ip!, {r4-r7}
- ldmfd sp!, {r4-r7, lr}
+ ldmfd sp!, {r4-r8, lr}
Step 4
======
Rewrite register list "r4-r7, r8" as "r4-r8".
Signed-off-by: Ivan Djelic <ivan.djelic@parrot.com>
Reviewed-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Enable VLAN networking functionality.
While at it also enable some more kernel modules for Apalis T30 PCIe
based devices like the Intel E1000E NICs, Intel IWLAGN Wi-Fi cards,
PCIe serial cards and XHCI based USB 3.0 controllers.
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Use HDA HDMI audio now on Colibri T30 as well allowing for up to 7.1
multi-channel playback. Split board sound initialisation between Apalis
and Colibri T30 in order to distinguish better between default SPDIF
being supported out-of-the-box on Apalis vs. this being an optional
feature for the Colibri. Therefore remove SPDIF for the Colibri T30.
While at it add csus clock required for vi_sensor camera master clock
on Apalis T30 and clk_out_2/extern2 for Colibri T30, fix debug UART1
initialisation, get rid of spurious CONFIG_SND_USB enable and further
clean-up both board platform data files.
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Enable CONFIG_FHANDLE required for systemd >= 209 according to
lists.freedesktop.org/archives/systemd-devel/2014-February/017362.html
While at it put them all 3 on par concerning ARM Errata configuration.
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Fix (Colibri) resp. introduce (Apalis) SPI device controller data to
properly use HW based chip select with one clock of setup and hold time
each for both MCP2515 CAN controller(s) as well as spidev.
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The 1.8V quirk also affected the internal eMMC which disabled newer
modes such as SDR50, SDR104 and DDR50. This in turn lead to an
out of spec usage since the clock was still 50MHz.
By creating a no_1v8 field in the platform data we can now enable
this work around on a per-instance basis. Hence we enable the
quirk only on the controllers which are connected to the external
SD-slots.
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PCIe Reset line must be asserted for at least 100us after clock is enabled.
PEX 2 Controller Register fix, offsets are not at constant intervals.
Bug 1521306
Reviewed-on: http://git-master/r/225399
(cherry picked from commit df0760bf515236bed2e87e590509642ab72a01b5)
Change-Id: I7b44ea51e7e02f2bca93cfc75ed85e01ab91fe03
Signed-off-by: Shreshtha Sahu <ssahu@nvidia.com>
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This commit resolves an issue of non-working vi camera driver
on Colibri T20 occured after a l4t-r16-r4 merge.
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Add SPI controller platform data required for use of hardware chip
selects.
While at it pull-up SPI chip select pin due to NVIDIA's designers
taking the term chip select a little too personal: they indeed only
select a chip otherwise all the chip select pins are just left
floating!
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The MCP2515 on the Colibri EvalBoard V3.1a actually uses regular system
reset aka RESET_OUT# on SODIMM 87 to reset the MCP2515.
Therefore clean-up resp. remove any MECS Tellurium legacy in that
respect.
While at it adjust copyright year, re-order some include, clean-up some
struct spacing, re-order clocks and improve some comments.
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This commit adds settings such as:
- values of horizontal/vertical active start,
- enabling/disabling internal sync,
to the private data of decoders: MAX9526, ADV7180, TVP5150,
OV7670 and AS0260.
The feature is available through *_tegra_camera_platform_data
struct initialised in board-*.c files.
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This commit fixes the crash that occures while loading tegra_v4l2_camera
module caused by its new features (private data per sensor).
updated files:
arch/arm/mach-tegra/board-apalis_t30.c
arch/arm/mach-tegra/board-colibri_t20.c
arch/arm/mach-tegra/board-colibri_t30.c
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This commit fixes the kernel compilation error with the lack
of the export of tegra_powergate_partition symbol in
arch/arm/mach-tegra/powergate.c
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Enable IEEE 1588 precision time protocol (PTP) support.
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Tegra20 and Tegra30 do not support gen2 PCIe, so correct the
register setting to disable it.
Signed-off-by: Eric Brower <ebrower@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Thierry Reding <treding@nvidia.com>
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Conflicts:
drivers/media/video/tegra_v4l2_camera.c
reverted to current driver supporting ACM rather than CSI2
drivers/media/video/videobuf2-dma-nvmap.c
drivers/video/tegra/host/Makefile
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Activate Fusion touchscreen driver. Use GPIO 5/6 as pen down/reset
GPIO and provide a helper function to free the GPIO before the
driver requests them.
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Fusion touchscreen driver now uses platform data to do GPIO
initialization by itself. Make use of this by providing GPIO numbers
instead of doing initialization in the board initialization.
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Allow to change clock polarity for RGB display output using the
keywords outputen/pixclockpol/vsync and hsync. Add them right
after the driver specification, use 0/1 to specifiy high/low
polarity, e.g. video=tegrafb0:pixclockpol:1,800x480
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Remove special clocks for Tegra 2, but use backup clock source
instead. This allows to run all common used resolution within
the drivers -1/+9% allowed band for pixelclock exactness.
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Remove TEGRA_FB_VGA defines and use VGA as default. Since initial
mode is now configureable through kernel cmd line parameter, we
don't need those compile time helpers.
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Use modedb to set mode on framebuffer/display controller for
Tegra 20 based module Colibri T20 too.
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In order to find a viable resolution we not only parse VESA mode,
we also parse CEA (multimedia) modes and our own small modedb (for
specific touch screens).
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Use new modedb based framebuffer settings by defining default_mode
in the display controllers platform data. Also impelmented the
fallback logic to this default_mode in case no kernel cmd line
parameter was set.
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Allow to specify framebufffer videomode using kernel command line
parameters. NVIDIAs binary X driver later on picks up those settings
and start X with current mode settings, if no EDID data are available.
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Disable hardware statistics monitor for AVP due to it completely
hanging upon boot on certain Colibri T20 V1.2a modules.
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Make use of the new STMPE ADC driver to expose the four free ADC
channels on the STMPE811 to userspace.
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The drivers internal root_bus_nr used to be u8 which lead to a wrong
error detection in bus_to_port. Bus number can be -1 in case bus is
not scanned yet. Thanks to James pointing that out.
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The port used for KEY_BACK does not support wakeup (no wake PIN). Remove
the wake flag, this prevents unbalanced irq warning messages.
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Add GPIO keyboard platform device configuration. Currently only the power key
is defined which is registred as wake key as well in order to wake the SoC when
in sleep mode (MXM3 37/WAKE1_MICO).
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SKU 0x81 is identical to 0xB1 so same can be used
for sku to speedo ID conversion.
Bug 1313434
Change-Id: I63f08522878524a05c2a6fb0a82fee90a59a99bd
Signed-off-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-on: http://git-master/r/334396
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
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Remove vdd_hdmi_con regulator from dc1 since we don't have a dedicated
regulator for this connector on our baseboards.
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Use TPS6591X IRQ base define to calculate correct IRQ number.
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Use TPS6591X base defines to make sure the chip gets its own irq range rather
than interfer with the STMPE chip.
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This reverts commit dd9a841da571a41d43f1eeaac1785b2adb1d80f3.
The config changes (for V4L2) can be done manually as per need
basis for V4L2, followed by compiling the kernel.
Change-Id: I9174bce0f3da2974ab703b238dfb8fb3bbf607c5
Signed-off-by: Vikram Fugro <vfugro@nvidia.com>
Reviewed-on: http://git-master/r/327607
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Kaustubh Purandare <kpurandare@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
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- Disables TEGRA_CAMERA
- Enables SOC_CAMERA and OV5640 sensor support
Bug 1369083
Change-Id: I073c226e9f04a6f4f4699051f624a755dceb36cb
Signed-off-by: Vikram Fugro <vfugro@nvidia.com>
Reviewed-on: http://git-master/r/309491
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
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Clean-up GPIO definitions and names (e.g. use LVDS_ defines, BKL1_ON
rather than BL_ON and HDMI1_HPD rather than hdmi_hpd).
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This gives the DDR3L memory settings for 400MHz/800MHz.
The boot memory speed must be 400MHz for this to work, i.e.
the 400MHz BCT must be used.
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If the boot console is RS232 and RX is left floating this leads
to arbitrary sys requests including reboots...
(RX is left floating on the evaluation boards if USB to serial is
jumpered but USB is not connected)
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Enable OV5650 and OV5640 sensor in Cardhu board file with the help of
Tegra V4L2 SoC camera interface.
To use V4L2 driver, we need to disable old camera HAL driver.
Bug 1240806
Bug 1369083
Change-Id: I0dc529d44fba4d80b45690e384e8bf81b29f69e5
Signed-off-by: Bryan Wu <pengw@nvidia.com>
Reviewed-on: http://git-master/r/246266
(cherry picked from commit 6b2f7cc4117208dc992478f27d5873ea38071fdc)
Reviewed-on: http://git-master/r/279988
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Tested-by: Matthew Pedro <mapedro@nvidia.com>
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Configure pll_a during boot so that
locking to pll_a does not fail
Bug 1330751
Change-Id: I188f0be211379f43770b24c5b382dec2788aefda
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/269469
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Kiran Adduri <kadduri@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jong Kim <jongk@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
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DVFS entry is fixed for Hynix_2GB_H5TC4G83MFR-PBA
to support all emc frequencies.
Bug 1218885
Change-Id: Id9d578499e495f43db1a072cbcee25a353fa78f5
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/210653
(cherry picked from commit 688bf04ff67e2c1ff22762f4f578b925ff3b9f3c)
Reviewed-on: http://git-master/r/273530
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Kiran Adduri <kadduri@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Tested-by: Matthew Pedro <mapedro@nvidia.com>
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Up to now only the LVDS transceiver controlling GPIOs were exported.
This patch adds the generic Apalis GPIOs to the list of via sysfs to
userspace exported ones as well.
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Initialisation of the framebuffer console on DVI-D aka HDMI sometimes
failed. This was particularly bad on Apalis T30 where this is activated
by default. On Colibri T30 this was observed when enabling it using the
fbcon=map:1 boot argument.
This fix curtsey of Bibek Basu from NVIDIA explicitly enables PLLA
during early clock initialisation which avoids a later race with the
display driver on DC1.
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