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2011-11-15input: tegra-kbc: Support to configure any pins to row/columnLaxman Dewangan
Any of the KBC GPIO pins can be configured to either as row or as column. Adding support for this. bug 804531 Reviewed-on: http://git-master/r/59927 (cherry picked from commit 59b90aa62766d34290e623fc6e2dfc8fc630af0e) Change-Id: I01100fc6964278940b97428a3df561616f356f2f Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/64034
2011-11-15arm: tegra: Configuring kbc pins as per gpio nrLaxman Dewangan
Configuring the kbc pins such that the row/column is configured in their respective GPIO number. bug 804531 Reviewed-on: http://git-master/r/59942 (cherry picked from commit 8685f95f771c5568e0dba4e444179a2f7412e639) Change-Id: I07c46281f25bdfadb2d35704a507e2ace640a684 Reviewed-on: http://git-master/r/64033 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
2011-11-15ARM: tegra: clock: Return shared_bus_set_rate() errorsAlex Frid
Returned error code from Tegra3 shared_bus_set_rate(). (cherry picked from commit b9aea1656af4d3e17433c82611fe5e7146a41733) Change-Id: Ib3706c61dc911d7bb876f1ddafe52474f79591ec Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/63978 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2011-11-15ARM: tegra: dvfs: Fix dvfs over-voltage error handlingAlex Frid
Record dvfs client voltage rate request only after over-voltage error is checked (otherwise, after over-voltage error rail goes above the limit when another client requests voltage change). (cherry picked from commit 9151f77b545dc5b898ad16ceb695cc57764f94e0) Change-Id: I20b70beadb226980c55feeea5510a52bc155eb73 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/63977 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2011-11-15ARM: tegra: clock: Add Tegra3 emergency throttlingAlex Frid
Add Tegra3 emergency throttling API to directly control G-CPU super clock skipper underneath clock framework, dvfs, and cpufreq driver s/w layers. To be used by system power supply over-current ISR. (cherry picked from commit fca2a12e90684526b2b7aeeb3af31de4254ad939) Change-Id: I8de8f4889d0f6cf6a7cc19a3cc11c6bd9b4fc526 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/63976 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2011-11-15ARM: tegra: dvfs: Update Tegra3 EMC DVFSAlex Frid
- Moved validation of EMC maximum rate against nominal core voltage from common dvfs initialization to board specific EMC scaling table setup (a logical place to do it, since EMC DVFS is board dependent) - Used current rate as rounded EMC rate if no EMC scaling table is provided (instead of maximum EMC rate - no sense in attempt to set maximum rate, or any rate, for that matter, if there is no table). - Cleaned EMC initialization procedure (cherry picked from commit 4f655077e09c0dc4abc50d190d82c91473e2e81c) Change-Id: Ibe5c689db58f0aab3a24eceda1f4b639d073a4dc Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/63975 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2011-11-15arm: tegra: Fix tegra_throttling_enable definitionKrishna Monian
Define tegra_throttling_enable as static instead of NULL to prevent compile errors. Change-Id: If6ff32dc93aaa8bd2564a795c4187e0dd57df0f9 Reviewed-on: http://git-master/r/63435 Reviewed-by: Krishna Monian <kmonian@nvidia.com> Tested-by: Krishna Monian <kmonian@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
2011-11-15arm: tegra: enterprise: Config enable conservative gov on early suspendKarthik Ramakrishnan
Enabling conservative gov for early suspend which is n by default Change-Id: I8bdd2fad82cf7667bb5b0c39738f628d902bae5d Reviewed-on: http://git-master/r/62770 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-11-14arm: tegra: config: Disabling CONFIG_MMC_PARANOID_SD_INITnaveenk
Disabling CONFIG_MMC_PARANOID_SD_INIT Bug 862205 Reviewed-on: http://git-master/r/59916 (cherry picked from commit c9e5705e03363baf9b6e8bfed30d8f00469d89ea) Change-Id: I040ec21d07d9e1c2680530169ba1bdd7c891d610 Reviewed-on: http://git-master/r/62888 Reviewed-by: Naveen Kumar Arepalli <naveenk@nvidia.com> Tested-by: Naveen Kumar Arepalli <naveenk@nvidia.com> Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
2011-11-11ARM: tegra: dvfs: Update Tegra3 AP33 speedo thresholdsDiwakar Tundlam
bugid 841336 Reviewed-on: http://git-master/r/61621 (cherry picked from commit 329035165f483c806f83831a8a5b4eff126b1ac8) Change-Id: I80cedc3391786570cbb24ec3bfc59e729abde795 Reviewed-on: http://git-master/r/62768 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
2011-11-11ARM: Tegra: power: T33 SKU EDP table for 10A regulatorDiwakar Tundlam
bug 841336 Change-Id: I0e0d88c2bcfd7ee4b774adc1bc4c8eff47d4ac29 Reviewed-on: http://git-master/r/60762 (cherry picked from commit 3e74aa621439db78500a8fb07d0fe4620ba3ad05) Reviewed-on: http://git-master/r/62766 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
2011-11-11tegra: NOR: Add NOR platform deviceManoj Chourasia
Added NOR platform device for Tegra. Change-Id: Id32e5d41862b2eccf1b49b953387de16302d6056 Reviewed-on: http://git-master/r/56895 Tested-by: Manoj Chourasia <mchourasia@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
2011-11-11tegra: NOR: Pass timing register value from platfom dataManoj Chourasia
Get timing register value from platform data instead of timing structure. Fix NOR device registration using tegra_nor_device. Signed-off-by: Manoj Chourasia <mchouraia@nvidia.com> Change-Id: I4ece8b149df1bc7ad41e8be3dc3e415b18a44072 Reviewed-on: http://git-master/r/56889 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-11-11tegra: NOR: Allow mapping NOR aperture and clocks.Manoj Chourasia
Renamed client driver for nor clock from "nor" to "tegra-nor". Add NOR flash aperature as valid address range in ioremap. Change-Id: Ib5e896996da5cbf3d31e1c3c31d8250bb0c0a3c4 Reviewed-on: http://git-master/r/44746 Tested-by: Manoj Chourasia <mchourasia@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
2011-11-10ARM: tegra: enable DVFS without EMC SCALINGJong Kim
Enable both CPU_DVFS and CORE_DVFS leaving EMC_SCALING OFF for Tegra2. EMC_SCALING makes graphics flaky on Ventana. BUG 899233 Change-Id: Icaa78f76c1c770ce268dd481d37c4c3b3a313df1 Signed-off-by: Jong Kim <jongk@nvidia.com> Reviewed-on: http://git-master/r/63619 Reviewed-by: Winnie Hsu <whsu@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2011-11-10ARM: tegra: enterprise: remove panel reset in first kernel bootMin-wuk Lee
Panel reset in the first kernel boot is removed because this makes short flicker in transition from bootloader display to kernel display. Panel reset in system resume is still remained. Bug 874071 Reviewed-on: http://git-master/r/53695 (cherry picked from commit 8d3412cfe2dd1d135209f8060f883fdc85571d8e) Change-Id: I78c1d3f07d7ef6eada3b5981218ab609532c3964 Reviewed-on: http://git-master/r/62373 Reviewed-by: Min-wuk Lee <mlee@nvidia.com> Tested-by: Min-wuk Lee <mlee@nvidia.com> Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com> Tested-by: Gerrit_Virtual_Submit
2011-11-10arm: tegra: enterprise: Pass ext power req control properlyLaxman Dewangan
Passing the external power request control information for rails through ext_pwr_req. Reviewed-on: http://git-master/r/62654 (cherry picked from commit 9fc465709e002d7967757a433a5465f92371d466) Change-Id: Iea797e1dfbbe9418b081940418aa770671ca1bfa Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/63502 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-11-10arm: tegra: cardhu: Put LDO7/8 to OFF in sleep stateLaxman Dewangan
Putting the LDO7 and LDO8 to OFF in sleep state. bug 892613 Reviewed-on: http://git-master/r/60878 (cherry picked from commit e4dbb17af9c1cca65c12c1db3ca491b467d188c9) Change-Id: I952476b4ac60a907851bd125493bdd4dca0ab9b0 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/63500 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-11-10ARM: tegra: cardhu: emmc: Increase max_clk freqPradeep Goudagunta
Increasing maximum clock frequency supported by sdmmc4 to 104MHz. Bug 877336 Reviewed-on: http://git-master/r/55433 (cherry picked from commit 8a785b8517e9c97992d53026b604698ea177e637) Change-Id: Ie160c939832eb01e8605c5bc8f9533c0bdf1daea Reviewed-on: http://git-master/r/62417 Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com> Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2011-11-10video: tegra: dsi: Add support for DCS short write (1 parameter)Ming Wong
Add MIPI DCS short write (1 parameter) support. The cmds sent with this new function will be sent every frame by hardware Signed-off-by: Ming Wong <miwong@nvidia.com> Bug 884157 (cherry picked from commit 855cac72bf030213db6fa1e42ce4e5891b16681c) Change-Id: I5c4e8696195d01f4f9dfb8cf66b5b3744f78c41e Reviewed-on: http://git-master/r/62300 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com>
2011-11-10ARM: Tegra: Power: use new api to get cpu regulator max_currDiwakar Tundlam
used when the chip SKU is T33/T33S (cardhu case) or AP33 (enterprise case) to initialize edp with a higher cpu regulator max_curr value. bug 888679 Reviewed-on: http://git-master/r/59452 (cherry picked from commit cd817edc2f2f3071d2cf4dc2b1166f5dcf77dbef) Change-Id: Icb50b33b1fc9b1248886e040f4b9b927feee4242 Reviewed-on: http://git-master/r/60780 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com>
2011-11-10ARM: Tegra: dvfs: T33 SKU EDP tableDiwakar Tundlam
Bug 841336 Reviewed-on: http://git-master/r/52460 (cherry picked from commit dd2864cd36ff707508fb5e5e8f5eb2ff944983da) Change-Id: I661a9d27cd84d28c7e6ab74a020653a93c388fe8 Reviewed-on: http://git-master/r/60779 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com>
2011-11-10arm: tegra: power: guardbanding only for accuracy of TDiodeDiwakar Tundlam
Bug 844025 Reviewed-on: http://git-master/r/51443 (cherry picked from commit 1abdcb266a1fa22fd766549d5eddcca92e1fb17e) Change-Id: I0bc47499ca1f944cc69d51eb78de39c25ef73e1a Reviewed-on: http://git-master/r/60777 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com>
2011-11-10arm: tegra: power: tsensor to therm frameworkJoshua Primero
Hooked up tsensor to thermal framework. Cleaned up some unnessary tsensor code as well. Bug 848755 Reviewed-on: http://git-master/r/62021 (cherry picked from commit 307f53a36bd1bdfaabddfdd80f9de5445d805786) Change-Id: Ic16f417461cdb71cbd135f57d1017bab8433dcdf Reviewed-on: http://git-master/r/63344 Reviewed-by: Joshua Primero <jprimero@nvidia.com> Tested-by: Joshua Primero <jprimero@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
2011-11-10arm: tegra: fuse: add tegra revision string for A03Diwakar Tundlam
Change-Id: I4928468454c4c2f3f5b0f3a8f08c7eb5241c40cd (cherry picked from commit 7c2b764fb591eaed843efcc4adf6b8b37f8eb942) Reviewed-on: http://git-master/r/62767 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
2011-11-10arm: tegra: fix compiler warningsDiwakar Tundlam
Reviewed-on: http://git-master/r/53296 (cherry picked from commit 12ed00a4b6024299617f7ff9cd2f0e718f5eb11e) Change-Id: Id536d9d33dd11eac706954ca1bce2d0c5ba14895 Reviewed-on: http://git-master/r/60778 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
2011-11-09arm: tegra: enterprise: HSIC phy ready and phy off callbacksSeshendra Gadagottu
Implemented HSIC phy ready and phy off callabacks for enterprise board. BUG 828389 Reviewed-on: http://git-master/r/52884 (cherry picked from commit fc919eab4be5012f9fd0fc7dbd4b7de7d5bff5db) Change-Id: Ia3539e5982f4c0df5b9fca04c118ba8a6132431a Reviewed-on: http://git-master/r/62975 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Michael Hsu <mhsu@nvidia.com> Reviewed-by: Steve Lin <stlin@nvidia.com>
2011-11-09arm: tegra: cardhu: HSIC phy ready and phy off callbacksSeshendra Gadagottu
Implemented HSIC phy ready and phy off callabacks for cardhu board. BUG 828389 Reviewed-on: http://git-master/r/52883 (cherry picked from commit 9d2e1e07c00d1f84dc24ccb861c5fb9ca751cb9c) Change-Id: I655c037402119244c7f78e2625fa893f4ad3c50f Reviewed-on: http://git-master/r/62974 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Michael Hsu <mhsu@nvidia.com> Reviewed-by: Steve Lin <stlin@nvidia.com>
2011-11-09arm: tegra: cardhu: pm299: Controls cpu power through PWRREQ2Laxman Dewangan
Controlling cpu power through external power request PWRREQ2. Reviewed-on: http://git-master/r/62651 (cherry picked from commit 3091e2ed93bb9bf5a962f5fc509dde16a89a34fb) Change-Id: I3276ab26abe451e091f290aedd9417ea04e53a5d Reviewed-on: http://git-master/r/62896 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
2011-11-09ARM: tegra: TrustedLogic drop 32055Rahul Prabhakar
The WARs checked into 12r7: disable LP0/LP1 and slave LP2, and force maxcpus to 1 aren't needed when used with the newer tf_include.h from this TL drop. bug 868906 bug 870224 bug 877339 Reviewed-on: http://git-master/r/54158 (cherry picked from commit 0c41dfa8eca33ca21c0ea49a2ed32802ddeb6a29) Change-Id: If4b1ab1f3e542bc4f0bdb7a2e6e83b8119f414c0 Reviewed-on: http://git-master/r/55583 Tested-by: Gerrit_Virtual_Submit Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
2011-11-08ARM: tegra: power: Update CPU rate after mode switchAlex Frid
Update Tegra3 CPU clock rate after G=>LP mode switch is completed to synchronize with cpufreq target rate. (cherry picked from commit 870d21e5e23eff476cdd841b4ce2605393d638ef) Signed-off-by: Alex Frid <afrid@nvidia.com> Change-Id: Id163cc9868c85c1efcf654adba67a2d56338b9d7 Reviewed-on: http://git-master/r/62754 Reviewed-by: Allen Martin <amartin@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com>
2011-11-08ARM: tegra: dvfs: Add Tegra3 AP33 dvfs tablesAlex Frid
Bug 841336 (cherry picked from commit b4cd14d5b9d1b2011a7752b6c52b3b64eb227cdb) Signed-off-by: Alex Frid <afrid@nvidia.com> Change-Id: I463a35c94ae7fe7fa53f02213f0daeb413823a6a Reviewed-on: http://git-master/r/62753 Reviewed-by: Allen Martin <amartin@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com>
2011-11-08ARM: tegra: dvfs: Optimize Tegra3 VDD_CPU control in LP modeAlex Frid
Optimized Tegra3 VDD_CPU control when VDD_CPU target is set to zero, which could happen only while CPU is in LP mode (and CPU regulator output is turned off by side-band signal, anyway): - Ignore VDD_CPU dependency on VDD_CORE while VDD_CPU target is zero - Allow VDD_CPU one step change to zero (i.e., to minimum voltage set by constraints) after entry to LP mode - Allow VDD_CPU one step change to the predicted G mode target before exit from LP mode (cherry picked from commit 5826f3e28867207b5dad1c50795de8275d1af872) Signed-off-by: Alex Frid <afrid@nvidia.com> Change-Id: I81e366836f7fec7af48b479ecc0b6b7787d73c42 Reviewed-on: http://git-master/r/62752 Reviewed-by: Allen Martin <amartin@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com>
2011-11-08ARM: tegra: cardhu: Update dvfs tables for elpida & samsungRay Poudrier
Added dynamic self-refresh field and updated arbitration settings. Bug 896654 Reviewed-on: http://git-master/r/61728 (cherry picked from commit 6b8d5582fb205c6cb277ce0ecbe328fcf724d664) Reviewed-on: http://git-master/r/62297 (cherry picked from commit 9c60a6c5f5bc07253454a057e9b3e0046c574b45) Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com> Change-Id: I8c7b16445fe2ec72c0423a3511397133e509247f Reviewed-on: http://git-master/r/62535 Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com> Tested-by: Raymond Poudrier <rapoudrier@nvidia.com> Reviewed-by: Allen Martin <amartin@nvidia.com>
2011-11-08ARM: tegra: cardhu: Expand EMC DFS table for Hynix DDR3Ray Poudrier
- Added dynamic self-refresh field, and updated arbitration settings Bug 896654 Reviewed-on: http://git-master/r/61725 (cherry picked from commit 2d5a9c1fbe5cdf4f4233ec3eca230d625d0439de) Reviewed-on: http://git-master/r/62296 (cherry picked from commit 31f9198bcc05c35cc4aa797e4f224aed62fdfc64) Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com> Change-Id: I1741c04520b13d7dcdf7d712c372a182b727400f Reviewed-on: http://git-master/r/62534 Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com> Tested-by: Raymond Poudrier <rapoudrier@nvidia.com> Reviewed-by: Allen Martin <amartin@nvidia.com>
2011-11-08ARM: tegra: clock: Add DSR field to Tegra3 EMC DFS tableAlex Frid
Added dynamic self-refresh (DSR) field to Tegra3 EMC DFS table. This field will be supported starting with table revision to 3.2, and it will allow to enable/disable DSR for each table entry independently. Bug 853990 (cherry picked from commit 6e225af7334d789ffac72542602913a0028d5eac) Change-Id: I42e719b2f13c69281f525c11122807c03a7c3bca Signed-off-by: Allen Martin <amartin@nvidia.com> Reviewed-on: http://git-master/r/62755
2011-11-08arm: enterprise: config: raise mmc minor limitSang-Hun Lee
- Raise the number of mmc minors per block device to 16 Bug 870221 Reviewed-on: http://git-master/r/59769 (cherry picked from commit 183f279210b797da859229ae83e81f25fdf2f86e) Change-Id: Ic911779f4d0a81f9615a1a54bdd147301f835337 Reviewed-on: http://git-master/r/62346 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-11-08arm: tegra: Fix sync point intr registration issue.Krishna Reddy
Perform sync point interrupt registration only when CONFIG_TEGRA_GRHOST is enabled. Reviewed-on: http://git-master/r/58854 Reviewed-by: Chris Dragan <kdragan@nvidia.com> Tested-by: Chris Dragan <kdragan@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Tested-by: Gerrit_Virtual_Submit (cherry picked from commit fa5fab33007eae5ef40d2dbb4701fa6840cc5191) Change-Id: I26df8fee6aaf7e6b2e09715d4b57bc32f9aaad73 Reviewed-on: http://git-master/r/62719 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-11-08ARM: tegra: gpio: Add range check for gpio enable/disableChaitanya Bandi
Added the range check into tegra_gpio_enable and tegra_gpio_disable Bug 897387 Reviewed-on: http://git-master/r/62104 (cherry picked from commit e2946c2cb77e3eacacb5169b3ce3f3f30caa87db) Change-Id: Ic9b745036959b64f1421b031d31f67b987dc2163 Reviewed-on: http://git-master/r/62641 Tested-by: Bandi Krishna Chaitanya <bandik@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2011-11-08arm: tegra: kbc: cardhu/enterprise: Set scan timesLaxman Dewangan
Setting the number of scans to 30 by keyboard controller after pressed key released. Also setting repeat delay time to 1 clock. bug 876712 Reviewed-on: http://git-master/r/61061 (cherry picked from commit 5592ddb0aa9fbec20a39ad6c1ad3efa3424cefe7) Change-Id: Icdc7238c4add89364834383c53fca26434b57392 Reviewed-on: http://git-master/r/62592 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-11-08input: tegra: kbc: Board param for scan countLaxman Dewangan
The scan timeout of the continuous mode can be calculated based on init delay, repeat delay, debounce count and number of active row. It also depends on how many scan need to be done before kbc change the mode from continuous to wakeup mode. Providing mechanism to select the scan count from platform data and calculating the scan timeout count based on above parameters. bug 876712 Reviewed-on: http://git-master/r/61060 (cherry picked from commit 830fbf574f7d545926a4ed3fd2433585688b884b) Change-Id: Ibced5559af2d2b0f87de626d86d16e6127b9b2fb Reviewed-on: http://git-master/r/62591 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
2011-11-08arm: tegra: enterprise: battery detection support for fuel-gaugesyed rafiuddin
Adding battery present support to fuel-gauge driver so as not to report battery charecterstics when battery is not present bug 873965 Reviewed-on: http://git-master/r/55122 (cherry picked from commit 6c88c37e3bedf4645ecf359e8cf9e84e0868fed0) Change-Id: I9366c859f7764cf675b9369a4722f80880732d44 Reviewed-on: http://git-master/r/61831 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-11-08arm: tegra: power: Device agnostic thermal driverJoshua Primero
Added a thermal driver which is agonistic to the device driver which will make it easier to port thermal devices to android tegra. Reviewed-on: http://git-master/r/55883 Change-Id: Ie51d6b2b5bb7f29a3e2308252a1fc4e7050b5dbf Reviewed-on: http://git-master/r/59471 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-11-07arm: tegra: enterprise: disable usb3Rakesh Bodla
Disabling usb3 as it is not used on enterprise. Bug 885298 Reviewed-on: http://git-master/r/57201 (cherry picked from commit a74f09883bd09355e1b4e8c322dff279f8505b5b) Change-Id: Ia403db9b039eeb646e0c8e452d2ef6549f83497f Reviewed-on: http://git-master/r/58625 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-11-07arm: tegra: cardhu: pm298: Fix SDMMC regulator registrationMin-wuk Lee
Use the device driver name instead of encoding the SDMMC controller in the regulator supply name. This change is came from commit 676dd57f8eb252ce61807c02e5153b4ee4e29418, and it was reviewd on http://git-master/r/#change,53783. Original Author: Jinyoung Park Reviewed-on: http://git-master/r/56368 (cherry picked from commit 03aa6082f7db7006de6e9c357fcf04e0d395fb16) Change-Id: I3b1c4a1f376f963bb829f4738dc5104a9d1292d2 Reviewed-on: http://git-master/r/62384 Reviewed-by: Min-wuk Lee <mlee@nvidia.com> Tested-by: Min-wuk Lee <mlee@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2011-11-07arm: tegra: cardhu: pm298: Remove SDMMC1_VDD control for PM269Min-wuk Lee
The SDMMC_VDD control is generated from the cpld programming for pm269 and so it is not require to have gpio control for this. This change is came from commit e92b10299b329f9df29ae23099b8f2f5f2eee1d7. Original Authour: Jinyoung Park Reviewed-on: http://git-master/r/56367 (cherry picked from commit b30687a50bb2bf520d71e02339d01481c2d418bd) Change-Id: I2ac174ab2303c669474d84e04f9ec2f18adde51d Reviewed-on: http://git-master/r/62383 Reviewed-by: Min-wuk Lee <mlee@nvidia.com> Tested-by: Min-wuk Lee <mlee@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2011-11-07arm: tegra: cardhu: pm298: Add regulator supply for NCT1008Min-wuk Lee
Adding regulator supply "vdd" for NCT1008 into PM298 what MAX77663 PMIC. Original Author: Jinyoung Park Reviewed-on: http://git-master/r/56366 (cherry picked from commit 3db418ee3342f70cb8bfbb7edc0e897d69a826c9) Change-Id: Ic09ef689a9ea56bdb29c2ff11676c518507b87c9 Reviewed-on: http://git-master/r/62382 Reviewed-by: Min-wuk Lee <mlee@nvidia.com> Tested-by: Min-wuk Lee <mlee@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2011-11-07arm: tegra: cardhu: pm298: Correct min_uV for SD1 power railMin-wuk Lee
Previously it is configured SD1 min_uV to 1.05V to avoid voltage under-shooting issue on SD1 power rail. But it doesn't need after safe voltage scaling step patch for max77663 regulator driver. Original Author: Jinyoung Park Reviewed-on: http://git-master/r/56962 (cherry picked from commit 3ea4ea8a5594cb8b5781bfd06816993b0a3e90cf) Change-Id: Iac7a955603fb55858b1bb232c18ff5acce3c5735 Reviewed-on: http://git-master/r/62377 Reviewed-by: Min-wuk Lee <mlee@nvidia.com> Tested-by: Min-wuk Lee <mlee@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2011-11-07arm: tegra: cardhu: pm298: Support for PM305, PM311 and E1257Min-wuk Lee
PM298 what MAX77663 PMIC supports for PM305, PM311 and E1257 based systems. Original Author: Jinyoung Park Reviewed-on: http://git-master/r/56365 (cherry picked from commit 7ed6615501bf406e0fca79e559e60e896b07bea2) Change-Id: I3766e1a6c2c14ff829062994b7919d90dfdb94db Reviewed-on: http://git-master/r/62375 Reviewed-by: Min-wuk Lee <mlee@nvidia.com> Tested-by: Min-wuk Lee <mlee@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2011-11-07ARM: tegra: power: Fix SDMMC regulator registrationPavan Kunapuli
Use the device driver name instead of encoding the SDMMC controller in the regulator supply name. Bug 876282 Reviewed-on: http://git-master/r/53783 (cherry picked from commit 676dd57f8eb252ce61807c02e5153b4ee4e29418) Change-Id: If9d8cd59e468969e590abe29d54702f586b9a80f Reviewed-on: http://git-master/r/62338 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-25 00:40:02 +0000