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2012-05-14arm: tegra: p1852: Add Tegra camera driverSonghee Baek
Add Tegra camera driver to support video capture through H/W interfaces VIP, CSI. Bug 978086 Change-Id: I0dc51e47928388ed2073a99f8ca80b5a5a77d166 Signed-off-by: Songhee Baek <sbaek@nvidia.com> Reviewed-on: http://git-master/r/101590 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-14ARM: tegra: clock: Export clock minimumAntti P Miettinen
Add clock minimum to debugfs. Bug 917644 Change-Id: Ie088809829af2bdc81a969a034bf00847459f0ce Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com> Reviewed-on: http://git-master/r/101555 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-14arm: tegra: sdhci: Limit eMMC,SDIO,SD DDR clockPavan Kunapuli
Limit eMMC, SD and SDIO DDR mode clock to 41MHz. Bug 967719 Change-Id: Iaccc5b771b81b15226f87684b547ad1fb7dd38d3 Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-on: http://git-master/r/101173 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-05-14arm: tegra: clock: Add tegra3 sdmmc4 EMC shared userPavan Kunapuli
Adding tegra3 sdmmc4 EMC shared user in the tegra3 clock table. Bug 967719 Change-Id: I934dcaebf664f8b1db9ea07eef07eb6f266822aa Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-on: http://git-master/r/100582 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-14arm: tegra: sdhci: Define ddr50 clock limitPavan Kunapuli
Added a new variable in sdhci platform data which will limit the ddr50 mode clock. Bug 967719 Change-Id: I3f55b55651362447845c2e1d5000939e3e028df6 Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-on: http://git-master/r/100569 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-05-14drivers: video: tegra: Implement HOST1X syncpt initTerje Bergstrom
Move initialization for HOST1X sync point irq to nvhost driver. Bug 871237 Change-Id: I0d31e03b43999c609194665cdcbd2f0e498d848f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/100250 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
2012-05-14ARM: tegra: Correction of safe optionAshwini Ghuge
Corrected safe option for LPW0 and LPW2 Bug 920686 Change-Id: I14e1a22de3338ba569d3b381508e123d12aad059 Reviewed-on: http://git-master/r/101973 Tested-by: Ashwini Ghuge <aghuge@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-05-14arm: tegra: cardhu: add ov5640 supportCharlie Huang
bug 921322 Change-Id: If7f05c632816abac54852293ebd3834b5b3984d8 Signed-off-by: Charlie Huang <chahuang@nvidia.com> Reviewed-on: http://git-master/r/99508 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-05-14ARM: config: tegra3: enable CONFIG_REGULATOR_USERSPACE_CONSUMERLaxman Dewangan
By enabling the user space regulator consumer, it is possible to control the rail from userspace through sysfs. bug 966960 Change-Id: I0f4a7a0afdc998d58e6448e4f621ee4e430a7ef6 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/100320 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-05-11ARM: tegra: Pinmux conflict correctionAshwini Ghuge
Corrected Mux option for LPW2 Bug 920686 Change-Id: I1e93a28c070ca7689c305d84ed8664c3f170bfcb Signed-off-by: Ashwini Ghuge <aghuge@nvidia.com> Reviewed-on: http://git-master/r/101959 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
2012-05-11ARM: tegra: Enable TXFILLTUNING for all USB interfacesVenu Byravarasu
As per recommendation from ASIC team, Setting TXFILLTUNNING to 0x10 for all USB interfaces. bug 974507 Change-Id: Id2ee26927e56bf500a0fed2a414b74ffab157403 Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> Reviewed-on: http://git-master/r/99629 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-11arm: enterprise: power: Fix sdmmc3 regulator entryPavan Kunapuli
Register vdio_sdmmc3 supply with a valid device id instead of NULL. Bug 982788 Change-Id: Ie19d8a48b381190e8f966928a785af0f51794cb1 Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-on: http://git-master/r/101971 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-05-11arm: tegra: configs: Add GPIO regulator supportPavan Kunapuli
Enable CONFIG_GPIO_REGULATOR for Tegra3 platforms. Bug 982788 Change-Id: I17587447013fdde6dc58b4fbf23f0ca37faa3dc5 Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-on: http://git-master/r/101968 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-05-11arm: tegra: enterprise: New EMC table for A04 enterpriseKarthik Ramakrishnan
New EMC memory table for A04 Enterprise board Bug 969716 Signed-off-by: Karthik Ramakrishnan <karthikr@nvidia.com> Change-Id: I6936859ddf8d01b71025bfd21b690394dc3207bc Reviewed-on: http://git-master/r/101626 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Thomas Cherry <tcherry@nvidia.com> Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
2012-05-10ARM: tegra: kai: change NCT72 conversion rateDaniel Fu
Bug 961829 NCT72 thermal sensor consumes ~3mW at 16Hz conversion rate. At 32Hz, the power consumption ~1.5mW. Change conversion rate to 32Hz to reduce power consumption. LP0 power consumption will not reduce, because the sensor will enter standby mode. Signed-off-by: Daniel Fu <danifu@nvidia.com> Change-Id: If584c57b4d6e0b3068d9a1210a977ef5cd347984 Reviewed-on: http://git-master/r/101217 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-05-10Arm: tegra: p1852: Changed sclk to run at max.Mohit Kataria
Sclk frequecy changes depending on the clocks derived from sclk. Changed it to run at max POR frequecy. Bug 971061 Change-Id: I357e1acd8d049bf233ff79b942c911db123865f6 Signed-off-by: Mohit Kataria <mkataria@nvidia.com> Reviewed-on: http://git-master/r/100859 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2012-05-09arm: tegra: Correct tap delay for all T30 sdhci controllersnaveenk
Tap delay value of 0x0F is recommended by HW team Bug 911075 Change-Id: I9b73e7203c0dcb1971073b1d7251d11d71eddff3 Reviewed-on: http://git-master/r/98796 (cherry picked from commit 637b073d6ff7d7d71c2e0e632b222ecc6850be23) Reviewed-on: http://git-master/r/98763 Tested-by: Naveen Kumar Arepalli <naveenk@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
2012-05-09Revert "ARM: tegra: clock: Don't fail clk_enable when max_rate has been lowered"Alex Frid
This reverts commit 8d351aa5478de533114e614f2607bc85ed23df91. The above commit introduced recursive call of clk enable/set rate APIs that may hang the system. Change-Id: I04eff9e1c3ddee82f6d2e17690122cc41fad203f Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/100710 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-09ARM: tegra: power: Apply down delay to balancing CPUsAlex Frid
On Tegra3 secondary G-CPU may be turned off by auto-hotplug governor in two cases: when overall CPU load is low enough to justify transition to LP CPU, or when CPU cores usage by the scheduler is unbalanced (skewed). In the former case down delay (currently 2sec) was inserted before the core is turned Off. In the latter case the up delay (100ms) was used, i.e., the same delay applied to balancing cores regardless of the On/Off direction. This commit would apply down delay when turning core Off in both cases above, and keep using up delay only for turning core On. Change-Id: Id545f8d48cbf380e24824a5adfe045ff68c1f39c Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/99708 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-05-08Arm: tegra: p1852: Avp clock frequency to 334Mohit Kataria
changed the max avp clock from 378MHz to 334MHz as per new POR changes Bug 883565 Change-Id: I4e9dda0288f3f85c8b1705971bb8f389127cff28 Reviewed-on: http://git-master/r/97279 Signed-off-by: Mohit Kataria <mkataria@nvidia.com> Reviewed-on: http://git-master/r/100870 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2012-05-08input: touch: enterprise: Increase i2c to 400Khz.David Jung
Modified board file to increase the speed of I2C connection for Atmel touch driver from 100KHz to 400KHz Bug 962710 Change-Id: Ic692a4b610c5b952c1bdcfbb26e19714b1952a5f Signed-off-by: David Jung <djung@nvidia.com> Reviewed-on: http://git-master/r/98585 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Ali Ekici <aekici@nvidia.com> Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com> GVS: Gerrit_Virtual_Submit
2012-05-08video: tegra: dc: Set default videomodeShashank Sharma
Set default videomode during the dc probe. This patch enables HDMI during the probe only and fixes following issues: 1. Until Xinit there was no display on HDMI. 2. Framebuffer console on HDMI needs it to be enabled well before Xinit. To avoide un-necessary powering on HDMI,Check HPD and enable HDMI only if it's present. Bug: 930136 Bug: 977705 Change-Id: Ifb71328e5df0ccbb5751669db71fd24719fe3738 Signed-off-by: Shashank Sharma <shashanks@nvidia.com> Reviewed-on: http://git-master/r/100656 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-05-07arm: tegra: Cardhu board file, 400K I2C touch drvrAli Ekici
Modified board file to increase the speed of I2C connection for Atmel touch driver from 100KHz to 400KHz Bug 962710 Bug 950422 Change-Id: Ib0f08af35d84cfc1f33cc3771d2aa422f79d98d0 Signed-off-by: Ali Ekici <aekici@nvidia.com> Reviewed-on: http://git-master/r/97744 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Robert Collins <rcollins@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: David Jung <djung@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-05-07ARM: tegra: enterprise: register parent regulator before fuse regulatorLaxman Dewangan
bug 978829 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/99460 (cherry picked from commit b5531673e3da75f2406685ce377f39d76f494162) Change-Id: I5280dedb460df9852cc39d1c17132319e202c7b2 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/100524 Reviewed-by: Automatic_Commit_Validation_User
2012-05-07ARM: tegra: cardhu: Wakup through GPIO-PV0 for E1291-A04Laxman Dewangan
To have the proper LP0 exit power sequence, it is require to wakeup system through tegra gpio rather than PMU-INT. bug 957972 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/100107 Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com> Cherry-picked commit ffe8e102d91c5eafc0b71b044b97fe9e8cef7463 Change-Id: I0518e46b43ec36ba6e076a946da2d395cd31777e Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/100521 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-05-07ARM: tegra: clock: Add locked version of round rateAlex Frid
Add locked version of round rate API to be used by tegra arch specific layer. Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit 457627966b91f2141439812869adc4acf9242471) Change-Id: Id68d0bb952d1e7d9e650341872d1b06b0b2d3cea Reviewed-on: http://git-master/r/100474 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-05-07arm: tegra: pl310: Enable dynamic clock gating and standy.Krishna Reddy
Bug 947861 Change-Id: Ib4ce7bfa3624562a766678a2ef20ebdcd3055d89 Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/100462 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bo Yan <byan@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-05-07arm: tegra: scu: Enable IC and SCU standbyKrishna Reddy
Bug 947861 Change-Id: I1ac97b5de5e7e79a418b3c38c70df4976616cdf3 Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/100457 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-05-06arm: tegra: kai: set the pull up source GPIO_PCC7Hunk Lin
TEGRA_GPIO_PCC7(PEX_L2_CLKREQ) is used as the pull up source to pull up other pins in schematic. So set it to high default. bug 949026 Change-Id: I5a4d806ec4b54969514547472cd08018d285ced5 Signed-off-by: Hunk Lin <hulin@nvidia.com> Reviewed-on: http://git-master/r/99778 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2012-05-06ARM: tegra2: clock: Enable PREINIT_CLOCKSJong Kim
Enable CONFIG_PREINIT_CLOCKS. bug 967065 Change-Id: Ib6675f9bff6729ffe7dfcd8b753c42b5d32240e4 Signed-off-by: Jong Kim <jongk@nvidia.com> Reviewed-on: http://git-master/r/99517 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2012-05-06arm: configs: tegra: enable tegra udc driverRakesh Bodla
Enable tegra udc driver. Bug 887361 Change-Id: Iaac2486d2a05454fa351920d5c65d17b9c2a881b Signed-off-by: Rakesh Bodla <rbodla@nvidia.com> Reviewed-on: http://git-master/r/99449 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
2012-05-06arm: tegra: update the udc driver nameRakesh Bodla
Update the clocks structure to use new udc driver name. Also, update the device structure. Bug 887361 Change-Id: I0fd846ab177e8651f285bcb9796361d30967b830 Signed-off-by: Rakesh Bodla <rbodla@nvidia.com> Reviewed-on: http://git-master/r/99448 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2012-05-06ARM: tegra: Export tegra_powergate_is_powered()Antti P Miettinen
Export tegra_powergate_is_powered() for use by modules. Change-Id: I8cfbb8aeb95dca00cbf6ef0c8c2bd189afeb62b6 Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com> Reviewed-on: http://git-master/r/97724 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2012-05-06arm: tegra: kai: Switch to external temperature sensorKerwin Wan
Disable internal temperature sensor and enable external temperature sensor. This is a modified version of change 74db6e22d316a95630d3059644fbc55e2620cb9b Bug 954134 Change-Id: Id64bb93a09e1701165ad1f82e08bb92e61425873 Signed-off-by: Daniel Solomon <daniels@nvidia.com> Reviewed-on: http://git-master/r/96285 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2012-05-06ARM: tegra: cardhu: pm299: system wake through tegra gpioLaxman Dewangan
Waking up system through the tegra gpio inplace of ricoh onkey when using the ricoh based pmu. bug 978922 Change-Id: If9c5baffa42aca5fcc7d6238c5cf122a136e7760 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/100351 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
2012-05-04ARM: tegra: enterprise: Limit holdoff set for 533MHzRay Poudrier
Bug 935079 Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com> Reviewed-on: http://git-master/r/86009 (cherry picked from commit 83eb3734f76e598d570dd9624e7e06f8b3e05afe) Change-Id: I5911670e7c1e8dd5fc4e89d4be21b9dcbc4c9085 Reviewed-on: http://git-master/r/98535 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com> Tested-by: Raymond Poudrier <rapoudrier@nvidia.com>
2012-05-04ARM: tegra: Enable ARM errata 716044 for Tegra2.Krishna Reddy
Change-Id: Id71da6f6371f337f913d981f6d121c3fb2561a41 Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/95915 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2012-05-04ARM: errata: 716044: an uncacheable load multiple can cause a deadlock.Krishna Reddy
Under some rare circumstances, an uncacheable load multiple instruction (LDRD, LDM, VLDM, VLD1, VLD2, VLD3, VLD4) can cause a processor deadlock. Change-Id: Ibd79aa8182dce37d0be9892f2310735e1123618a Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/95914 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2012-05-04arm: tegra: Implement safe option for T30 pinmuxAshwini Ghuge
Bug 950086 Change-Id: I2eb129566bfea83b9a73d29f0c6443bdab087b65 Signed-off-by: Ashwini Ghuge <aghuge@nvidia.com> Reviewed-on: http://git-master/r/95518 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Andy Park <andyp@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-05-03ARM: tegra2: clock: Put Tegra2 clocks to known statesJong Kim
Add TEGRA_PREINIT_CLOCKS option to put host1x, disp1, and video clocks into known state, so that L4T Ventana/Harmony works on u-boot. bug 967065 Change-Id: If7637b13e0daf1823fa0fe694a87870f4601e4df Signed-off-by: Jong Kim <jongk@nvidia.com> Reviewed-on: http://git-master/r/95734 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2012-05-03ARM: tegra: enterprise: register supply regulator before child regulatorLaxman Dewangan
LDO3 has the input from the VIO output and hence VIO should be register before LDO3 for regulator registration. bug 976254 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/99446 Change-Id: I6771af3e7eb93886e974695ab3550cdf8ebc52c4 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/100262 Reviewed-by: Automatic_Commit_Validation_User
2012-05-03ARM: tegra: whistler: Set I2c pin drive strength to maxLaxman Dewangan
Setting i2c drive strenth to maximum and pulling all pins to high. bug 951052 bug 958415 bug 927583 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/91805 Change-Id: Ia2bf4ccba6d4c47411e59fb9567dc4e3c2db76ae Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/100261 Reviewed-by: Automatic_Commit_Validation_User
2012-05-03ARM: tegra: ventana: Set drive strength to max for all i2c pinsLaxman Dewangan
Setting drive strength to maiximum for all i2c pins. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/91952 Change-Id: I8882dd238af34e06c924f2e160d0897111e8103d Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/100260 Reviewed-by: Automatic_Commit_Validation_User
2012-05-03ARM: tegra: whistler: Add slave address for i2c driverLaxman Dewangan
Configuring all i2c controller to have slave addresss to 0xFC (unused slave address) to avoid responding the slave with general call address. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/91951 Change-Id: Id1a45f46cfc5ffa3a48b01c0bae71c4ee9ab699b Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/100259 Reviewed-by: Automatic_Commit_Validation_User
2012-05-03Revert "video: tegra: dc: Set default videomode"Hunk Lin
This reverts commit 9349cedf17f9b3c10760c8d48f831473f87a3a15. It is reviewed on http://git-master/r/99635 It will cause HDMI power ON and emc clock bump up to 667Mhz after resume from LP0. bug 930136 Change-Id: I130494fdb381b3d322ac0e3fc8be2e44f2c2d7a7 Signed-off-by: Hunk Lin <hulin@nvidia.com> Reviewed-on: http://git-master/r/100202 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jon Mayo <jmayo@nvidia.com>
2012-05-03ARM: tegra: power: Enforce CPU rate range in min cpu notifierAlex Frid
On Tegra3 make sure cpu rate is within G-mode range before LP to G mode switch triggered by minimum CPUs notifier. Bug 964208 Change-Id: Ic4ee6bc7eca5ad0902da4907e4702f296a155280 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/99834 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-05-03arm: tegra: enterprise: Set gpio LCD_D8 to tristateKarthik Ramakrishnan
LCD_D8 used for BAT_REMOVAL staus from PMU to be programmed as input/tristate to in line with hardware schematics. It is connected VIO_IN Bug 955519 (Cherry picked from I692d8d805c54da3996c33b9837b197a6995689c8) Change-Id: I68e6566249675cd5fce8aa954983478e4fc29a4c Reviewed-On: http://git-master/r/#change,91589 Signed-off-by: Karthik Ramakrishnan <karthikr@nvidia.com> Reviewed-on: http://git-master/r/99742 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-05-03ARM: tegra: clock: Add DSI implicit dependency on PLLPAlex Frid
Added dsi fixed clock entry derived from PLLP_OUT3. This would allow DC driver to properly ref-count implicit dependency of DSI operations on PLLP_OUT3 clock. Bug 933653 Change-Id: I71e6ada13f9d231c5a4924f345cdbf7cf05cd59e Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/98103 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-05-02arm: tegra: Update pinmux setting for nct alertAshwini Ghuge
Set KB_ROW11 pin to default PULL_UP to fix the excessive interrupts from nct alert. Bug 973536 Change-Id: Idab3769f3fe1945f5e0f487f7bd23a7c0b58d5d1 Signed-off-by: Ashwini Ghuge <aghuge@nvidia.com> Reviewed-on: http://git-master/r/99339 Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Tested-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Hunk Lin <hulin@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> GVS: Gerrit_Virtual_Submit
2012-05-02Revert "arm: tegra3: change min_rate for clocks"Amit Kamath
This reverts commit 5dc206986103aaa443fa6b0ef6fef20bcb35d299 because it causes noisy audio playback on Tegra3 platforms with secure-os. Bug 939415 Change-Id: Ib19962dd57a2560945d1c0ed49b3eade2c751446 Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-on: http://git-master/r/98986 Reviewed-by: Automatic_Commit_Validation_User
generated by cgit v1.2.3 (git 2.0.4) at 2024-04-27 23:23:14 +0000