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add the BCH clock setting, and keep them work in the same
frequncy.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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Change the DDR freq to 133MHz from 266Mhz (or 200MHz) when the AHB
is dropped to 66.5MHz. The DDR freq change will be initiated only
when the EPDC clock is not active. So there will be brief periods of time
when DDR is at 266Mhz even when AHB is at 66.5Mhz and DDR will be at 133Mhz
even when AHB is at 133Mhz.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Register SPI device first so that it will be the last device
to be suspended and first device to be resumed.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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By default, dynamic ZQ calibration runs by interval of 10 seconds.
This interval can be changed via Sys, for example 5 seconds,
echo 5 > /sys/devices/platform/mxc_zq_calib/interval
Signed-off-by: Robby Cai <R63905@freescale.com>
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need to make sure last ZQ calib run completed and no more ZQ calib to be run
during suspend, and resume ZQ calib until the system resumes.
Signed-off-by: Robby Cai <R63905@freescale.com>
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Added pgprot_writethru(), to set the buffer's cache property as
writethrough.
Signed-off-by: Robby Cai <R63905@freescale.com>
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For boards that use the SMSC 911x ethernet driver, the MAC ID for
the ethernet controller was randomly being generated. It should get
the MAC ID from the IIM fuses that are blown to show the correct MAC ID.
Signed-off-by: Dinh Nguyen <Dinh.Nguyen@freescale.com>
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Setting DSE to high and ODE bits in I2C3_SDA IOMUX pad causes WVGA to fail.
Fix is to use the default values for pad control.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Fix keypad can't wake up system
Signed-off-by: Frank Li <Frank.Li@freescale.com>
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Changed DLL delay from 0x14 to 0x0b
Swapped pu and (pu+1), pd and (pd+1) assignment in CFG1 and CFG2.
Signed-off-by: Robby Cai <R63905@freescale.com>
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Also fix the suspend/resume issue when CPU running @261818000Hz
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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LPDDR2 ZQ calibration is different from mDDR/DDR2 in this version.
The patch added a workaround to get appropriate pu/pd value for h/w.
Signed-off-by: Robby Cai <R63905@freescale.com>
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1. Changed VDDGP voltage to 1.0V as CPU freq is 160MHz.
2. Changed suspend values of VDDGP and VCC back to 0.95V
as HW issue has been resolved.
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
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Register the PWRON3 event when probe the power key device.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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Fix MX53 boot issue caused by the changes made to bus_freq driver.
Ensure that all MX5x platforms can enter/exit various low power modes.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Enable NO_HZ and PREEMPT as default config for mx28
Signed-off-by: Frank Li <Frank.Li@freescale.com>
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mdelay(10) actually delay 50ms before fix timer issue.
After fix timer issue. It should set to 50ms
Signed-off-by: Frank Li <Frank.Li@freescale.com>
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It should be match = current - delta.
Original code is match = last_match -delta.
Signed-off-by: Frank Li <Frank.Li@freescale.com>
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Add the capability to change the bus clocks at half the max frequency based on
which modules are active. AHB_CLK, AXI_A and AXI_B clock are at half the max.
DDR is left at 266MHz(LPDDR2)/200MHz (mDDR).
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Some GPC bits were getting set twice, fixed the issue. Protected the section where CPU
frequency is changed. For MX50, increase the cpu frequency along with increasing
the bus frequency.
Fixed the test conditions under which bus frequency should be set to low, medium or high
setpoint.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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In LPAPM mode, DDR is sourced from 24MHz OSC. Since only ARM clock is
sourced from PLL1, relock it to 160MHz to save some power.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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The dynamic ZQ calibration procedure need some revision and further debug.
Currently turn off this option for safety.
Signed-off-by: Robby Cai <R63905@freescale.com>
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Change vpu clock dependency for iram to emi_intr_clk[0]
since vpu should use emi_intr_clk[0], not emi_intr_clk[1].
Signed-off-by: Sammy He <r62914@freescale.com>
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SATA AHCI temperature monitor
HOWTO-USE:
Use the following cmd after boot up the target board and log in the system
The unit of the temperature is celsius.
Signed-off-by: Richard Zhu <r65037@freescale.com>
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The #defines for EPDC data lines were all off by 1. This
is now fixed.
Signed-off-by: Danny Nold <dannynold@freescale.com>
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The usb wakeup thread should be prior to usb system resume
during usb wakeup process. It adds wait_event_interruptible
at usb resume process, and the usb wakeup irq will set event,
and the usb wakeup thread will clear event.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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The usb wakeup thread should be prior to usb system resume
during usb wakeup process. It adds wait_event_interruptible
at usb resume process, and the usb wakeup irq will set event,
and the usb wakeup thread will clear event.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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Fix FEC GPIO/IOMUX settings in suspend to reduce board level power.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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VUSB2 cannot be shutdown in suspend, else USB remote wakeup fails.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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add a macro to fill the DMA command word one for IMX23,IMX28 and
IMX50.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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This is required by SD2 card detection function.
The root cause is that the power for SD2 card detection pull up
is the same as the SD2 I/O power, they are all supplied by VSD
regulator. If we disable VSD dynamically, the card will never be
able to be detected again.
Signed-off-by: Aisheng.Dong <b29396@freescale.com>
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Enable SRPG for TO1.1 chips.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Set the new video modes values
Signed-off-by: Ran Ferderber r53561@freescale.com
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Since the device suspend timing driver is
default set to off, so add it to default config of mx5, mx3.
If you want to debug your driver's suspend / resume
timing, please enable it by write time in microsecond.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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MC13892 LED workaround can only be applied when a battery is connected.
But we can not detect if a battery is connected since the ADIN5
pin has been tied to look like a battery is attached on MX5x
boards. So disable battery driver firstly.
Signed-off-by: Lily Zhang <r58066@freescale.com>
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This patch add code in msl for adding sense and fuse.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Add low power mode and wakeup support for mx28 otg port,
and the host1 and otg port are fully verified for low power mode and wakeup
function.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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FB_SYNC_EXT was used to represent ext clk, but actually, it represent ext sync.
Some applications do not recognize it, during fb_set_var ioctl may miss it,
which will cause fb display fail, for example X window startup.
Remove FB_SYNC_EXT flag, and choose ext clk support by ipu driver.
Signed-off-by: Jason Chen <b02280@freescale.com>
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MX53 TO2 and MX50 uses newer Z160 GPU core
Signed-off-by: Jie Zhou <b30303@freescale.com>
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ZQ calibration is now only applied in mx50 to1.1 board.
Thus zq should be run only on mx50 to1.1 board.
Signed-off-by: Terry Lv <r65388@freescale.com>
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The ioremap for dma apbh registers mapping is not correct.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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add onboard VBUS 5v regulator for USB ops in host mode
Signed-off-by: Zhou Jingyu <Jingyu.Zhou@freescale.com>
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Implemented the following:
1) Code to check mDDR v LPDDR2 memory type
2) For mDDR, changed DATABAHN register values for 24 MHz DDR clock
3) For mDDR, changed DATABAHN register values when clock is changed
back to 200 MHz in Async mode.
Note that this code is untested on TO 1.1.
Signed-off-by: Anish Trivedi <anish@freescale.com>
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Dump the DMA registers for the function mxs_dma_get_info().
Signed-off-by: Huang Shijie <b32955@freescale.com>
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change uart default parent to pll2 and clk rate to 66.5MHz
Signed-off-by: Jason Chen <b02280@freescale.com>
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It's found that MX53 ARD reset sometimes if setting VDDGP/VCC
to 0.95V in suspend mode. After many experiments, it's found
the system can resume well if setting VDDGP as 1.05v and VCC
as 1.025V accordingly, the system can resume.
HW team thought that DDR power supply U2 "enable" may turn off
U2 when VCC is 0.95V. So DDR may lost power. The suggested rework
is to add a NC7SP125 chip.
Since MX53 ARD boards didn't conduct such kind of reworks, this
patch increase suspend voltages to workaround for it before a
better solution can be found.
Signed-off-by: Lily Zhang <r58066@freescale.com>
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Change Vcc to 1.05V when the system is in LPAPM mode (LP domain and
DDR are at 24MHz)
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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and do the following for debugging purpose,
1. changed the running interval from 5 minute to 10 seconds
2. printed out the pu/pd value when it runs.
Signed-off-by: Robby Cai <R63905@freescale.com>
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Add ZQ calibration support
Signed-off-by: Terry Lv <r65388@freescale.com>
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MX53 TO2.0 fix the errata ENGcm11185 (L2 data corruption after
SRPG event). So this patch enables ARM SRPG for MX53 TO2.0
Signed-off-by: Lily Zhang <r58066@freescale.com>`
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