summaryrefslogtreecommitdiff
path: root/arch
AgeCommit message (Collapse)Author
2012-02-22ENGR00174734-1 usb: need to discharge both dp and dmPeter Chen
Change to discharge both dp and dm Signed-off-by: Peter Chen <peter.chen@freescale.com>
2012-02-17ENGR00174652 i.mx6: explicitly set the LPM mode to run mode during early bootupJason Liu
the reset value of LPM[1:0] in CCM_CLPCR register is b'01, which means system will enter into wait mode on next assertion of dsm_request signal. In order to avoid the system unexpectly enter the wait mode during bootup we need set the LPM mode to run mode explicity during early boot up phase, Anytime, we want system to enter the wait mode, the sw procedure is: mxc_cpu_lp_set(LP_MODE) -> set CCM_CLPCR register -> system enter wait mode This patch also fix linux kernel reboot stress test on i.mx6dl, without this patch linux kernel reboot test will fail random with error like this: [ 12.091220] Bad mode in interrupt handler detected [ 12.096056] Bad mode in interrupt handler detected [ 12.100851] Internal error: Oops - bad mode: 0 [#1] PREEMPT SMP Signed-off-by: Jason Liu <r64343@freescale.com>
2012-02-17ENGR00174630 [MX6]Disable GPT serial clockAnson Huang
Currently we use 24MHz clock as GPT's clock source, serial clock can be disabled, it sourced from high freq clock, gating it can save ~8mA @VDDSOC. Signed-off-by: Anson Huang <b20788@freescale.com>
2012-02-16ENGR00174540: i.mx6: anatop_regulator: LDO voltage print not correctlyJason Liu
The LDO voltage constraint not printed correctly: print_constraints: vddpu: 725 <--> 1300 mV at 700 mV fast normal print_constraints: vddsoc: 725 <--> 1300 mV at 700 mV fast normal print_constraints: vdd2p5: 2000 <--> 2775 mV at 2000 mV fast normal print_constraints: vdd1p1: 800 <--> 1400 mV at 700 mV fast normal print_constraints: vdd3p0: 2800 <--> 3150 mV at 2625 mV fast normal There due to one typo: << in the code, thus will make the LDO constraint print not correctly, the patch will make the print correctly as the followings: print_constraints: vddpu: 725 <--> 1300 mV at 1100 mV fast normal print_constraints: vddsoc: 725 <--> 1300 mV at 1200 mV fast normal print_constraints: vdd2p5: 2000 <--> 2775 mV at 2400 mV fast normal print_constraints: vdd1p1: 800 <--> 1400 mV at 1100 mV fast normal print_constraints: vdd3p0: 2800 <--> 3150 mV at 3000 mV fast normal Signed-off-by: Jason Liu <r64343@freescale.com> (cherry picked from commit 5c2d296401e2ded0cd36f9e651871c6454049de1)
2012-02-16ENGR00174532 [MX6Q]Change 2D clock to 480MLarry Li
Change GPU2D core clock to 480M and use PLL3 as parent Signed-off-by: Larry Li <b20787@freescale.com>
2012-02-15ENGR00174569: MX6 - Disable WAIT mode by defaultRanjani Vaidyanathan
None of the workarounds implemented in SW provide a stable solution for the WAIT mode issue. For 4.1 release, WAIT mode is disabled by default. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-02-15ENGR00172274-02 - [MX6]: rework IEEE-1588 in MX6Q Sabre-lite/sd board.Fugang Duan
- Config GPIO_16 pad to ENET_ANATOP_ETHERNET_REF_OUT. - IEEE-1588 ts_clk and i2c3 are mutually exclusive, because all of them use GPIO_16, so it only for one function work at a moment. - Test result: TO1.1 IEEE 1588 is convergent in Sabrelite board. Signed-off-by: Fugang Duan <B38611@freescale.com>
2012-02-14ENGR00174381 imx6q-sabreauto: spdif remove tx clock settingsAdrian Alonso
* Sabreauto platform only supports spdif in (Rx) Remove unused Tx clock settings Signed-off-by: Adrian Alonso <aalonso@freescale.com>
2012-02-13ENGR00174315 MX6Q max7310 set the default value of PCIE PWR ctrl2 to lowRichard Zhu
System would be halt, when the default value CTRL_2 is set to high, change the default value to low. root cause: System 3V3 would be dragged down to 1.5V for about 4ms. Signed-off-by: Richard Zhu <r65037@freescale.com>
2012-02-13ENGR00174316 MX6Q ARM2: Fix ov5640_mipi IOMUX incorrect configureEven Xu
One type error on ov5640_mipi IOMUX configure, fix it. Signed-off-by: Even Xu <b21019@freescale.com>
2012-02-13ENGR00174302 [MX6]Clean build warningAnson Huang
arch/arm/mach-mx6/clock.c:1749: warning: unused variable 'reg'; Signed-off-by: Anson Huang <b20788@freescale.com>
2012-02-10ENGR00174232 [mx6q perfmon]PDM No. TKT055916: remove workaround for TO1.1Tony Lin
remove the workaround For TO1.0: bit16 of GPR11 must be set to enable perfmon For TO1.1 and later: bit0 of GPR11 is enable bit for perfmon. set 1/0 to enable/disable perfmon add workaround for mx6dl Signed-off-by: Tony Lin <tony.lin@freescale.com>
2012-02-10ENGR00174224 [MX6Q]: Add new AR6003 driver to 3.0.15 into default configRyan QIAN
- Add cfg80211, Atheros Wifi driver into default kernel config. Signed-off-by: Ryan QIAN <b32804@freescale.com>
2012-02-10ENGR00174033-1 MX6 PCIE: add pcie RC driverRichard Zhu
Add PCIE RC driver on MX6 platforms. Based on iwl4965agn pcie wifi device, verified the following features. * Link up is stable * map the CFG, IO and MEM spaces, and CFG/MEM spaces can be accessed Signed-off-by: Richard Zhu <r65037@freescale.com>
2012-02-10ENGR00174128-2 Revert "Remove the discharge for VBUS and DP-2"Peter Chen
This reverts commit 4f025d73de4a55077691096eacf60f90c3b9e7af. Signed-off-by: Peter Chen <peter.chen@freescale.com>
2012-02-09ENGR00174094 i.MX6DL: Change CPU voltages to 1VNancy Chen
Change CPU voltages (0.95V and 0.85V) to 1V CPU voltage should be above 1.0V for all CPU frequency since L1 Cache power is connected to VDDARM internally. Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
2012-02-09ENGR00174152 i.mx6/clock: set ddr clock parent to pll2_mfd_400MJason Liu
on i.mx6dl, DDR clock is sourcing from pll2_mfd_400M, so, we need set DDR/periph_clk parent to pll2_mfd_400M during clock init, which will setup the clock usecount of pll2_mfd_400M correctly, otherwise, when all the child device with clock source from pll2_mfd_400M turn off, the pll2_mfd_400M will turns off automaticly, which will cause system hang due to DDR clock is off when code is runing on it. Signed-off-by: Jason Liu <r64343@freescale.com>
2012-02-09ENGR00174103 [usb hsic] add usb hsic support for mx6dlTony LIU
- change the pad setting Signed-off-by: Tony LIU <junjie.liu@freescale.com>
2012-02-09ENGR00174037-1 Add HSIC suspend/resume featureTony LIU
MSL part - For HSIC, not connect nor disconnect, then WKCN, WKDC must not be set during suspend - For HSIC, must set bit 21 in host control registry after device connected to host controller - USB PHY 480M clock output must turn on to avoid about 10ms delay before sending out resume signal - HW_ANA_MISC clkgate delay must be set to 2 or 3 to avoid 24M OSCI not stable issue Signed-off-by: Tony LIU <junjie.liu@freescale.com>
2012-02-08ENGR00172342-1 EDID parse audio data blocksAlan Tull
Add functionality to parse Audio Data Blocks from EDID data to find out what modes of LPCM are suppored by the HDMI sink device. The parsed settings are saved in the hdmi mfd. The HDMI audio driver will check the settings when the audio stream is opened and will then apply appropriate constraints. If we are unable to read from the EDID, then we default to supporting Basic Audio as defined by the HDMI specification (stereo, 16 bit, 32KHz, 44.1KHz, 48KHz PCM). Signed-off-by: Alan Tull <r80115@freescale.com>
2012-02-08ENGR00174054-2: imx6_defconfig: enable CONFIG_COMPACTIONJason Liu
Enable CONFIG_COMPACTION on imx6_defconfig to reduce the external memory fragementation Signed-off-by: Jason Liu <r64343@freescale.com>
2012-02-08ENGR00174054-1: i.mx6_defconfig: sync imx6_defconfig with v3.0.15Jason Liu
After upgrade kernel to 3.0.15, the defconfig also need be updated to sync with the kernel version change Signed-off-by: Jason Liu <r64343@freescale.com>
2012-02-08ENGR00173845 MX6Q SABRESD camera: add camera power down functionYuxi Sun
Add camera power down function and change default camera to ov5642 for parallel interface camera Signed-off-by: Yuxi Sun <b36102@freescale.com>
2012-02-08ENGR00173947-2 MX6Q/ARCH : enable the BBT support to ARM2Huang Shijie
enable the BBT support to ARM2 board. Signed-off-by: Huang Shijie <b32955@freescale.com>
2012-02-08ENGR00172274-01 - [MX6]: rework IEEE-1588 ts_clk in MX6Q ARIK CPU board.Fugang Duan
- Fix GPIO_16 IOMUX config. - Config GPIO_16 pad to ENET_ANATOP_ETHERNET_REF_OUT. - IEEE-1588 ts_clk, S/PDIF in and i2c3 are mutually exclusive, because all of them use GPIO_16, so it only for one function work at a moment. - Test result: Enet work fine at 100/1000Mbps in TO1.1. IEEE 1588 timestamp is convergent. Signed-off-by: Fugang Duan <B38611@freescale.com>
2012-02-08ENGR00174021 MX6Q/ARCH : fix the section mismatchHuang Shijie
add __init to the gpmi_nand_platform_init() to make this function store in the init.text section. Signed-off-by: Huang Shijie <b32955@freescale.com>
2012-02-07ENGR00173869-8: i.mx6: ARM2: add i.mx6dl supportJason Liu
i.mx6dl and i.mx6q share the same ARM2 board due to the pin-pin compatible between them. Signed-off-by: Jason Liu <r64343@freescale.com>
2012-02-07ENGR00173869-7: i.mx6: sdma: add i.mx6dl supportJason Liu
add i.mx6dl support for sdma Signed-off-by: Jason Liu <r64343@freescale.com>
2012-02-07ENGR00173869-6: i.mx6: gpio: add the i.mx6dl supportJason Liu
add the i.mx6dl support for gpio Signed-off-by: Jason Liu <r64343@freescale.com>
2012-02-07ENGR00173869-5: i.mx6: don't turn off MMDC clock on i.mx6dlJason Liu
MMDC clock is from pll2_pfd_400M, thus we can't turn it off Signed-off-by: Jason Liu <r64343@freescale.com>
2012-02-07ENGR00173869-4: i.mx6: add the i.mx6dl iomux supportJason Liu
externally, i.mx6dl is pin-pin compatible with i.mx6dq internally, i.mx6dl is totally different with iomux setting Checkpatch will throw some warnings in iomux-mx6dl.h file as: WARNING: line over 80 characters But for the readable, I intend not to fix these warnings, and linux upstream also has so many such kind of cases Signed-off-by: Jason Liu <r64343@freescale.com>
2012-02-07ENGR00173869-3: i.mx6: add the cpu_is_mx6dl() supportJason Liu
In order to support one image for i.mx6q and i.mx6dl, we introduce the below functions by diff the value reading from ANATOP ID register. cpu_is_mx6q() and cpu_is_mx6dl() The layout for the register defines: Major Minor i.MX6Q1.1: 6300 01 i.MX6Q1.0: 6300 00 i.MX6DL1.0: 6100 00 For the common bits shared across all i.mx6 ports, we can use: cpu_is_mx6() for it. Signed-off-by: Jason Liu <r64343@freescale.com>
2012-02-07ENGR00173869-2: i.mx6: add the i.mx6dl memory map and irq definionJason Liu
i.mx6dl shares with almost the same memory layout with i.mx6d/q except it adds some new fetures such as pxp/epdc etc. Signed-off-by: Jason Liu <r64343@freescale.com>
2012-02-07ENGR00173869-1: i.mx6: cosmetic the codeJason Liu
This is the cosmetic patch for the i.mx6 and make the prepartion for the coming i.mx6dl support. Why cosmetic? It's due to the code is a little bit mess and want to make it clean and clear. Signed-off-by: Jason Liu <r64343@freescale.com>
2012-02-07ENGR00173731-5 MX6Q/ARCH :rename gpmi-nfc to gpmi-nandHuang Shijie
rename the gpmi-nfc to gpmi-nand. Signed-off-by: Huang Shijie <b32955@freescale.com>
2012-02-07ENGR00173731-4 MX6Q/ARCH : add mxs_reset_block()Huang Shijie
add mxs_reset_block() for mx6q. In order to keep the same code as the community, I reduce the parameters to one. Signed-off-by: Huang Shijie <b32955@freescale.com>
2012-02-07ENGR00173731-1 mxs-dma : rename the dma.h for mxs-dmaHuang Shijie
Move the header to a more common place. The mxs dma engine is not only used in mx23/mx28, but also used in mx50/mx6q. It will also be used in the future chips. rename it to mxs-dma.h Acked-by: Lily Zhang <r58066@freescale.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
2012-02-07ENGR00173615 [mx5 mmc]fix mx5 build errorTony Lin
fix build error on mx5 platforms Signed-off-by: Tony Lin <tony.lin@freescale.com>
2012-02-07ENGR00173615-1 [mx6q]add mx6q_revision to common header fileTony Lin
the common API is needed by drivers to distinguish TO version Signed-off-by: Tony Lin <tony.lin@freescale.com>
2012-02-06ENGR00173846 MX6DQ_SD: add touch support for LVDS0 and LVDS1Frank Li
Add touch support. Signed-off-by: Frank Li <Frank.Li@freescale.com>
2012-02-06ENGR00173639 mx6q: clock: PLL3's power can be off at runtime at TO1.1Peter Chen
It is the fix for Design PDM TKT064178, IC has already verified it, and no more power consumption for setting/clear this bit. With this bit, the power of pll3 can be off even the power bit for pll3 is on. In order to support USB wakeup, the power bit for pll3 should be always on, and the power of pll3 is controller by USB hardware and this new added bit at runtime. Signed-off-by: Peter Chen <peter.chen@freescale.com>
2012-02-03ENGR00173586-2 [MX6] Add support to source GPT from 24MHzRanjani Vaidyanathan
On MX6Q TO1.1, MX6DL/S and MX6Solo, GPT can be sourced from a constant source (better for frequency scaling). Currently we set the GPT clock to 3MHz (24MHz div by 8). Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-02-03ENGR00173586-1 [MX6] Add support to source GPT from 24MHzRanjani Vaidyanathan
On MX6Q TO1.1, MX6DL/S and MX6Solo, GPT can be sourced from a constant source (better for frequency scaling). Currently we set the GPT clock to 3MHz (24MHz div by 8). Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-02-03ENGR00173645 [MX6]Implement low power actions into DSMAnson Huang
1. Need to follow right programming model for wb_per_at_lpm ,zeroed wb_count each time exit from DSM and set it before entering DSM; 2. For TO1.1, need to set fet_odrive for better power gate. Signed-off-by: Anson Huang <b20788@freescale.com>
2012-02-02ENGR00173659 MX6Q_UART Change Physical / Virtural Port mappingEric Sun
For ARM2 and Sabreauto, change TTY0 to TTY3 (which is physical UART4) For SabreSD, Change TTY3 to TTY0 (which is physical UART1) Mapping Changed as the following Physical Virtual -------- -------- 1 0 2 1 3 2 4 3 Signed-off-by: Eric Sun <jian.sun@freescale.com>
2012-02-02ENGR00173617 Enable LVDS on MX6DQ sabresd boardSandor Yu
Enable AUX 5V when system bootup. Enable PWM0 for LVDS backlight. Signed-off-by: Sandor Yu <R01008@freescale.com>
2012-02-02ENGR00172391 [MX6]Remove unnecessary workaround of wdog for TO1.1Anson Huang
On TO1.1, there is no such issue now, so remove the workaround, as this is a very very low possibility to reproduce this issue, and the workaround has very complicated logic, it is hard and non-necessary to add SOC version check, so just remove it. Signed-off-by: Anson Huang <b20788@freescale.com>
2012-02-01ENGR00173585: MX6: Added WAIT mode workaround for MX6Q TO1.1Ranjani Vaidyanathan
There is small window where an interrupt can occur when the SOC is in the process of entering WAIT mode. The ARM core responds to this interrupt and can access the internal memories when their clocks are disabled. To avoid crashes generated due to this, WFI code should be executed from non-cacheable IRAM and enough delay should added after the WFI so that accesses to memories are prevented. This workaround assumes that all interrupts are routed to CPU0 only. This workaround is applicable to iMX6DL/Solo also. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-02-01ENGR00173378-1 usb: device: Change judgement condition for resume occurrencePeter Chen
At former code, it uses portsc.fpr to indicate if the host sends resume signal to device, but it has some limitations that if the code can't be executed before the resume signal finishes, the portsc.fpr will be cleared automatically. Now, it uses usbsts.pci to judge host resume signal, this bit will not be cleared before the non-wakeup interrupt handler is called, and the wakeup code is executed before non-wakeup interrupt handler. Signed-off-by: Peter Chen <peter.chen@freescale.com>
2012-02-01ENGR00172395-1 MX6Q_ARM2: add sgtl5000 audio driverGary Zhang
add sgtl5000 platform data. VPC board is used to extend sgtl5000 hardware. Signed-off-by: Gary Zhang <b13634@freescale.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-24 09:45:04 +0000