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2012-09-13ENGR00223954 External SD: Failed to init external SD on SD1Jack Lee
Change the order of device registration for SDHC controller. Signed-off-by: Jack Lee <jacklee@freescale.com>
2012-09-11Merge commit 'rel_imx_3.0.35_12.09.02_RC2' into einkJack Lee
2012-09-11ENGR00223759 evK : Change F5 key to power key on Eink Add-on BoardJack Lee
Change F5 key to power key in keymap Signed-off-by: Jack Lee <jacklee@freescale.com>
2012-09-06ENGR00222170: Add mx6sl_evk_android_config for mx6sl evk boardJack Lee
- add CONFIG_MACH_MX6SL_EVK to imx6s_android_defconfig Signed-off-by: Jack Lee <jacklee@freescale.com>
2012-09-05Merge commit 'rel_imx_3.0.35_12.09.02_RC1' into imx_3.0.35_android_r13.5-betaJack Lee
Conflicts: arch/arm/mach-mx6/board-mx6q_sabresd.c arch/arm/mach-mx6/board-mx6sl_arm2.c arch/arm/mach-mx6/bus_freq.c arch/arm/mach-mx6/cpu_op-mx6.c arch/arm/plat-mxc/cpufreq.c Signed-off-by: Jack Lee <jacklee@freescale.com>
2012-09-03ENGR00222855 MX6 CPUFREQ: support three VDDSOC setpointsrel_imx_3.0.35_12.09.02Robin Gong
On MX6Q/DL , there is only two set point of VDDSOC/VDDPU, one is 1.25V(1GHz), another is 1.175V. And in arch/arm/plat-mxc/cpufreq.c will judge whether the current cpu frequency is the highest set point(1G) or not to set the right VDDSOC/VDDPU. The logic is also match to dynamic ldo bypass function, since the change point is the highest set point too. But there is three set points of VDDSOC/VDDPU in MX6SL , so the logic in cpufreq.c need to change. Now VDDSOC/VDDPU will track with VDDARM fully. Signed-off-by: Robin Gong <B38343@freescale.com>
2012-09-03ENGR00222841: mx6sl: pgc: display power gating causes PxP processing timeoutRobby Cai
For safety, DO NOT enable display power gating feature for MX6SL EVK. Otherwise will meet PxP processing timeout when run EPDC unit test. The cause is under investigation. Signed-off-by: Robby Cai <R63905@freescale.com>
2012-09-03ENGR00222834 MX6x-A9 prefetcher should not access DDR before IO is restoredRanjani Vaidyanathan
Add enough nops to suspend code when exiting due to a pending interrupt. This is required so that we can guarantee that the prefetch unit will not bring DDR out of self-refresh before all of the DDR's IO pads are restored. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-09-03ENGR00222835 MX6x-Fix incorrect enabling/disabling of PLL1Ranjani Vaidyanathan
PLL1 was enabled without incrementing the usecount, and was thus not getting disabled under certain conditions. This causes 2 issues: 1. Increases the power. 2. Causes crashes on MX6SL in audio mode as ARM is switched to PLL1 assuming its in bypass when entering WAIT mode. But PLL1 is enabled and not in bypass state. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-09-02ENGR00222257 MX6x-Prime TLB entries before DDR enters self-refresh.Ranjani Vaidyanathan
Need to ensure that no page table walk occurs in DDR when it is in self refresh and its IO pads are floated during suspend. Hence we need to make sure that the translation of all the addresses that the suspend code will access is in the TLB before DDR cannot be accessed anymore. So do a dummy read of IOMUX, MMDC, SRC and ANATOP regsiters. Also need to add a dsb to drain all the write buffers before DDR enters self-refresh. Also ensure that the LDO bypass enable is reset if an interrupt is pending before the system enters suspend. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-09-02ENGR00222157 MX6x-Fix bug in transitioning from low_bus to audio_bus mode.Ranjani Vaidyanathan
Ensure that the transtion from low bus freq mode to audio bus freq mode happens instantly. Don't schedule the delayed work in this case else there will be a pause in the audio playback. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-08-31ENGR00222134 MX6x - Fix race-conditions in low power code.Ranjani Vaidyanathan
Fix couple of race-conditions associated with low power IDLE code: 1. Ensure that bus freq mutex is used in the suspend/resume function 2. Ensure that the usecount of pll2 is incremented/decremented when ARM is switched to run from PLL2_PFD_400. And PLL2 is enabled/disabled when necessary. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-08-31ENGR00222133 MX6SL - Fix crashes caused by Low power IDLE supportRanjani Vaidyanathan
Need to ensure that the ARM_CLK rate stays exactly the same when moving ARM_CLK from PLL2_PFD_400 to PLL1 when system enters 24MHz state. Also need to ensure that PLL1 is enabled before relocking the PLL to the correct rate. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-08-30ENGR00221218: imx6: remove redundant spi defineRobby Cai
There're two imx6q_add_ecspi() defines, remove one. Signed-off-by: Robby Cai <R63905@freescale.com>
2012-08-30ENGR00222005 mfgtool can't work on mx6sl evk boardTony LIU
- add imx6s_updater_defconfig to generate mx6sl firmware - add CONFIG_MACH_MX6SL_EVK=y - remove SMP for mx6sl - add CONFIG_MX6_INTER_LDO_BYPASS=y Signed-off-by: Tony LIU <junjie.liu@freescale.com>
2012-08-29ENGR00221975 Fix race condition in clock code.Ranjani Vaidyanathan
Need to ensure that check for usecount in clk_set_parent occurs within the protection of the clock mutex. Else there is a chance that the usecount can be decremented (and the clock disabled) after the check. Also add back the code to maintain the correct usecount for pll2_pfd_400. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-08-29ENGR00221974 MX6SL-Fix system hang/crash issue in low power IDLERanjani Vaidyanathan
Ensure that the pull-up is enabled when the DQS line of LPDDR2 is floated when DDR freq is dropped to 24MHz. This is required else its possible that the DDR will latch incorrect data when it exits self-refresh. CKE line should not be floated as it may cause DDR to incorrectly exit self-refresh mode. Also add 25 nops after the code that removes DDR from self-refresh. We need this to ensure that the prefetcher block in A9 does not access any instruction from DDR before the DDR exits self-refresh. The A9 prefetch depth is about 23, hence 25 nops. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-08-29ENGR00221970 MX6SL:Fix suspend/resume issue on MX6SLEVKRanjani Vaidyanathan
Make sure the Pull Ups are enabled on the DQS lines of LPDDR2 memory. Without that its possible that the data latched by the memory will be incorrect when exiting from self-refresh mode. So only set the drive strengths to 0 when floating the DDR IO pads before entering suspend. Also never float the CKE pad, this pin always needs to be driven, else the DDR may incorrectly exit self-refresh. Hence remove the line that was setting CKE drive strength to zero (GRP_CTLDS). Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-08-30ENGR00221902 [MX6]Fix udelay inaccurate issue during suspend/resumeAnson Huang
When system enter suspend, we increase CPUFreq to the highest point without update the global loops_per_jiffy, it will lead to udelay inaccurate during the last phase of suspend/resume. WB counter and RBC counter need at least two 32K cycles to finish, here we add 80us for safe. Signed-off-by: Anson Huang <b20788@freescale.com>
2012-08-29ENGR00221867 sabresd : support adjust VDDSOC if enable LDO bypassRobin Gong
support adjust VDDSOC if enable LDO bypass on mx6_sabresd board Signed-off-by: Robin Gong <B38343@freescale.com>
2012-08-29ENGR00221716-02 Mx6 USB host: add port speed define MACRO to arc_otg.hmake shi
Add port speed define MACRO to arc_otg.h. Signed-off-by: make shi <b15407@freescale.com>
2012-08-29ENGR00221716-01 Mx6 USB host: set disconnect bit should wait for resume finishedmake shi
For i.MX6DLTO1.1 and i.MX6DQTO1.2, the disconnection-bit can only be set after the resume finished, otherwise, the remote-wake-up may fail. Because if the device not switch to High-Speed 45ohm termination resistors mode, when the disconnection detection bit is set the disconnection detection circuit will detect a high speed disconnection by mistake. Signed-off-by: make shi <b15407@freescale.com>
2012-08-29ENGR00221643 [MX6]Fix race condition of pfd 400 usecountAnson Huang
We can't modify the usecount of pfd 400M clock when ARM freq is changed, as when the children of pfd 400M do clock enable/disable, they will also modify this usecount, these two modification is out of same lock protection. And this wrong usecount may lead to pfd 400M or pll2 disabled accidently, and it will cause system hang! Signed-off-by: Anson Huang <b20788@freescale.com>
2012-08-29ENGR00221438 [MX6]Adjust CPU setpoint according to datasheetAnson Huang
1. Adjust ARM/SOC/PU voltage according to latest datasheet; 2. Remove Rigel's 200M setpoint to align with Arik. Signed-off-by: Anson Huang <b20788@freescale.com>
2012-08-28ENGR00221302 [MX6SL_ARM2/EVK]: VDDSOC adjust if use LDO bypassRobin Gong
The function has been implement in LDO enable , but not in LDO bypass. Implement it on mx6sl. Signed-off-by: Robin Gong <B38343@freescale.com>
2012-08-27ENGR00221457 MX6DL clock:Set PLL3_PFD_540M to 540MHzLiu Ying
This patch sets PLL3_PFD_540M clock frequency to 540MHz so that IPU and VPU clock can reach 270MHz. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> (cherry picked from commit faf59e846f03b37c65996e58d045de8d64481283)
2012-08-27ENGR00221438 [MX6]:Remove Rigel's 200M working pointLin Fuzhen
Remove Rigel's 200M working point to align with Arik Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
2012-08-27ENGR00221457 MX6DL clock:Set PLL3_PFD_540M to 540MHzLiu Ying
This patch sets PLL3_PFD_540M clock frequency to 540MHz so that IPU and VPU clock can reach 270MHz. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
2012-08-26ENGR00221161 [MX6SL]- Add audio bus freq mode support.Ranjani Vaidyanathan
Set DDR to 50MHz in low power audio playback. AHB/AXI are at 24MHz. Also fix correct usecount for PLL1 main clock. If not it causes issues when pll1_sw_clk's parent is changed. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-08-26ENGR00221440 MX6x-Fix race-condition in checking bus_freq variablesRanjani Vaidyanathan
Checking of the bus_freq variables and changing of the bus/ddr frequency should be done under one mutex. Else there is a race-condition that the variable changed just after it was checked. Also ensure that the bus freq is always increased before the cpu freq is set to anything other than the lowest setpoint. Else there is a possibility that the ARM is set to run from PLL1 at higher frequency when bus/DDR are still at 24MHz. This is dangerous since when system enters WAIT mode in low bus freq state, PLL1 is set to bypass when ARM is being sourced from it. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-08-26ENGR00221441 MX6SL - Update voltages based on the latest datasheet.Ranjani Vaidyanathan
Add a new working point table to MX6SL and set the voltages according to the latest datasheet. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-08-24ENGR00220796-3: imx6sl arm2/evk: Add platform_device for V4L2 supportRobby Cai
Add platform device for V4L2 support Signed-off-by: Robby Cai <R63905@freescale.com>
2012-08-24ENGR00221317-02 Mx6 USB host: set stop_mode_config when any USB host enabledmake shi
The Mx6 phy sometimes work abnormally after system suspend/resume if the 1V1 is off. So we should keep the 1V1 active during the system suspend if any USB host enabled. - Add stop_mode_config to 1 with refcount - Add mutex to protect the refcount and HW_ANADIG_ANA_MISC0 register - If stop_mode_config is set as 1, the otg vbus wakeup system will be supported Signed-off-by: make shi <b15407@freescale.com>
2012-08-24ENGR00221317-01 Mx6 USB host: set stop_mode_config when any USB host enabledmake shi
MSL headfile part change. Signed-off-by: make shi <b15407@freescale.com>
2012-08-24ENGR00221277 MX6DL/S - Set AXI clock to 270MHzimx-android-r13.4-betaRanjani Vaidyanathan
Change AXI_CLK to be sourced from PLL3_PFD1_540MHz, so that it can run at 270MHz on MX6DL/S. This is required for improving VPU performance. Change AXI_CLK to be sourced from periph_clk just before the DDR freq is going to be dropped to 24MHz/50MHz. Change it back to PLL3_PFD1_540 when the DDR freq is back at 400MHz. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-08-23ENGR00221277 MX6DL/S - Set AXI clock to 270MHzRanjani Vaidyanathan
Change AXI_CLK to be sourced from PLL3_PFD1_540MHz, so that it can run at 270MHz on MX6DL/S. This is required for improving VPU performance. Change AXI_CLK to be sourced from periph_clk just before the DDR freq is going to be dropped to 24MHz/50MHz. Change it back to PLL3_PFD1_540 when the DDR freq is back at 400MHz. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-08-23ENGR00221281 [MX6X] Fix BogoMIPS value is not correctNancy Chen
[MX6X] Fix BogoMIPS value is not correct Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
2012-08-23ENGR00221131: imx6sl arm2/evk: add mma8450q accelerometer supportRobby Cai
mma8450q on E-INK DC3 boards, with i2c address 0x1c on I2C1. Signed-off-by: Robby Cai <R63905@freescale.com>
2012-08-23ENGR00221214 MX6Q/DL SabreSD: avoid pop-noise on audio padsGary Zhang
config audio pads to avoid pop-noise Signed-off-by: Gary Zhang <b13634@freescale.com>
2012-08-23ENGR00221102-2 MX6Q: increase VPU frequence to 352MhzRobin Gong
Increase VPU frequency to 352Mhz for TV box, use pll2_pfd_400M.To avoid impact other code which assume ARM clock sourcing from pll2_pfd_400M, change cpu setpoint of 396M to 352M. and disable bus freq adjust. add CONFIG_MX6_VPU_352M to choose it, default is disabled. Signed-off-by: Robin Gong <B38343@freescale.com>
2012-08-22ENGR00220989 [MX6SL]: DDR Controller measure unit workaroundNancy Chen
[MX6SL]MMDC: DDR Controller's measure unit may return an incorrect value when operating below 100 MHz Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
2012-08-22ENGR00220834 Disable GPU IRQ trigger for CPU governor to save powerRichard Liu
Disable GPU IRQ trigger for CPU governor to save power Current GPU trigger will let CPU work at 1G no matter any 3D draw that make much power waste, to balance power and performance we desire to disable GPU trigger for CPU governor, this change will impact some benchmark performance but the drop is acceptable, android will add performance mode, for any demo or customer who care performance more than power please select performance mode. Signed-off-by: Richard Liu <r66033@freescale.com> Acked-by: Lily Zhang
2012-08-21ENGR00220696 [MX6SL]-Reduce IDLE mode power consumption.Ranjani Vaidyanathan
When ARM enters WFI in low power IDLE state, float the DDR IO pins to drop the power on the VDDHIGH rail. Need to run WFI code from IRAM since DDR needs to be put into self-refresh before changing the IO pins. Drop AHB to 8MHz and DDR to 1MHz when ARM is in WFI when in IDLE state. Set IPG_PERCLK to run at 3MHz, since we want to maintain a 1:2.5 ratio between PERCLK to AHB_CLK. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-08-22ENGR00220370 [MX6]Fix BUS freq suspend/resume fail in low bus modeAnson Huang
1. BUS freq's set low bus setpoint using delat work, which didn't have mutex lock, so in some scenarios, set high bus freq function can be called at the same time, we need to move mutex lock into these two routine; 2. Using pm notify to make sure bus freq set to high setpoint before supend and restore after resume. 3. Clear build warning. Signed-off-by: Anson Huang <b20788@freescale.com>
2012-08-22ENGR00220388 [MX6]Adjust SOC/PU voltage according to datasheetAnson Huang
SOC/PU voltage need to following some rules according to latest datasheet: 1. SOC/PU CAP voltage must be 1.15V <= SOC/PU <= 1.3V; 2. SOC and PU must be same as they don't have level shift; 3. Adjust previous wrong voltage setting. If SOC/PU voltage is too low, may cause system crash on some chips, we have a board that easily crash with GPU working and doing some tar operation, with this voltage adjust, this issue fixed. Signed-off-by: Anson Huang <b20788@freescale.com>
2012-08-22ENGR00220497 [MX6Q, MX6DL]: Fix not able to set high bus freqNancy Chen
Fix not able to set high bus frequency from low bus frequency. Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
2012-08-22ENGR00220154 GPT mx6: move mx6_timer_rate to clock.cRobin Gong
System will report oops as below. To fix it we will move mx6_timer_rate to clock.c, so that we can avoid use clk_get_sys which cause schedule after spin_lock. oops log: BUG: scheduling while atomic: kinteractiveup/1403/0x00000002 Modules linked in: (unwind_backtrace+0x0/0xfc) from [<804f05f0>] (__schedule+0x4b8/0x6b0) (__schedule+0x4b8/0x6b0) from [<804f12ac>] (__mutex_lock_slowpath+0x138/0x208) (__mutex_lock_slowpath+0x138/0x208) from [<804f13b4>] (mutex_lock+0x38/0x3c) mutex_lock+0x38/0x3c) from [<803b9134>] (clk_get_sys+0x1c/0xec) (clk_get_sys+0x1c/0xec) from [<8005f814>] (mx6_timer_rate+0x14/0x7c) (mx6_timer_rate+0x14/0x7c) from [<80056a20>] (_clk_gpt_get_rate+0x18/0x2c) (_clk_gpt_get_rate+0x18/0x2c) from [<8005e89c>] (clk_get_rate+0x34/0x40) (clk_get_rate+0x34/0x40) from [<80055f3c>] (_clk_pll_enable+0xa8/0x1ec) (_clk_pll_enable+0xa8/0x1ec) from [<80056088>] (_clk_pll1_enable+0x8/0x20) (_clk_pll1_enable+0x8/0x20) from [<80056998>] (_clk_arm_set_rate+0x278/0x2e8) (_clk_arm_set_rate+0x278/0x2e8) from [<8005e824>] (clk_set_rate+0x54/0x68) (clk_set_rate+0x54/0x68) from [<80061660>] (set_cpu_freq+0xb8/0x160) (set_cpu_freq+0xb8/0x160) from [<800618b4>] (mxc_set_target+0xf0/0x20c) (mxc_set_target+0xf0/0x20c) from [<80372388>](__cpufreq_driver_target+0x54/0x60) Signed-off-by: Robin Gong <b38343@freescale.com>
2012-08-22ENGR00220153 cpufreq mx6: new cpu set point and add VDDSOC/PU adjustRobin Gong
1.add new cpu setpoint: replace 498Mhz with 672Mhz,and remove 198Mhz. but now 498Mhz seems not stable enough, comment now, test enough to add it. Rigel kept unchange now. 2.support adjusting VDDSOC/VDDPU when cpu frequency change. Signed-off-by: Robin Gong <b38343@freescale.com>
2012-08-21ENGR00220776 mx6dl_arm2: ECSPI pin config overlaped by epdcRobin Gong
ECSPI pin MX6DL_PAD_EIM_D17__ECSPI1_MISO is configured overlap by epdc MX6DL_PAD_EIM_D17__GPIO_3_17, so that SPI-NOR flash can't work normally. From schematic of ARM2 board, epdc and spi share this pin if plug epdc daughter board. But SPI-NOR is on ARM2 mother board, so it should be config well firstly. So we make sure SPI-NOR work successfully by default. But if enable epdc , SPI-NOR on ARM2 will work fail. Signed-off-by: Robin Gong <B38343@freescale.com>
2012-08-21ENGR00220833 mx6sl: USB hsic: enable mx6sl hsic functionmake shi
- Set MX6SL_PAD_HSIC_DAT and MX6SL_PAD_HSIC_STROBE pad DDR attribute as DDR3 - Add imx6sl_add_fsl_ehci_hs and imx6sl_add_fsl_usb2_hs_wakeup in usb_h2.c Signed-off-by: make shi <b15407@freescale.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-25 01:24:00 +0000