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2012-05-23arm: tegra: cardhu: add TEGRA_CARDHU_DUAL_DSI_PANEL config optionPreetham Chandru
add TEGRA_CARDHU_DUAL_DSI_PANEL config option to enable or disable dual dsi panel in cardhu Bug 935764 Signed-off-by: Preetham Chandru R <pchandru@nvidia.com> Change-Id: I9a93386c046f5845a3dcf55c575de6b8e67f188d Reviewed-on: http://git-master/r/96706 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-23arm: tegra: kai: change thermal sensor to nct72Chandler Zhang
Kai board uses OnSemi NCT72 thermal sensor. NCT72 is pin and register compatible to NCT1008. Change the i2c device id from "nct1008" to "nct72" to avoid confusion. Bug 961970 Reviewed-on: http://git-master/r/100466 Signed-off-by: Chandler Zhang <chazhang@nvidia.com> (cherry picked from commit 07ed4a320ff7e18e615270e0e15bd4212e6a7c9f) Change-Id: I6ef858d27b1b1f35ddd071542bb22caed2e776ab Reviewed-on: http://git-master/r/103582 Tested-by: Daniel Fu <danifu@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Chandler Zhang <chazhang@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-05-21arm: tegra: Added support for TDM mode paramsNitin Pai
Added TDM mode params to be passed from platform to the machine driver Bug 948478 Change-Id: I909db0ceebde002fcebcf7635cebe98c6a74142d Signed-off-by: Nitin Pai <npai@nvidia.com> Reviewed-on: http://git-master/r/103594 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Scott Peterson <speterson@nvidia.com>
2012-05-21ARM: tegra: clock: Account for memory BW efficiencyAlex Frid
Account for memory efficiency when processing requests from Tegra3 EMC shared bandwidth users. Do not round requests from these users until they are aggregated. The respective debugfs node: /d/tegra_emc/efficiency (in %). Bug 952739 Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit 86929087f68c4366d6179101eb9a6a6473a4f084) Change-Id: I4acdd89f44de1401ce5dad8fc4936932df014458 Reviewed-on: http://git-master/r/103499 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Jihoon Bang <jbang@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com> GVS: Gerrit_Virtual_Submit
2012-05-21ARM: tegra: clock: Share Tegra3 camera EMC bandwidthAlex Frid
Change Tegra3 camera EMC shared user mode from SHARED_FLOOR to SHARED_BW and combine requests from ISO clients (camera and display, which is already in SHARED_BW mode). Bug 652739 Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit f1107ea4fe229d9807c1fba79a003753d0a8be7f) Change-Id: If5b7f578060a646df1794dde8c9be2944d88e942 Reviewed-on: http://git-master/r/103498 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com> GVS: Gerrit_Virtual_Submit
2012-05-21arm: tegra: apbdmaio: Add dma_sync* callsPradeep Kumar
Add dma_sync* calls to make memory coherent between CPU and Device. Bug 983988 Change-Id: I40c514e01130762a12833c3ab7e0613f984870c6 Signed-off-by: Pradeep Kumar <pgoudagunta@nvidia.com> Reviewed-on: http://git-master/r/103336 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> GVS: Gerrit_Virtual_Submit
2012-05-21ARM: tegra: define/enable ARCH_HAS_SUSPEND_PAGETABLEChris Johnson
For Tegra, the CPU suspend code path installs its own 1:1 pagetable setup once at init time. This pagetable is used by all CPUs doing suspend/resume. We want to use the common ARM code for CPU suspend/resume, but don't want the MMU reenable code to patch the current pagetable as it's shared (and could cause problems if the pagetable loads/stores were were interleaved). The installed pagetable already covers the cpu_resume_turn_mmu_on VA, so we're able to just use the existing pagetable. This sets up the CONFIG option to skip this part of the MMU reenable. Bug 929856 Change-Id: Ibbac258122df6def7f7a2d511778a6f11d474938 Signed-off-by: Chris Johnson <cwj@nvidia.com> Reviewed-on: http://git-master/r/92350 Reviewed-by: Sang-Hun Lee <sanlee@nvidia.com> Tested-by: Sang-Hun Lee <sanlee@nvidia.com> Reviewed-by: Thomas Cherry <tcherry@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Ahung Cheng <ahcheng@nvidia.com> Tested-by: Ahung Cheng <ahcheng@nvidia.com> Reviewed-on: http://git-master/r/103205 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-21ARM: vfp: ensure preemption is disabled when enabling VFP accessWill Deacon
The vfp_enable function enables access to the VFP co-processor register space (cp10 and cp11) on the current CPU and must be called with preemption disabled. Unfortunately, the vfp_init late initcall does not disable preemption and can lead to an oops during boot if thread migration occurs at the wrong time and we end up attempting to access the FPSID on a CPU with VFP access disabled. This patch fixes the initcall to call vfp_enable from a non-preemptible context on each CPU and adds a BUG_ON(preemptible) to ensure that any similar problems are easily spotted in the future. originally from http://git.kernel.org/?p=linux/kernel/git/will/linux.git;a=commit;h=468c963e0210bf8108b17cf75066f25f39cabb56 Change-Id: I26fff8abe4c18bd3291613f70d0228aa2313811a Reported-by: Hyungwoo Yang <hwoo.yang@gmail.com> Signed-off-by: Hyungwoo Yang <hyungwooy@nvidia.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Reviewed-on: http://git-master/r/102315 GVS: Gerrit_Virtual_Submit Reviewed-by: Thomas Cherry <tcherry@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-05-21Revert "ARM: vfp: Prevent process migration"Hyungwoo Yang
This reverts commit 68667feb8eae225f1293a7044c989ab0bba8dbd1. Change-Id: I59023f2d83392465f7a989693b67cef96d565ed9 Signed-off-by: Hyungwoo Yang <hyungwooy@nvidia.com> Reviewed-on: http://git-master/r/102314 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-05-21arm: tegra: governor: change governor using cpufreq interfacePuneet Saxena
Older code sets "conservative" governor in early-suspend using sysfs entries.This implementation changes governor in early-suspend using cpufreq interfaces. bug 871958 Change-Id: I721afb6184982a063dc5f330da31f8fb88481cfd Signed-off-by: Puneet Saxena <puneets@nvidia.com> Reviewed-on: http://git-master/r/100849 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-21ARM: tegra: decouple mode from flagsBo Yan
When doing LP2 on last standing CPU, we currently pass "mode | flag" to a few functions as argument, with the assumption that "mode" will be confined to lower 22 bits in PMC_CTRL register and "flags" will occupy higher 10 bits. If "flags" grows downward or "mode" grows upward, without this explicit knowledge, LP2 will break on the last standing CPU. Therefore we need to decouple them. Currently only "flags" part is being used when passed to other subroutines, so use "flags" only. Change-Id: I299c998145d81c17760bda8a0b56311fed553958 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/100358 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-21ARM: Tegra: P1852: changed nor timing regs and freqMohit Kataria
Nor frequency and timing registers changed as per values provided by syseng Bug 978870 Change-Id: I18313c7df6265ddd4140d264ac2751ed8f1982df Reviewed-on: http://git-master/r/103355 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Mohit Kataria <mkataria@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-05-21ARM: tegra: cardhu: add A07 memory tableRay Poudrier
Bug 970890 Change-Id: If0ebb1ad76dfe3267bc0acd3feae70a701c1dfdb Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com> Reviewed-on: http://git-master/r/103237 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-05-21arm: thermal: Removed nonTEGRA_THERMAL_SYSFS logicJoshua Primero
All throttling must go through the Linux thermal sysfs framework now. Change-Id: Ia871e0b06e548d5d82211a65979bea52a6c28fb0 Signed-off-by: Joshua Primero <jprimero@nvidia.com> Reviewed-on: http://git-master/r/103183 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-21arm: tegra: thermal: removed TEGRA_THERMAL_SYSFSJoshua Primero
Removed the CONFIG_TEGRA_THERMAL_SYSFS option. Any throttling activities must go through the Linux thermal sysfs framework now via CONFIG_THERMAL. Change-Id: Ibe680d82d3225994e6bebcfe75a0f058e567e35c Signed-off-by: Joshua Primero <jprimero@nvidia.com> Reviewed-on: http://git-master/r/103182 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-21arm: tegra: xmm: pm qos for modem enumerationVinayak Pane
XMM modem first enumeration has timing requirement, so khubd should perform enum within 1 second. An issue is seen sometimes when the hub events are not sent on time (on fully loaded system) and then khubd timesout. This patch adds PM QOS request to bump up the cpu frequency for 2 seconds. Bug 946027 Change-Id: I1a43c043d42cfa442517a2a7ad8d69a934d4ab47 Signed-off-by: Vinayak Pane <vpane@nvidia.com> Reviewed-on: http://git-master/r/102697 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-21arm: tegra: xmm: simultaneous L3 to L0 wakeupVinayak Pane
In AP initiated L3->L0 wakeup xmm power state is set BBXMM_PS_L3TOL0 but if CP is also trying to wakeup then ipc_ap_wake_irq with falling edge treats it incorrectly as CP wakeup pending - new race condition. Adding a check to fix this scenario for both L3 and L3TOL0 states. Bug 966077 Change-Id: I3af3538b48745588f17e4c13a3e23e4033f21821 Signed-off-by: Vinayak Pane <vpane@nvidia.com> Reviewed-on: http://git-master/r/102698 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Steve Lin <stlin@nvidia.com>
2012-05-21video: tegra: dc: Init hdmi's platform data and fbShashank Sharma
1. Change hdmi platform data structure's xres and yres values. These values were made same as LVDS panel (1366x768). LVDS runs fix display mode,but HDMI can switch to different modes. The new values (640x480) are corresponding to HDMI's fallback mode resolution. 2. Map bootloader's framebuffer content to fb1 also, to initialize fb1's content, and to avoid black & white strips when hdmi gets enabled but has no content in fb. It sometimes causes inconsistency on fb_console mapped on HDMI. Bug: 930136 Change-Id: Iecf0d8c1cdd6a1baec2aec9c5dded3d73d1347e1 Signed-off-by: Shashank Sharma <shashanks@nvidia.com> Reviewed-on: http://git-master/r/103381 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jon Mayo <jmayo@nvidia.com>
2012-05-18ARM: tegra: pcie: Fix for second pcie port detection.Manoj Chourasia
PCIE card on second port doesn't get detected if the first port is empty. If the link for first port is reset and the second port is queried for card, it doesn't get detected. Fix for the issue is do not reset the link if the port is not detected in third attempt. bug 970206 Change-Id: I4e4d32c22697b817381834ac746417437016d7f3 Signed-off-by: Manoj Chourasia <mchourasia@nvidia.com> Reviewed-on: http://git-master/r/101986 (cherry picked from commit c085f6b1b3a77b7aae3b04e22c7a9bfed8517c1e) Reviewed-on: http://git-master/r/103077 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-18ARM: tegra: cardhu: add initial A07 supportRay Poudrier
Bug 970890 Change-Id: I24c3b1e2c621afbb90ced552194403f147e20a6c Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com> Reviewed-on: http://git-master/r/102984 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-05-18arm: tegra: nvmap: remove nvmap.h from mach-tegra/include.Krishna Reddy
It is moved to kernel/include. Bug 854182 Change-Id: I3fb729c88e29a9f213656fbf20810c10dfd9d7a6 Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/102727 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Jon Mayo <jmayo@nvidia.com> Reviewed-by: Bo Yan <byan@nvidia.com>
2012-05-18ARM: tegra: cardhu: add pm267 to kbc int keysRay Poudrier
Bug 896071 Change-Id: I1bcd8069bfccdd80a1506e71bb9cc0353b9ea9a6 Conflicts: arch/arm/mach-tegra/board-cardhu-kbc.c Change-Id: I29af7c5289ae06757eb9cffce3065db08b3e8d06 Reviewed-on: http://git-master/r/97734 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-18ARM: defconfig: enable background opsVishal Singh
Enable background ops on p852 and p1852. Bug 847037. Change-Id: Ib72d361aba5cf08c171976e6f5bf0ffa555e1471 Signed-off-by: Vishal Singh <vissingh@nvidia.com> Reviewed-on: http://git-master/r/99121 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2012-05-18ARM: tegra: smmu: Use non-secure register for sync-readHiro Sugawara
Bug 973463 Change-Id: Ia2e42232e6f10d12387b2bc3bbee1f996e7aea9d Signed-off-by: Hiro Sugawara <hsugawara@nvidia.com> Reviewed-on: http://git-master/r/101837 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-05-18video: tegra: dc: add per window global alphaJon Mayo
Adds a global alpha parameter to each window. It provides a default alpha value for pixel formats that do not include alpha. Change-Id: I5465864877a727b4daed0eb32fb8219e2ccb663e Signed-off-by: Jon Mayo <jmayo@nvidia.com> Reviewed-on: http://git-master/r/101806 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-05-18ARM: tegra: smmu: Save & restore correct SMMU registersHiro Sugawara
Bug 981373 Change-Id: I8617ca0ffd7df570b8ee6f3cad524decf6c26437 Signed-off-by: Hiro Sugawara <hsugawara@nvidia.com> Reviewed-on: http://git-master/r/101285 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-05-18arm:tegra:pcie: Resolve section mismatch warningJay Agarwal
Bug 984434 Change-Id: I7184fc77132485ab24357e5f2c965ddf4eca6a07 Signed-off-by: Jay Agarwal <jagarwal@nvidia.com> Reviewed-on: http://git-master/r/103112 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-05-18arm: tegra: Use nvmap.h include file from kernel/includeKrishna Reddy
Use nvmap.h include file from kernel/include instead of mach-tegra/include. Bug 854182 Change-Id: Ic82b35d6c2e1c49461575a7bbbfd28ee43921466 Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/102723 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Jon Mayo <jmayo@nvidia.com>
2012-05-17ARM: tegra3: defconfig: enable MAX8973Pradeep Kumar
Enable MAX8973 voltage regulator chip. bug 981355 Change-Id: Ifdb3dd89b0e36c2a8500f8aa1e49884cbc6761d5 Signed-off-by: Pradeep Kumar <pgoudagunta@nvidia.com> Reviewed-on: http://git-master/r/102805 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-05-17ARM: tegra: emc: add eack_disable functionalityRay Poudrier
Bug 946110 Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com> Change-Id: I0d4c716c4ab7a60011018d6c13be4265cc9f7290 Reviewed-on: http://git-master/r/87061 (cherry picked from commit a7dad880dcea36fcb8223cf0b34cc1091d725a9f) Reviewed-on: http://git-master/r/102360 Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com> Tested-by: Raymond Poudrier <rapoudrier@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-05-17arm: tegra kai:fix screen flicker when kernel boot up.Linqiang Pu
set vdd_pnl as 'boot_on' to avoid dropping panel VDD. Bug 965398 959819 Signed-off-by: Linqiang Pu <dpu@nvidia.com> Reviewed-on: http://git-master/r/95398 (cherry picked from commit 9f423c83e391fa8581de2c088b4dea8248da8ae1) Change-Id: I513e004f7ec1a46c155825af9e6278c46ca444c5 Reviewed-on: http://git-master/r/96643 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-05-17arm: tegra: kai: change SD1 power up periodJinyoung Park
To reduce delay between CORE_PWR_REQ and VDD_CORE, changed SD1 power up period from 1 to 0. Bug 930883 Change-Id: I50ea110d0cb72402b5d03c3e260e6ab340d87fbe Signed-off-by: Jinyoung Park <jinyoungp@nvidia.com> Reviewed-on: http://git-master/r/92704 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-05-17ARM: tegra: Modify tegra_apb functionsPrashant Malani
Make tegra_apb_readl() , tegra_apb_writel() T20 only Bug 950116 Change-Id: I75601bebaee14ed2e217a16c0e46fb2910c421c8 Signed-off-by: Prashant Malani <pmalani@nvidia.com> Reviewed-on: http://git-master/r/102712 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com>
2012-05-17ARM: tegra: power: Don't enable auto-hotplug as PM QoS side-effectAlex Frid
On Tegra3, if PM QoS hotplug request is received when auto-hotplug is disabled, do not enable auto-hotplug as side effect of the request. Change-Id: I8928d9ecd22e2d2df5fe60274fed30da0c565b47 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/102118 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Donghan Ryu <dryu@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
2012-05-16arm: tegra: xmm: baseband modem pm code cleanupVinayak Pane
- Platform data is treated as const and not modified in driver. - Driver specific data is stored and used from a new structure. - Remove support for older firmware version of XMM modem (<1130). - Shortening of names for compliance and to fit in 80 characters. - Organize irq function to reduce indentation. Change-Id: I269401aa0a2efc685d7a630b4952cb31cbca6a4f Signed-off-by: Vinayak Pane <vpane@nvidia.com> Reviewed-on: http://git-master/r/101587 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Steve Lin <stlin@nvidia.com>
2012-05-16Arm: p1852: dvfs: Added ASIC SKUs as per updated PORMohit Kataria
Automotive platforms are broken down further into 5 Asic skus from 3 ASIC SKUs, updated kernel to reflect these changes. Bug 983555 Change-Id: I75925c5853d4ec2a5c72e430f4c2380e58aae774 Signed-off-by: Mohit Kataria <mkataria@nvidia.com> Reviewed-on: http://git-master/r/101903 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
2012-05-15ARM: tegra3: defconfig: enable TPS6238X0Pradeep Kumar
Enable TPS6238X0 voltage regulator chip. Bug 981330 Change-Id: I0d4207543cd2d2c1b2977536ea7299b5b65fc600 Signed-off-by: Pradeep Kumar <pgoudagunta@nvidia.com> Reviewed-on: http://git-master/r/102588 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-15arm: tegra: pm269: update sh532u configCharlie Huang
bug 980184 Change-Id: I376a62ada8f7e825693a4cdd87942edaa92b8fc4 Signed-off-by: Charlie Huang <chahuang@nvidia.com> Reviewed-on: http://git-master/r/102309 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-15ARM: config: tegra: Enable SECTION_MISMATCH warningLaxman Dewangan
Some of our driver generate the section mismatch warning but details of the error is not displayed. Enable config variable to display all such warning during compilation. Change-Id: Ie0a6dc10cc20304b74a7712717adb44a86474247 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/102183 Reviewed-by: Automatic_Commit_Validation_User
2012-05-14ARM: tegra: cardhu: wakeup system from GPIO_PV0 without key detectionLaxman Dewangan
To meet the LP0 exit power on sequence, it is require to wake system for tegra gpio in place of PMIC for E1291-A04. Also it is observed that if GPIO key is used to wakeup then there is possibility of loosing the key event and hence adding the gpio GPIO_PV0 as the key with code of RESERVED so that it can only wakeup system but will not able to send the key event through gpio keys. bug 981320 Change-Id: I8610adca4b5ed8ae79f8fcca9a1d4b5548158c60 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/101784 Tested-by: Sang-Hun Lee <sanlee@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
2012-05-14ARM: tegra: pm: suspend trace eventSivaram Nair
A new trace event is added for tracing cpu suspend start and end Change-Id: I2506e3aed0692c44fb4325e9d381cea53228b0c3 Signed-off-by: Sivaram Nair <sivaramn@nvidia.com> Reviewed-on: http://git-master/r/101748 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
2012-05-14arm: tegra: p1852: Add Tegra camera driverSonghee Baek
Add Tegra camera driver to support video capture through H/W interfaces VIP, CSI. Bug 978086 Change-Id: I0dc51e47928388ed2073a99f8ca80b5a5a77d166 Signed-off-by: Songhee Baek <sbaek@nvidia.com> Reviewed-on: http://git-master/r/101590 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-14ARM: tegra: clock: Export clock minimumAntti P Miettinen
Add clock minimum to debugfs. Bug 917644 Change-Id: Ie088809829af2bdc81a969a034bf00847459f0ce Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com> Reviewed-on: http://git-master/r/101555 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-14arm: tegra: sdhci: Limit eMMC,SDIO,SD DDR clockPavan Kunapuli
Limit eMMC, SD and SDIO DDR mode clock to 41MHz. Bug 967719 Change-Id: Iaccc5b771b81b15226f87684b547ad1fb7dd38d3 Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-on: http://git-master/r/101173 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-05-14arm: tegra: clock: Add tegra3 sdmmc4 EMC shared userPavan Kunapuli
Adding tegra3 sdmmc4 EMC shared user in the tegra3 clock table. Bug 967719 Change-Id: I934dcaebf664f8b1db9ea07eef07eb6f266822aa Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-on: http://git-master/r/100582 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-14arm: tegra: sdhci: Define ddr50 clock limitPavan Kunapuli
Added a new variable in sdhci platform data which will limit the ddr50 mode clock. Bug 967719 Change-Id: I3f55b55651362447845c2e1d5000939e3e028df6 Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-on: http://git-master/r/100569 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-05-14drivers: video: tegra: Implement HOST1X syncpt initTerje Bergstrom
Move initialization for HOST1X sync point irq to nvhost driver. Bug 871237 Change-Id: I0d31e03b43999c609194665cdcbd2f0e498d848f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/100250 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
2012-05-14ARM: tegra: Correction of safe optionAshwini Ghuge
Corrected safe option for LPW0 and LPW2 Bug 920686 Change-Id: I14e1a22de3338ba569d3b381508e123d12aad059 Reviewed-on: http://git-master/r/101973 Tested-by: Ashwini Ghuge <aghuge@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-05-14arm: tegra: cardhu: add ov5640 supportCharlie Huang
bug 921322 Change-Id: If7f05c632816abac54852293ebd3834b5b3984d8 Signed-off-by: Charlie Huang <chahuang@nvidia.com> Reviewed-on: http://git-master/r/99508 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-05-14ARM: config: tegra3: enable CONFIG_REGULATOR_USERSPACE_CONSUMERLaxman Dewangan
By enabling the user space regulator consumer, it is possible to control the rail from userspace through sysfs. bug 966960 Change-Id: I0f4a7a0afdc998d58e6448e4f621ee4e430a7ef6 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/100320 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-01 02:37:40 +0000