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AgeCommit message (Expand)Author
2011-11-30arm: tegra: enterprise: Enabling Security EngineKasoju Mallikarjun
2011-11-30ARM: tegra: usb: update default UTMIP phy settingJay Cheng
2011-11-30ARM: tegra: power: use buffered memory for suspend contextJin Qian
2011-11-30ARM: tegra: power: Enable LP2 mode on Cardhu platformScott Williams
2011-11-30ARM: tegra2: power: Don't disable CPU1 GIC interface in LP2Scott Williams
2011-11-30ARM: tegra: power: Perform L2 cache sync when flushing L1Scott Williams
2011-11-30ARM: tegra2: power: Fix reset race condition between the CPUsScott Williams
2011-11-30ARM: tegra: timer: Save TWD counter instead of load registerScott Williams
2011-11-30ARM: tegra: power: Workaround PMD corruption by cpu_resume_mmuScott Williams
2011-11-30ARM: tegra2: power: Don't flush D-cache on aborted LP2 with L2Scott Williams
2011-11-30ARM: tegra: power: Map the CPU context page to tegra_pgdScott Williams
2011-11-30ARM: tegra: power: Consolidate PM_SLEEP conditionalsScott Williams
2011-11-30ARM: tegra: power: Conditionalize diagnostic register save/restoreScott Williams
2011-11-30ARM: tegra: power: Fix build errors when DVFS is enabledScott Williams
2011-11-30ARM: tegra: Fix mutex in atomic context when updating TWD freqScott Williams
2011-11-30ARM: tegra: power: Rename variables for consistencyScott Williams
2011-11-30ARM: tegra: power: Fix Tegra2 secondary CPU LP2 time calculationScott Williams
2011-11-30ARM: tegra: power: Save CPU context to non-cacheable stackScott Williams
2011-11-30ARM: tegra: power: Add stack frame debug checksScott Williams
2011-11-30ARM: tegra: power: Define push/pop context register macrosScott Williams
2011-11-30ARM: tegra: power: Use uniform save/restore register setScott Williams
2011-11-30ARM: tegra: power: Use standard definitions for SCTLRScott Williams
2011-11-30ARM: tegra: power: Consolidate CPU context save and SMP exitScott Williams
2011-11-30ARM: tegra: power: Clear cache/TLB forwarding when exiting SMPScott Williams
2011-11-30ARM: tegra: power: Add SMP coherency exit macroScott Williams
2011-11-30ARM: tegra: power: Delete obsolete functionScott Williams
2011-11-30ARM: tegra: Use common coherency exit function for Tegra2Scott Williams
2011-11-30ARM: tegra: power: Fix suspend pgd identity mappingScott Williams
2011-11-30ARM: tegra: power: Allocate non-cacheable page for CPU contextScott Williams
2011-11-30ARM: tegra: power: Put power functions under CONFIG_PM_SLEEPScott Williams
2011-11-30ARM: tegra: power: Reorganize CPU idle codeScott Williams
2011-11-30ARM: tegra: power: Disable power management if pgd alloc failsScott Williams
2011-11-30ARM: Tegra: Make T20's MACH_* depend on ARCH_TEGRA_2x_SOCStephen Warren
2011-11-30ARM: tegra: Cardhu/Ventana only select ..._TEGRA_WM8903 if SND_SOCDan Willemsen
2011-11-30ARM: Tegra: ALSA support for CardhuStephen Warren
2011-11-30ARM: tegra: Limit ahb.c to Tegra2Dan Willemsen
2011-11-30ARM: tegra: power: cluster control requires CONFIG_PM_SLEEPScott Williams
2011-11-30ARM: tegra: power: Add debug checks for LP2 entry/exitScott Williams
2011-11-30ARM: tegra: power: Clean up stack pointer handlingScott Williams
2011-11-30ARM: tegra: power: Fix Tegra2 LP2 modeScott Williams
2011-11-30ARM: tegra: Handle uniprocessor all CPUs booted statusScott Williams
2011-11-30ARM: tegra: Fix uniprocessor reset handler initializationScott Williams
2011-11-30ARM: tegra: power: CPU complex must be suspended on CPU0Scott Williams
2011-11-30ARM: tegra: power: Add LP2 in idle support for secondary CPUsScott Williams
2011-11-30ARM: tegra: power: Split CPU context save and coherency exitScott Williams
2011-11-30ARM: tegra: power: Calculate address of IRAM LP2 mask onceScott Williams
2011-11-30ARM: tegra: timer: Save TWD registers on secondary CPU LP2Scott Williams
2011-11-30ARM: tegra: power: Save TWD registers on cluster transitionsScott Williams
2011-11-30ARM: tegra: power: Add TWD context save/restoreScott Williams
2011-11-30ARM: tegra3: power: Add LP2 power mode support for CPU 0Scott Williams
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