Age | Commit message (Collapse) | Author |
|
Add MIPI DCS short write (1 parameter) support.
The cmds sent with this new function will be sent every frame by hardware
Bug 884157
Reviewed-on: http://git-master/r/58180
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
(cherry picked from commit df4679db62b164e33e82fe56a18787cfca431d82)
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
[jmayo@nvidia.com: cleaned up formatting]
Change-Id: Ia2b54c070c91bbb4ba59741c0c5c23dae8f71ce8
Reviewed-on: http://git-master/r/63413
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
Rebase-Id: R965eb64babd304bd66f2c057721a9dd1eedb17ca
|
|
Registering the ricoh583 pmu driver.
Change-Id: I3547522d661852826185e50b6958234a04ca0b4b
Reviewed-on: http://git-master/r/62948
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
Rebase-Id: R458057614dd9db4aeb34d37de20c6753e78b3e51
|
|
Enabling the onkey for pm299 based system. This
will be used to wakeup/suspend the system.
Reviewed-on: http://git-master/r/61901
(cherry picked from commit e86410259e234d0c6ab9acdab7ab0e0fa36309ca)
Change-Id: I48c1e8ad44fa1a991b357e924baf9e0b3ba74563
Reviewed-on: http://git-master/r/62914
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
Rebase-Id: R075c1d69a70af7d4b90a61315ed1b025528fce61
|
|
Setting the slewrise and slewfall rates properly.
Bug 811303
Reviewed-on: http://git-master/r/52367
(cherry picked from commit 337b90b5a359c4f320f58f5026fa511dca5d8031)
Change-Id: I518b4dcdad8ac338cf03d4fb6c634b0747a82836
Reviewed-on: http://git-master/r/62326
(cherry picked from commit 7a04424fb0b8c1f36f28c99f73a313cd192360e9)
Reviewed-on: http://git-master/r/63813
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Rebase-Id: Racfd777be42f83018a9e295e1c7048ebb02f7f9e
|
|
These changes have no effect if CONFIG_GCOV_KERNEL is not set in
defconfig. It is easier to trigger GCOV for kernel if this patch
is in by only setting the before mentioned flag.
Change-Id: I8aade309da2da62c4b3889bd84e4123ba8f182da
Signed-off-by: Juha Tukkinen <jtukkinen@nvidia.com>
Reviewed-on: http://git-master/r/62999
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Rebase-Id: R4c238f707f1db600f188ae83426336753992b7be
|
|
Based on work by George G. Davis <gdavis@mvista.com>.
See http://lwn.net/Articles/390419/
Change-Id: I8df700d20a154e179f8cf6cdfe4015efc5d384f2
Signed-off-by: Juha Tukkinen <jtukkinen@nvidia.com>
Reviewed-on: http://git-master/r/62998
Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Rebase-Id: R2607a46c8bd1e521abe44a57a5ccf7317333d6c9
|
|
Perform sync point interrupt registration only when CONFIG_TEGRA_GRHOST
is enabled.
Reviewed-on: http://git-master/r/62719
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
(cherry picked from commit 0f1a8ad77749a1abee7893b7a1a8829a95a4711f)
Change-Id: I8749abc918247f4bda0332c02908741caeb08608
Reviewed-on: http://git-master/r/63415
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R94f39f55f13637998ea41456621b67adc506130a
|
|
Update Tegra3 CPU clock rate after G=>LP mode switch is completed to
synchronize with cpufreq target rate.
(cherry picked from commit 870d21e5e23eff476cdd841b4ce2605393d638ef)
(cherry picked from commit 11b20d7d6206c557f00e3f7a40dec1d498345d79)
Change-Id: I62237b8d34be23a8d903937f2ebb2d395c5db1b9
Reviewed-on: http://git-master/r/63359
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Rdd1548389896521fddb2e239d6236706eb102f73
|
|
Bug 841336
(cherry picked from commit b4cd14d5b9d1b2011a7752b6c52b3b64eb227cdb)
(cherry picked from commit 24cefb5d699db0a53b9fb3dd7cbe41de93c44e8e)
Change-Id: I080b04577697f31d9f9d4e96213630a28844a7db
Reviewed-on: http://git-master/r/63358
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R332edca05c942d8698353eb6817ad1acf0a5f8bf
|
|
Optimized Tegra3 VDD_CPU control when VDD_CPU target is set to zero,
which could happen only while CPU is in LP mode (and CPU regulator
output is turned off by side-band signal, anyway):
- Ignore VDD_CPU dependency on VDD_CORE while VDD_CPU target is zero
- Allow VDD_CPU one step change to zero (i.e., to minimum voltage set
by constraints) after entry to LP mode
- Allow VDD_CPU one step change to the predicted G mode target before
exit from LP mode
(cherry picked from commit 5826f3e28867207b5dad1c50795de8275d1af872)
(cherry picked from commit 79c531421dfc65e27af657fd12b64c4187c67827)
Change-Id: I3c469132034a431d2e9b8727d11d604c306122f1
Reviewed-on: http://git-master/r/63357
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R4c4f6e79decddb778f58cb5eef853a4c9d52ca94
|
|
Added dynamic self-refresh (DSR) field to Tegra3 EMC DFS table. This
field will be supported starting with table revision to 3.2, and it
will allow to enable/disable DSR for each table entry independently.
Bug 853990
(cherry picked from commit 6e225af7334d789ffac72542602913a0028d5eac)
(cherry picked from commit c7ebe73da695206a992088a4ba5a6cd7643ea333)
Change-Id: I212d5992067baffaaf5b2e1de25b103c7b1fb56a
Reviewed-on: http://git-master/r/63356
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R7261d49b023634a783ab2bd55f494112d0bac2a1
|
|
Bug 841336
Reviewed-on: http://git-master/r/60546
(cherry picked from commit accf2b0e8cb96ac1cd9ea620081004c36673d761)
Change-Id: I07615da1f4bae5ebad75e46286701aaecba8b7f8
Reviewed-on: http://git-master/r/62774
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Rf596b18fe295288ab4a392559b64fb1f5cc35e23
|
|
Earlier value of 75 had unnecessary double guardbanding.
Changed 90C row in EDP table down to 85C to get throttling alert.
Bug 862301
Reviewed-on: http://git-master/r/50544
(cherry picked from commit 9f2693a80274bcd9eb8e7424bca87f34cc190741)
Change-Id: If7204150013e7894fc310a2f7e8fd46baf11d869
Reviewed-on: http://git-master/r/62773
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R6ef35feeaad04bea897d9343d9d3a21a988f3dde
|
|
Bug 860231
Reviewed-on: http://git-master/r/46599
(cherry picked from commit 3a85d02f0d61f8d94b864716ce7f3f12e78d62a0)
Change-Id: I73d61b766bfa885ebcacbe9f2facd8fc64635903
Reviewed-on: http://git-master/r/62771
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R08596750b3d68357c435f690fb08c884d4da8650
|
|
Bug 844025
Reviewed-on: http://git-master/r/51443
(cherry picked from commit 1abdcb266a1fa22fd766549d5eddcca92e1fb17e)
Change-Id: Ie9b405482eebf40923f8de20c897f20bebdb84ba
Reviewed-on: http://git-master/r/61681
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R73990d76e2030664cb7cc6b6c7c36052f4c64bdb
|
|
The scan timeout of the continuous mode can be calculated based on
init delay, repeat delay, debounce count and number of active row.
It also depends on how many scan need to be done before kbc change
the mode from continuous to wakeup mode.
Providing mechanism to select the scan count from platform data
and calculating the scan timeout count based on above parameters.
bug 876712
Reviewed-on: http://git-master/r/62591
(cherry picked from commit 3360ed5be86a2afd6716bc5227cc39657efd35b2)
Change-Id: Ib9dc96b1cc201b7af0bd62a3ec7fe9a80791d796
Reviewed-on: http://git-master/r/63229
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Rebase-Id: Rbcb685d34c5d00ebf1c79d356eb63e4584075447
|
|
Setting the number of scans to 30 by keyboard controller after
pressed key released.
Also setting repeat delay time to 1 clock.
bug 876712
Reviewed-on: http://git-master/r/62592
(cherry picked from commit 9afabbf3d72135346b02c9a2cf48e4793fb90d43)
Change-Id: Idec353b68fba82676655125acd7f3d78ff4d0d08
Reviewed-on: http://git-master/r/63198
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Rebase-Id: R20feaf7cd291cd2b404effad4c029dca1a21c57c
|
|
1) configuring pinmux
2) create pn544_i2c_platform_data
3) register i2c device info using i2c_register_board_info
Bug 846684
Bug 873017
Change-Id: I6cc370d3ee6cc5df6b75db19bb719275e465f344
Reviewed-on: http://git-master/r/62746
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R334a9cc8f86c90214b2415b3b855d5f234ad7a11
|
|
Disabling usb3 as it is not used on enterprise.
Bug 885298
Reviewed-on: http://git-master/r/57201
(cherry picked from commit a74f09883bd09355e1b4e8c322dff279f8505b5b)
Change-Id: I77c00284ea8dd96a39aa267a0a6784cb8caf3a7a
Reviewed-on: http://git-master/r/63257
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
Rebase-Id: R8f0f9a693ec579e50658e97e4198c6b243455903
|
|
The ramp voltage for the ldo3 for PM269 is around 1mV/us.
Setting this value.
bug 872382
Reviewed-on: http://git-master/r/51364
(cherry picked from commit aa84b06982dbea58b815fc99bbbf84c7bdaddc78)
Change-Id: I2b7cd8883c06250490c3e27dd28384985706aa68
Reviewed-on: http://git-master/r/62341
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
Rebase-Id: R74b6d629197cc9b1cc591a4ac318f7105c7f28c5
|
|
Registering gpadc driver through tps80031.
bug 872697
Reviewed-on: http://git-master/r/56986
(cherry picked from commit 95f9948f31f1ce0862821830bb348cbe027cfcaf)
Change-Id: I07942d3aac247b12e0e0cb344ed292bbae4caf78
Reviewed-on: http://git-master/r/61859
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
Rebase-Id: R5871b51c9f335e6b1843c40c6882e24642813a28
|
|
OTG host register/unregister functions were duplicated identically
across all board files, making the code difficult to maintain (and
actually some boards did not get all some code fixes leading to the same
bug being met again and again). This patch moves this common code into
tegra-otg.c.
Bug 884315
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Change-Id: I99b118664f0481f6c5470411b43f36609e0feb52
Reviewed-on: http://git-master/r/61763
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
Rebase-Id: R0f6060514c017946cc9ae2ba2f04a1c134d14d9b
|
|
Removing the old/deprecated spi slave driver.
Change-Id: Ie9b05d03dfe183dd1f4c926d55d746ebcb2b0f6d
Reviewed-on: http://git-master/r/62979
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Rebase-Id: R7934a311a878811232d798f7d8d59f7561e4a5c8
|
|
Camera I2C wasn't registered in A00 board. Add support for this.
Bug 894201
Reviewed-on: http://git-master/r/60567
(cherry picked from commit 1122e0e92bf1cc8df7f9d5e3091c96e012529b54)
Reviewed-on: http://git-master/r/62213
(cherry picked from commit 44bb5880800e1d29c346d063c4aba649370f4cfa)
Change-Id: I65196666e40d5a827ceb36e808a0535279d4ce46
Reviewed-on: http://git-master/r/62777
Reviewed-by: Jihoon Bang <jbang@nvidia.com>
Tested-by: Jihoon Bang <jbang@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R5bb1541b409bce616994e4636b0f2f8be8b7ee39
|
|
Enable Virtual Terminal for AP20 and T30.
Bug: 898297
Change-Id: I1c69a620ecdbf5901b101b542bdcd0dff25f94f1
Signed-off-by: Preetham Chandru <pchandru@nvidia.com>
Reviewed-on: http://git-master/r/62715
Reviewed-by: Mursalin Akon <makon@nvidia.com>
Reviewed-by: Allen Martin <amartin@nvidia.com>
Rebase-Id: R6bbe63c09f4ca4e920dc69eea1efdb12ba78a449
|
|
Restore FCR while resuming debug uart, to enable RX and TX FIFOs with
trigger levels configured during initialisation of debug uart port.
Bug 867063
Change-Id: I9665ff29a53c3e2e6c78a3037e20e7362a642f77
Reviewed-on: http://git-master/r/62411
Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Rebase-Id: Ra3b9858456b952ab539a36019a55863077094054
|
|
Remove unused SDHCI controller registration to suppress bootup
warn-on messages.
bug 896928
Change-Id: I027d9a3e9b56c2ca37449d4a1835a904f584dd88
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/62156
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: R7cfeccf2ccf998f5c994e5732e4839cdfa52034a
|
|
PL310 virtual address was calculated using PPSB virtual/phy address.
It should be done using CPU virtual/phy address. This causes
TEGRA_PL310_VIRT value to get overlapped with virtual kerenl memory map's
Vmalloc region on whistler.
Bug 881831
Bug 867094
Change-Id: Ifaeeb9291553af59453f0041ad7cb1fe9d27979b
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/62097
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Rebase-Id: Ra5a6165c8a02f0ac130bbaac4a477b901ceea62f
|
|
Change-Id: Ie730ad7ec74927ef63722f4038db00e5f5d31154
Signed-off-by: Colin Patrick McCabe <cmccabe@nvidia.com>
Reviewed-on: http://git-master/r/60558
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Rebase-Id: Rad06124e61bdf95cb0307dd2204f2bf4bb92e718
|
|
This patch adds tegra_p852_gnu_linux_defconfig as defconfig
for p852 platform.
bug 872849
Reviewed-on: http://git-master/r/46384
(cherry picked from commit a4faef82941ab6fa7465f60ee7f4830c91a3aa38)
Change-Id: Ib01ca8ad25377407bac44ea8cc68307402dd56c1
Reviewed-on: http://git-master/r/56899
Tested-by: Manoj Chourasia <mchourasia@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Rebase-Id: Rc19c4c253a9a642a8a38870156bf1abb660ad172
|
|
Registered number of p852 platform on arm-linux
forum is 3667.
This patch adds p852 machine number to mach-types
bug 872849
Reviewed-on: http://git-master/r/46385
(cherry picked from commit 418b55a780649ce355bd0f8c2a423b11b10c110f)
Change-Id: I6c62e6c69bffbf634ca17e418a197b01df137a85
Reviewed-on: http://git-master/r/56896
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Manoj Chourasia <mchourasia@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Rebase-Id: R3c7e29f06d1f60cfaeae44d4c8fd40046cc9e1d6
|
|
The transciever settings were set for every suspend/resume of the device.
The transciever settings should be set only once that is during the phyopen.
Bug 889140
Reviewed-on: http://git-master/r/62336
(cherry picked from commit 6eb5f6192adf8ee996ba51b3d20bc26d1d9e9640)
Change-Id: Id32299f4d72c195a8bf4814cefd2085ddc3ef7d8
Reviewed-on: http://git-master/r/63011
Reviewed-by: Suresh Mangipudi <smangipudi@nvidia.com>
Tested-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
Rebase-Id: R51d06ec9171a2a90da92037a89b873359e8f950d
|
|
Change the trigger for the wake events. The WAKE_ON_CONNECT bit should not
be cleared until the PCD_STS bit is set.
Bug 881388
Reviewed-on: http://git-master/r/62335
(cherry picked from commit 0b2d13a0e7dfe5218082b799599fa815ad9c9334)
Change-Id: I0d02f939ea5ba205765771242787f328c92092d5
Reviewed-on: http://git-master/r/63010
Reviewed-by: Suresh Mangipudi <smangipudi@nvidia.com>
Tested-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
Rebase-Id: R3673afb4fc4357f4b72cd9af8c561902f223fbc5
|
|
sdmmc3 and sdmmc4 clocks need not be enabled by default.
Change-Id: I8b691ae6d906fd487e31e1fe5b764a37546e1eb5
Reviewed-on: http://git-master/r/62972
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Rebase-Id: R7bfb79ecf4857c99e0a801411a4b0fd3a489e47a
|
|
This is to keep consistency with tegra* files all of which use
underscores instead of dashes
Reviewed-on: http://git-master/r/55582
(cherry picked from commit 401f0018a27a18aafb9eac7d0bed6990c99c73cc)
Change-Id: I1a7066e6ac86f5876126ae54cee84f64fbc509f1
Reviewed-on: http://git-master/r/62251
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Rd08530c8b72d63d3ed1c8557f1c47f481ed49044
|
|
When core rail is disabled it is set to nominal voltage underneath
clock framework. On Tegra3 DDR3 platforms low EMC rates are not safe
at high voltage that exceeds EMC bridge minimum level. Enable EMC
bridge explicitly in this case to set safe floor for EMC. Similarly
need to enable EMC bridge when CPU rail is disabled and pushing core
voltage (cpu-to-core voltage dependency) over bridge minimum level.
(cherry picked from commit bff814b2e46e67defde178b72bd379003b5429c2)
(cherry picked from commit e5567cb8dafcbd30797237e7bb91d77ce57de66a)
Change-Id: Ibb8dad5132f69e3325d793658b3dcc8b887974bf
Reviewed-on: http://git-master/r/62031
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Rebase-Id: R56f360c3b1ee25bf2dae4b886399b83e357f0225
|
|
When dvfs is suspended core rail is set to nominal voltage underneath
clock framework. On Tegra3 DDR3 platforms low EMC rates are not safe
at high voltage that exceeds EMC bridge minimum level. Enabling EMC
bridge during suspend for Tegra3 DDR3 platforms guarantees safe EMC
operations at high voltage.
(cherry picked from commit 677c01d3d9edaf7e91f09de5025e7864b6a288d8)
(cherry picked from commit 75710c173caa46f2e3cd24e48cc82f030cdb52d9)
Change-Id: I1e300c18867295b1394184da39eeffcab43de4c7
Reviewed-on: http://git-master/r/62030
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Rebase-Id: R2a3a91b370d2517e89e1d30f27f9fd41a9a81267
|
|
- Moved initialization of Tegra3 dram configuration variables from
EMC DVFS setup to EMC clock initialization, so that these variables
can be used independently of DVFS.
- Added graceful exit from EMC DVFS setup in case of empty DVFS table
- Applied EMC minimum rate to direct EMC clock round rate operations
(currently applied only to shared EMC bus update).
(cherry picked from commit c6b3f6e0eb0b6e3485d02fc5306a1c09cbacf914)
(cherry picked from commit cbf09d55bb9fa9c9ade7bb472859b4808f47b615)
Change-Id: I84bbdc05ff7a0670ec9d088b98a9df25683db4df
Reviewed-on: http://git-master/r/62029
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R0fb03ff9903aa51aa922b4a49eed96aad0e97a06
|
|
Update cpu nominal voltage selection to accommodate irregular voltage
steps in cpu dvfs table (instead of constant 25mV step assumed so far).
(cherry picked from commit 3bdc83bebf4ef74c760d075a8ae8ffe6baf8b15a)
(cherry picked from commit e2301c1d8e868d4658f768cfacc631c0f78c185b)
Change-Id: Ief9298608dd524d7cc7ff4057fc1cffc180e7c82
Reviewed-on: http://git-master/r/62028
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Rebase-Id: R91e4948134b5b385dff77c6b8f610ab80cf91c6a
|
|
- Removed xio and twc clock descriptors (no such clocks on Tegra3)
- Updated 1.7GHz cpu frequency table (for T33), and added 1.5GHz
table (for AP33)
- Updated emc bridge related comments
(cherry picked from commit 5749bd88bad0eb23cfc2d4fc721ae30ff5b9f5e0)
(cherry picked from commit 06312525cb8021b73cd65993ff7e400e4fa9314d)
Change-Id: Ia1502bf85e0e5121d0e536b56277659710c70d87
Reviewed-on: http://git-master/r/62027
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Rebase-Id: R4cde93c9ec39b7c1787235ddf99743b4874fb394
|
|
Removed 750mV and 775mV steps from Tegra3 CPU voltage ladder
(way below VDD_CPU min 850mV), and added 1200mV step needed
for future AP33 DVFS support.
Bug 841336
(cherry picked from commit 67191a68a25b32299520673e8cdfa4e166c152d0)
(cherry picked from commit 7e3cf6cc679afe6828cba64b3e1482585301841a)
Change-Id: I3ca97126662204cb0f65ec808609c8135408d7ed
Reviewed-on: http://git-master/r/62026
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Rebase-Id: R321ee8f89da66d2178f98cf4f86e83c9dcc3191b
|
|
Change-Id: I04155e54a1aaea950921990c31c3a7a3a45ccaf1
Reviewed-on: http://git-master/r/62017
Tested-by: Gerrit_Virtual_Submit
Tested-by: Jeff Smith <jsmith@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: Rd7f272d471e109faf9e82cfa039aed22d2f7b801
|
|
Configuring the LDO4, LDO7 and LDO8 in low power mode in suspend.
bug 890770
Reviewed-on: http://git-master/r/60411
(cherry picked from commit 5c65acbba9526f66679ed6934e008c4205c7fd88)
Change-Id: I519e99ba02eac08fc93b69422fd129eea85eec3a
Reviewed-on: http://git-master/r/61439
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Rebase-Id: Rd5f3000c7845e3967b542268feaeeff169ad7498
|
|
Set pin configuration information for required rows and columns.
Enable only required ROW and COL gpio.
bug 889620
Change-Id: Ia9794d6a1af13dd9148ddac81378e961f6ae35f4
Reviewed-on: http://git-master/r/59618
Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
Tested-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: Re56f1d9384993f544d0bfbbf0e8a457cee0c4913
|
|
Set pin configuration information for required rows and columns.
Enable only required ROW and COL gpio.
bug 889620
Change-Id: I4965fc8db89ccc79c12e4295b9afdef635e6c909
Reviewed-on: http://git-master/r/59155
Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
Tested-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: Rd658f960ea9f0b4e79bc99b0c4f159f030f65320
|
|
-Set only REQUIRED row and column configuration register to
PROPER values to avoid continuously generating KBC input events.
-Use *enable* field in pin_cfg, to check GPIO_x_ROW_EN register
should be set or clear.
bug 889620
Change-Id: I91990156c300605c214e7e393edf14fbced1573d
Reviewed-on: http://git-master/r/59153
Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
Tested-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: R03e9deb839fc21c1ea66fc81ae6601155b8e8d4d
|
|
If kernel command line option have the power_supply as battery
then enable the battery charging functionality.
Reviewed-on: http://git-master/r/50673
(cherry picked from commit 4f36edabc585f3fea28e2f959558ac7e07dd2b5e)
Change-Id: I5a12105503f29e4e58991bcf4c020c709a97a7cd
Reviewed-on: http://git-master/r/56994
Reviewed-by: Syed Rafiuddin <srafiuddin@nvidia.com>
Tested-by: Syed Rafiuddin <srafiuddin@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Rebase-Id: R9fa09e3c265fabefd14804def31100259bfd9730
|
|
Enable i2s3 and bluetooth dit device for cardhu. Also add i2s2 clock in
clock table. It is needed to support BT SCO playback/record.
Bug 872652
Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com>
Change-Id: I3b702bbbd360db966447b099e982891383db27cd
Reviewed-on: http://git-master/r/62049
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R035bff07f147e9100956df6c238bf7df60d89e93
|
|
pll_m initialized to 0 so that it stays at the frequency configured
by BCT.
For AP25 pll_m runs at 760MHz. Peripherals connected to pll_m and
running at frequency not multiple of 760MHz switched to pll_c.
Bug 892505
Change-Id: Ie6abb47c4fac6d808aab5ed13a6b049c42126588
Reviewed-on: http://git-master/r/61491
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: Rcbbad7a6d277b7800e8e75962b96d533148fe1eb
|
|
Create mapping from gpio to pingroup and set gpio to
normal or tristate
Bug 866633
Reviewed-on: http://git-master/r/56557
(cherry picked from commit 321ded98d41170b9e32d60177c6808492ccdf115)
Change-Id: I3d1b979717f1c6b208af3df0a7dfe603e5272d21
Reviewed-on: http://git-master/r/61120
Tested-by: Bandi Krishna Chaitanya <bandik@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Rebase-Id: R5991c2cbc11aa35345fde7f08c0bfeb306e85e1e
|