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2011-11-30ARM: tegra: power: Refactored kernel powergate codeKaran Jhavar
This change provides a centralized location for powergating modules. It would take care of switching on/off clocks while un-powergating/ powergating modules respectively. Bug: 814267 Original-Change-Id: Ic80dc517f634c29085c8e089bdaa32c6fd742710 Reviewed-on: http://git-master/r/31776 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: Rc0aac0edd4e693c15d22d998c882fceeeb85765d
2011-11-30tegra: power: correct LP0 sequenceJay Cheng
Change-Id: I5f548f11059039cbd830be483ecfa0c6671002e7 Reviewed-on: http://git-master/r/47365 Tested-by: Cho-Che Cheng <jacheng@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rd7ef967c8b40295a04a0447eb8bbc8e2d577a48e
2011-11-30tegra: power: add wakeup_key methodJay Cheng
connect wakeup_key method to KEY_POWER (TEGRA_WAKE_GPIO_PV2) Change-Id: I13b8f503399989bb06e97343711ed9e7348839ac Reviewed-on: http://git-master/r/47364 Tested-by: Cho-Che Cheng <jacheng@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rffb10919b9cfa49c975f37d12646a34aeee44375
2011-11-30ARM: tegra: power: setup TTB0 for cacheable memoryJin Qian
Bug 862494 Change-Id: Ib7875ded150b3e9dc288a9ed90f6ded0a37014a3 Reviewed-on: http://git-master/r/47246 Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: R11be58a9cf3a46fadf985e209e26dc00a8d87c58
2011-11-30ARM: tegra2: power: fix LP2 statistics reportingJin Qian
Bug 863108 Change-Id: I5cc4e3ba58daeaeb527871026c85bdca5f6362f2 Reviewed-on: http://git-master/r/47232 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: R843a5cf74874bad3999bc55caa0eb8cad04cc555
2011-11-30ARM: tegra: Fix build error when CONFIG_SMP is not selectedScott Williams
Change-Id: I2420730290c7ecb407e6f30c8a6159ceadfabbbe Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/47589 Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rb177b1e8ed9ce89c732319f49525588c5c0dd9d0
2011-11-30ARM: tegra: Delete obsolete tegra_audio_device declarationScott Williams
Change-Id: I119fdbbc2440f8a7e64e2f3b5cec2ae4b182ee36 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/47592 Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: R891ed7225b634dc01aaf3f13dbe79fc1eae1c27c
2011-11-30ARM: tegra: Delete references to obsolete tegra_audio_deviceScott Williams
Change-Id: Id234e2d264d70c2244f4040d74f43b5478043904 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/47591 Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: Re8ab569df562b66ffa14e589775968238fc4c338
2011-11-30ARM: tegra: Fix build error when CONFIG_PM_SLEEP is not selectedScott Williams
Change-Id: I65e18395eef3a36f6dd537d64d98ab970f166460 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/47590 Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: R2643d7665780442e71444999f21d96a508c7a062
2011-11-30ARM: tegra: workqueue: Unify spelling of 'freeze'+'able' to 'freezable'Gaurav Sarode
In K39 , 'freezeable' is changed to 'freezable'. Reference Commit Id 58a69cb47ec6991bf006a3e5d202e8571b0327a4. Change-Id: Ie3f95db453205c05da4cf4e655ba8b12a126255b Reviewed-on: http://git-master/r/47487 Tested-by: Gaurav Sarode <gsarode@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: R530643b91e8c252eb606ce7e789cfe34101f6edd
2011-11-30arm: tegra: Use new platform typesYudong Tan
This change is needed to support three different platforms, silicon, fpga and simulation. Change-Id: I407853e1d86accbe3686deb4f34571fe6b10bcce Reviewed-on: http://git-master/r/36351 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rc4b424f1a55ffb71245f3a8330559258124e2a19
2011-11-30arm: tegra: Add platform types for TegraYudong Tan
Change-Id: Ib9ef42efcbc24d1424a1b43e7d4ad46b97255aaa Reviewed-on: http://git-master/r/36350 Reviewed-by: Yudong Tan <ytan@nvidia.com> Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R99f25c1b92fe4a9322d83e00c9560fc7ada2b641
2011-11-30ARM: config: tegra3: Enable TPS80031, gpio regDan Willemsen
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R0a2fb354b3b79058ef435577d44f11d595fe46c3
2011-11-30arm: tegra: cardhu: correct rail_names in ina219_platform_dataPritesh Raithatha
Bug 844743 Original-Change-Id: I7538342b2a267540ee14ddd70e10d0d71618d46e Reviewed-on: http://git-master/r/39527 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Pritesh Raithatha <praithatha@nvidia.com> Tested-by: Pritesh Raithatha <praithatha@nvidia.com> Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com> Rebase-Id: Rc4967909a7a47860073144c11f69b73453e1e897
2011-11-30arm: tegra: pm269: Low power mode to unused vddio-gmi pinsLaxman Dewangan
Putting the unused vddio_gmi pins into the low power mode. bug 833087 Original-Change-Id: I7595d011a61d5993fee167e89ed7eb204d5cb6b6 Reviewed-on: http://git-master/r/37877 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Matthew Longnecker <mlongnecker@nvidia.com> Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Rebase-Id: R3fa74a5ebc7720b95f91f8da7b665e634522f210
2011-11-30ARM: tegra: clock: Change default sampling period to 12msTom Cherry
Bug 845349 Original-Change-Id: I0ce1a5da9a80cea6a4e55bc92490e6ae8508e22f Reviewed-on: http://git-master/r/39704 Tested-by: Thomas Cherry <tcherry@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: Rfc2bfc89082778e43d15406b0b5e53bdf845f08e
2011-11-30ARM: tegra: power: Restore cpufreq governor targetAlex Frid
Restored cpufreq governor target frequency on exit from suspend. Otherwise, CPU would stay at frequency set underneath the governor by tegra driver on suspend entry. Original-Change-Id: Iad96c7771bf89b78cdeb3e8f4e2c40b36e845b57 Reviewed-on: http://git-master/r/38390 Reviewed-by: Alex Courbot <acourbot@nvidia.com> Tested-by: Alex Courbot <acourbot@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: R12135cc7f8f940eac1653432786826bf2affec16
2011-11-30ARM: tegra: cardhu: Add 408MHz node to EMC DFS tableAlex Frid
Bug 836260 Original-Change-Id: I4fb8e8eb3610676f89cb29ee0d10487c01200f95 Reviewed-on: http://git-master/r/39244 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R1edb58986433fd6cc95ddecf0ef38e8c41f81fed
2011-11-30ARM: tegra: clock: Add/convert Tegra3 shared bus usersAlex Frid
- Convert display users of emc shared bus from shared floor users to shared bandwidth users - Add shared ceiling user to each supported shared bus (cbus, sbus, emc) Bug 837005 Original-Change-Id: I526d06a7ddd6072ec8ac750c4ffbfb7aa1890ec8 Reviewed-on: http://git-master/r/39140 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Raaca80423e60ee4c37e16c993641c2a5062bfd69
2011-11-30ARM: tegra: clock: Expand Tegra3 shared bus modesAlex Frid
Implemented 3 different modes of combining rate requests from shared bus users : - SHARED_FLOOR: cumulative floor request is determined by maximum rate among all users in this mode and minimum bus rate - SHARED_BW: cumulative bandwidth request is determined by adding rates of all users in this mode together - SHRED_CEILING: cumulative ceiling request is determined by minimum rate among all users in this mode and maximum bus rate Final shared bus rate is determined as minimum rate between cumulative ceiling request and maximum of floor or bandwidth cumulative requests. Up to now shared bus clocks supported only SHARED_FLOOR mode, and this mode is kept as default mode for all users. Hence, no change in actual shared bus operations. Bug 837005 Original-Change-Id: I29f8215ba7bab4998fdd23b74c4f96611f5848fe Reviewed-on: http://git-master/r/39139 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Re9f9f87d58419a6756b7985c59743356c6a634bc
2011-11-30arm: tegra: usb_phy: pad power offSuresh Mangipudi
Turn off the pad power when hotplug support is not supported. Bug 829628 Original-Change-Id: Iea61ca9ac387f475e177a1c69a97f323ca37659e Reviewed-on: http://git-master/r/38696 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rf30be66234d431139f62480dda128ce6bda88bd9
2011-11-30ARM: tegra: dvfs: Set Tegra3 EMC max rate at 1.0V to 408MHzAlex Frid
Bug 836260 Original-Change-Id: I381619f6084a558f4c16142f8f0dfa3565ca2e94 Reviewed-on: http://git-master/r/39247 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Mandar Potdar <mpotdar@nvidia.com> Rebase-Id: R0d2d4bd478f526d116a741916de5c2fc2df7a998
2011-11-30ARM: tegra: enterprise: proper emc tableSachin Nikam
Updated SDRAM emc clock table for below freqs. 25.5 MHz, 51 MHz, 102 MHz, 400 MHz. Bug 832436 Original-Change-Id: I36e51172e98b20f8f099def3b72b503a68013a63 Signed-off-by: Sachin Nikam <snikam@nvidia.com> Reviewed-on: http://git-master/r/38056 Tested-by: Thomas Cherry <tcherry@nvidia.com> Reviewed-by: Thomas Cherry <tcherry@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: R86b8a379ea13d6d555aff62aafe744248d62094e
2011-11-30ARM: tegra: power: Update Tegra3 EMC DFS tableRay Poudrier
Add EMC table for LP-DDR2 Samsung memory Original-Change-Id: I931bbb0d2283ad94d130803cef7c08b6da5923a1 Reviewed-on: http://git-master/r/37757 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com> Tested-by: Raymond Poudrier <rapoudrier@nvidia.com> Tested-by: Gerrit_Virtual_Submit Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Karan Jhavar <kjhavar@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: Racdadadfeb4438faab94ca2bea4d9665da381d18
2011-11-30ARM: tegra: mcstats: Enable overall bandwidth measurement.Heechul Yun
Allow users to measure overall bandwidth of the system. Original-Change-Id: I5bb19609451a464c0a2335f05033cd9c87927a40 Reviewed-on: http://git-master/r/37687 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R57b747cb81514336fdc45a3eeff17d6d00e154b1
2011-11-30arm: tegra: Add sysfs entries for SMMU debuggingHiro Sugawara
CONFIG_TEGRA_SMMU_SYSFS enables /sys/devices/smmu/* entries to update various SMMU register contents from user's land. Default is "n" to allow only displaying the current values but not updating except SMMU TLB/PTC statistics enabling and disabling bits. Original-Change-Id: Icb4574c08d89006cb09da1d8d60c7ab40fefd1b1 Reviewed-on: http://git-master/r/37118 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R647d1f9a59edbbc8a60b7393cb0572a927bd6d32
2011-11-30ARM: tegra: dvfs: Update Tegra3 cpufreq table selectionAlex Frid
- For selection of cpufreq scaling table used top-most rate in G CPU dvfs table, instead of G CPU max rate. Commonly the above rates are the same, however, in case when PMU limitations on core voltage indirectly (VDD_CPU on VDD_CORE dependency) lower cpu max rate, the top-most dvfs rate should be used for table selection, and the max rate clipped to table entry. - Replaced BUGs in table selection implementation with errors. Thus, when no table is found cpufreq is not installed, but the system boots with respective error messages. - Step up suspend frequency index in cpufreq tables to reduce suspend entry latency (the selected rate is still low enough to work under Vmin voltage setting). Original-Change-Id: I45db19dbf5b48cef80db35663db2df3b68473993 Reviewed-on: http://git-master/r/37415 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R59fb213db14d868bec0ca701e1c73dd9d1918e82
2011-11-30ARM: tegra: Fixed the wrong 'if' statement.Jubeom Kim
Removed the semicolon after 'if'. (cherry picked from commit 9a118fd001bfbe23a7b825aa66cb19ebe7c12c7c) Original-Change-Id: I058d58f6bad2ec08cf5a509361dbc3fc52801ce1 Reviewed-on: http://git-master/r/38228 Tested-by: Jubeom Kim <jubeomk@nvidia.com> Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Rebase-Id: R1221658aa101f439a88df3cdae8a2d8c9c659cfb
2011-11-30arm: tegra3: pinmux: Adding SFIO3 mode for VI_MCLKHarry Hong
SFIO3 on VI_MCLK pin is needed to output vi_sensor clk. bug 839517 Original-Change-Id: Ied7408a8711b0256b8fe98eea67c873a7b168bcb Reviewed-on: http://git-master/r/37426 Tested-by: Harry Hong <hhong@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Matthew Longnecker <mlongnecker@nvidia.com> Rebase-Id: Ra0c9550efc2ff7af8075eaf7962be94f2d299c2b
2011-11-30arm: tegra: clock: clock fix for lp0Luke Huang
Since clock is required when resetting devices, always enable pllc and plla at the beginning of clock restore routine. The actual value will be restored back after reset. Original-Change-Id: Ic141ddb8cde5958d4e0f8b1154b8204a68c0ca50 Reviewed-on: http://git-master/r/38388 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R254cf377d4cde1863f560867fafc10b4f37a87c9
2011-11-30ARM: tegra: clock: Add shared bus users rate printoutAlex Frid
Original-Change-Id: Icb1a5028d575155427f1fd7fa5b3ee2a145934f4 Reviewed-on: http://git-master/r/38421 Tested-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Gerrit_Virtual_Submit Reviewed-by: Wen Yi <wyi@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Rebase-Id: Rf473061330e8b6d63948c9a0ed247e37e3534a52
2011-11-30ARM: tegra: power: trace C states and CPU mode switchesPeter De Schrijver
Original-Change-Id: I7915d356f18ac830c93b736463406b907d8c1cef Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-on: http://git-master/r/31958 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: R341f7619d11f81fd7dfbab2ceb1c6fdaab6ead78
2011-11-30ARM: tegra: power: Overlap Tegra3 cpu off delayAlex Frid
Overlap cpu off delay during G-to-LP mode switch with LP mode residency. Original-Change-Id: I8e93a5af3983e7daad46ae026fc510ce6c2fef99 Reviewed-on: http://git-master/r/31641 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Rebase-Id: R9260cc70b0fd5cf5266c7331a7b37d045f87fbfd
2011-11-30ARM: tegra: power: Use CPU LP mode for Tegra3 deep sleepAlex Frid
Original-Change-Id: If23b48fb414332f5dd25307a098569a5474283c6 Reviewed-on: http://git-master/r/31471 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R6ba9ce7c7b355da4148ce0ebc9bc357bf5fc0b13
2011-11-30ARM: tegra: power: Idle Tegra3 auto-hoplug on suspend entryAlex Frid
Original-Change-Id: I7f4fb6447c882a54d95ee3fb4c6149f4e0357d69 Reviewed-on: http://git-master/r/31457 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Gerrit_Virtual_Submit Rebase-Id: Rbe2ac5f11065109d34a04793f93c873441e261be
2011-11-30arm: tegra: usb_phy: update BIAS and XCVR registersRakesh Bodla
Modifing the UTMIP_BIAS_CFG0 and UTMIP_XCVR_CFG0 register settings to pass HS eye-diagram and receiver sensitivity tests. Bug 842700 Original-Change-Id: I4660fc3bd4d620408b52ed274232762fe50abee2 Reviewed-on: http://git-master/r/38510 Tested-by: Rakesh Bodla <rbodla@nvidia.com> Reviewed-by: Suresh Mangipudi <smangipudi@nvidia.com> Reviewed-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com> Tested-by: Gerrit_Virtual_Submit Rebase-Id: R3dec3d6e8699a6202482946ea49d0d98fe2cf48c
2011-11-30arm:tegra:tsensor: tsensor clock table updateBitan Biswas
tegra3 clock table updated with tsensor information Bug 661228 Original-Change-Id: I7ba9bd8f24f98e8108198e0ad0453d3a22648fe1 Reviewed-on: http://git-master/r/36120 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R9270c8323a5af2db19ebc400bbf6afb919388ee8
2011-11-30arm: tegra: enterprise: SMPS1 controlled by PREQ2 inputLaxman Dewangan
Configuring the regulator SMPS1 output such that output of regulator SMPS1 is controlled by the input peripheral power request signal PREQ2. bug 839809 bug 829405 Original-Change-Id: I352feb47444077af4a3da2d0a321feb1f3d8a9a0 Reviewed-on: http://git-master/r/39118 Tested-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Rebase-Id: Re0019fef9cc5789b184c2f5704e8a93abc56b5e5
2011-11-30arm: tegra: enterprise: Enabling vbus regulatorKasoju Mallikarjun
Enable vbus regulator for USB1 on Enterprise Bug 833736 Original-Change-Id: I2c1fdf829b55103b544c7319bac272f5a1912bc9 Reviewed-on: http://git-master/r/39154 Tested-by: Mallikarjun Kasoju <mkasoju@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Thomas Cherry <tcherry@nvidia.com> Rebase-Id: R8f67ea6b6a274529d7e0cdb5d56686fbce191081
2011-11-30arm: tegra: enterprise: Add VBUS regulator informationLaxman Dewangan
Adding VBUS regulator information to activate the VBUS. bug 833736 Original-Change-Id: I1cf4c2eb112a6ea26b74c3d1a2754019a47533fd Reviewed-on: http://git-master/r/38500 Tested-by: Mallikarjun Kasoju <mkasoju@nvidia.com> Reviewed-by: Thomas Cherry <tcherry@nvidia.com> Reviewed-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com> Rebase-Id: R1bf2e329910d76bde5f0897f1f84147d1db1952a
2011-11-30arm: tegra: pinmux: Handling unfitted RSVD pinmux option.Jin Park
When call tegra_pinmux_set_func with unfitted RSVD pinmux option, to prevent unexpected potential problem, handle to finding more preferred value. Bug 839423 Signed-off-by: Jin Park <jinyoungp@nvidia.com> Original-Change-Id: Idf8a1ece4317d14e94a69df0d1c8d450d7762c14 Reviewed-on: http://git-master/r/37185 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Mallikarjun Kasoju <mkasoju@nvidia.com> Rebase-Id: Rfb625aa025048c88c44fd96da1e8b0a3db8d013d
2011-11-30ARM: tegra: clock: Add Tegra3 AVP activity monitor supportAlex Frid
Added AVP clock control using Tegra3 activity monitoring device. The target AVP frequency floor is set based on average load and short term boost. Average AVP load time (time when AVP is not halted by flow controller) is determined by fixed frequency count provided by monitoring h/w featuring 1st order IIR activity filter. The boost frequency is calculated by s/w - exponentially increasing/ decreasing when sampled AVP activity has crossed upper/lower boost watermarks. The implementation is interrupt driven - periodic sampling is hidden by h/w. The tune-able debugfs parameters are: /sys/kernel/debug/tegra_actmon/avp/boost_step - boost rate increase step (% of max AVP frequency) /sys/kernel/debug/tegra_actmon/avp/boost_rate_inc - boost rate increase factor (%) /sys/kernel/debug/tegra_actmon/avp/boost_rate_dec - boost rate decrease factor (%) /sys/kernel/debug/tegra_actmon/avp/boost_threshold_up - upper activity watermark for boost increase (AVP active time in %) /sys/kernel/debug/tegra_actmon/avp/boost_threshold_dn - lower activity watermark for boost decrease (AVP active time in %) Original-Change-Id: Ia82247176531f2fb67acfc277e63b9f16916a488 Reviewed-on: http://git-master/r/37175 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: R995949fe30f188c16c3fa39e292a2ca56256f2a3
2011-11-30ARM: tegra: clock: Add Tegra3 EMC activity monitor supportAlex Frid
Added EMC clock control using Tegra3 activity monitoring device. The target EMC frequency floor is set based on average activity and short term boost. Average EMC activity is obtained directly from monitoring h/w featuring 1st order IIR activity filter. The boost frequency is calculated by s/w - exponentially increasing/ decreasing when sampled EMC activity has crossed upper/lower boost watermarks. The implementation is interrupt driven - periodic sampling is hidden by h/w. The tune-able debugfs parameters are: /sys/kernel/debug/tegra_actmon/emc/boost_step - boost rate increase step (% of max EMC frequency) /sys/kernel/debug/tegra_actmon/emc/boost_rate_inc - boost rate increase factor (%) /sys/kernel/debug/tegra_actmon/emc/boost_rate_dec - boost rate decrease factor (%) /sys/kernel/debug/tegra_actmon/emc/boost_threshold_up - upper activity watermark for boost increase (% of current EMC frequency) /sys/kernel/debug/tegra_actmon/emc/boost_threshold_dn - lower activity watermark for boost decrease (% of current EMC frequency) Original-Change-Id: I385c6e0a75da42dada792db6b4018b68fea8f23b Reviewed-on: http://git-master/r/36790 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: R0ac50b162b8e86237986885e115996f755b1e00a
2011-11-30tegra: dc: set EMC clock dynamicallyXin Xie
If the screen is idle (no POST for some time), reduce the DC EMC clock according the windows size. If external display connected, the EMC clock will not be reduced. BUG 828306 Original-Change-Id: I6fb62ce6baf3380737c76b71f16e38ad6465a667 Reviewed-on: http://git-master/r/37106 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: Re2b2c8b1a57c2a04b61c338b0b50e41d8c11ad65
2011-11-30tegra: dc: adding max pixclock check for hdmiDonghan Ryu
tegra_dc_hdmi_equal doesn't check pixclock and some devices doesn't support 148.5Mhz pixclock which is needed for 1080p@60. However, adding 1080p@30 to the supported hdmi mode array makes tegra_dc_hdmi_equal to retun 1080p@60. Therefore, this commit adds max pixclock check to distinguish modes with different pixclock Bug: 815409 Original-Change-Id: Ifbf07929e3c7a92172856518a55e9d4a04f0b943 Reviewed-on: http://git-master/r/32511 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: R5b3c53a840ea0855d4298d92ec8db696a0c2f40e
2011-11-30ARM: tegra: generate status events for all clocksPeter De Schrijver
Original-Change-Id: I55f52ab038764079811c68b3bb3738a9de17d7bf Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-on: http://git-master/r/31530 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: R25afcccf5ff8d7a88b705ce7f68ab83e818ae1e4
2011-11-30ARM: tegra: sysfs write permission for user onlySachin Nikam
Giving read-write permission for user only for sysfs attributes. Group and other will have only read permission. - tegra_mc_stats: enable and quantum - susend: mode - clock: rate, parent, state File System Permission CTS expects this to pass. Bug 840409 Original-Change-Id: I3335b27124be38f0f5ea4cc415fef6532e574680 Signed-off-by: Sachin Nikam <snikam@nvidia.com> Reviewed-on: http://git-master/r/36867 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: R3360698aa910479a0eccb460656d104912af99bb
2011-11-30arm: tegra: cardhu: handle regulator_get errorPrayas Mohanty
For sh532u, when regulator_get fails, it still returns unwanted value. Reset regulator variable to NULL and return error. bug 841078 Original-Change-Id: I7265b2b5ca40405c92555a242d7d39f5dfe2bb07 Reviewed-on: http://git-master/r/37848 Reviewed-by: Alok Chauhan <alokc@nvidia.com> Tested-by: Prayas Mohanty <pmohanty@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: R74efd1bf6a77b71f19a32058f55ba094e213648d
2011-11-30arm: tegra: cardhu: enable PMU features for lp0Luke Huang
Enable PMU only features for LP0. System-wise LP0 is not enable by default yet. 1. Allow pmu SLEEP state 2. Keep 32KHz clk out from PMU enabled on LP0 3. Set core_power_req to be high enable 4. Turn off VDD1 (power for Vcore) on LP0 Original-Change-Id: Id6babdfc36de1a597f8df5d2943ef048699013d4 Reviewed-on: http://git-master/r/32853 Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com> Tested-by: Chih-Lung Huang <lhuang@nvidia.com> Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: R1be5db70870d950a7ffe1361e60aad4156398172
2011-11-30video: tegra: dsi: Set dc and dsi clock for DSI burst mode.Kevin Huang
Original-Change-Id: Ia631f7bae013f378c36fe05c665ef178bef12a46 Reviewed-on: http://git-master/r/31904 Reviewed-by: Kevin Huang <kevinh@nvidia.com> Tested-by: Kevin Huang <kevinh@nvidia.com> Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Reviewed-by: Animesh Kishore <ankishore@nvidia.com> Rebase-Id: R5b5d821365fce376a19a5527c5a9ecc9d2bfbb14
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-02 19:16:00 +0000