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2012-07-10ENGR00216010-1: gpc: Add missing display_pup_req config after system resumesRobby Cai
There's only DISPLAY power down request setting before system suspends, but without the paired DISPLAY power up request setting after resume. This will cause ePxP/EPDC/SPDC module nonfunctional because the modules will be powered down once pdn_req is asserted but not powered up again. With this patch, ePxP/EPDC/SPDC survived (need reinitialize each, however) on resume. Signed-off-by: Robby Cai <R63905@freescale.com>
2012-07-10ENGR00216013-3 vpu: add VPU_IOC_PHYMEM_CHECK ioctl.Zhang Jiejing
Add VPU_IOC_PHYMEM_CHECK ioctl in header file. This IOCTL will check the phy memory address is valid or not. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
2012-07-10ENGR00216013-2 mx6: not call memblock_free after reserve memory.Zhang Jiejing
Remove call memblock_free after reserve memory with memblock_allocate(). The function of memblock_free is to remove the memory block from reserve list of memblock, it will totally lost the info about how much phy memory we have. Skipping call this can make the reserved memory be accountable in memblock With no side-effect. After doing this, we can know how much our phy memory is, then can add check in our driver like(vpu) to check the phy memory valid or not before vpu start use the address. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
2012-07-06ENGR00215884-2 MX6 SabreSD:Refine OV csi camera reset sequenceLiu Ying
This patch refines OV csi camera reset sequence according to OV's recommendation: reset --------------------|_____|---------------- ->| 1ms |<- pwdn ----------|_________________________|------ ->| 5ms |<- ->| 5ms |<- ->| 5ms |<- Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
2012-07-06ENGR00215884-1 MX6 SabreSD:Refine OV mipi camera reset sequenceLiu Ying
This patch refines OV mipi camera reset sequence according to OV's recommendation: reset --------------------|_____|---------------- ->| 1ms |<- pwdn ----------|_________________________|------ ->| 5ms |<- ->| 5ms |<- ->| 5ms |<- This change makes the OV mipi camera be at a correct status after reset, otherwise, the wrong status of OV mipi camera will reduce the ~2.78V analog camera power to ~2.3V, which causes random thin colorful lines on OV5642 CSI camera image as OV5642 CSI camera uses the same analog power. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
2012-07-05ENGR00215188-3 mx6sl:enable LDO bypass function on mx6sl_arm2Robin Gong
enable LDO bypass function on mx6sl_arm2 board as mx6q_sabresd board Signed-off-by: Robin Gong <B38343@freescale.com>
2012-07-05ENGR00215188-2 LDO bypass: disable LDO bypass before suspend and back in resumeRobin Gong
There is one SOC bug if use LDO bypass, VDDARM_CAP will take 2ms to raise up normal voltage when system resume back, longer than 40us before. Then it will cause cpu hang if resume back. Workaround: We can disable LDO bypass at the last minute of suspend and enable LDO bypass again as long as system resume back. Signed-off-by: Robin Gong <B38343@freescale.com>
2012-07-05ENGR00215188-1 PFUZE CPUFREQ: reconstruct LDO bypass functionRobin Gong
As before, raw I2C operation is added in suspend interface of cpufeq driver,so that we can raise up cpu frequency and voltage after I2C driver suspended.But the code is not platform independent if customer use another pmic whose I2C slave address is different with pfuze. Now, we rasie up cpu frequency and disable cpu frequency change in more earlier than before. If system begin to suspend flow, we will do this. Signed-off-by: Robin Gong <B38343@freescale.com>
2012-07-05ENGR00215668 [MX6]Only restore PU field value instead of whole reg valueAnson Huang
Only need to save and restore PU field register value instead of the whole CORE REG value to avoid changing SOC and ARM voltage. No need to increase BUS freq before CPU freq increase when system is in audio bus mode. Signed-off-by: Anson Huang <b20788@freescale.com>
2012-07-05ENGR00215491 [MX6]Need to increase BUS freq when CPU freq is increasedAnson Huang
When BUS freq is running at DLL off mode(24M or 50M), when CPU freq is increased, we need to increase BUS freq to 400M setpoint in order to achieve high performance when CPU is busy. Signed-off-by: Anson Huang <b20788@freescale.com>
2012-07-05ENGR00214810 [MX6]Fix bus freq 50M->528M change issueAnson Huang
50M -> 528M bus freq change will cause system hang, root cause is that we didn't set 50M as DLL off mode, it should be DLL off mode. And make sure bus, axi, ahb, ipg and ipg_perclk are at right freq during all setpoints. Can't disable PU LDO again if it is not enabled. Signed-off-by: Anson Huang <b20788@freescale.com>
2012-07-04ENGR00215740 Enable the Keypadb02247
1. enable the Keypad 2. change the F5 as POWER key Signed-off-by: b02247 <b02247@freescale.com> Signed-off-by: Jack Lee <jacklee@freescale.com>
2012-07-03ENGR00215542 mx6sl: enable usb tether in mx6sl.Zhang Jiejing
enabel mx6sl usb tether. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
2012-06-29ENGR00215195 MX6 PM:Add necessary info for waitmode to help debug system issueLin Fuzhen
Add debug message for wait mode to check it was enabled or not. it will easy to get the wait mode status from this info e.g, if wait mode is enabled, there are below info from console: wait mode is enabled for i.MX6 Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
2012-06-29ENGR00215041-3 MX6 SabreSD:Correct camera and audio mclk freqLiu Ying
This patch corrects camera mclk and audio mclk frequency to be 24MHz to align with 24MHz osc clock. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
2012-06-29ENGR00215041-2 MX6 SabreSD:Set clko parent to be clko2Liu Ying
On MX6 SabreSD board, gpio_0 is muxed to clko to be audio mclk and camera mclk. 24MHz osc clk is a stable clock source, which can meet the requirement of audio mclk and camera mclk. This patch sets clko parent clock to be clko2 clock so that camera mclk and audio mclk can source from osc clk. There are 2 benifits after applying this patch: 1) clko's original parent clock(pll4_audio_main_clk) can be gated off to save power or used by another module. 2) ov5640/ov5642 camera most settings can reach claimed 15fps or 30fps with no human eye recognizable video quality downgrade. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
2012-06-29ENGR00215041-1 MX6 clock:Support clko2 to be clko's parent clkLiu Ying
This patch supports clko2 clock to be clko's parent clock. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
2012-06-29Merge commit 'rel_imx_3.0.15_12.06.01_RC3' into imx_3.0.15_androidXinyu Chen
2012-06-28ENGR00214791-1 [MX6] Add baseAddress parameter for GPU resourceLarry Li
Add baseAddress parameter for GPU resource according to different SOC Signed-off-by: Larry Li <b20787@freescale.com>
2012-06-28ENGR00215165 android: config: support pptp,l2tp vpn function, enable magic keyZhang Jiejing
1. enable pptp,l2tp vpn function. - tested pptp - l2tp not tested. 2. enable magic key in android by default, usuful when debuging. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
2012-06-26ENGR00214899 mx6 sabresd: requires 400MHz DDR when WIFI workingXinyu Chen
Change the sdhc2 clock flag to require at least 400MHz DDR frequency when SDIO working. If the SDIO clock is not taking into count by busfreq, then when we going to low bus mode, the WIFI sdio driver will lost interrupt and cause WIFI failed to work. Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
2012-06-25ENGR00214765 [MX6]Fix resume fail when there is pending wakeup irqAnson Huang
r2 is broken by L2 clean function which is used in the flow of pending wakeup irq there before suspend, need to avoid using important register. Signed-off-by: Anson Huang <b20788@freescale.com>
2012-06-25ENGR00210654 - MSL : fix NFS boot fails issue in sometimeFugang Duan
- MX6 sololite cpu board NFS boot fails in sometimes, because MAC cannot get any packets while sending DHCP to require IP. The reproduce rate is 10%. - Lan8720 phy enter a unexpected status, and need software reset phy before transmition. - Do some below overnight tests after add the changes, no NFS boot issue found. 1. Kernel boot from MMC, rootfs mount from NFS. 2. Kernel boot from tftp, rootfs mount form NFS. Signed-off-by: Fugang Duan <B38611@freescale.com>
2012-06-25ENGR00214607 [MX6]Fix CPUFreq change flow issueAnson Huang
Previous flow when we change PLL1_SW_CLK from 400M PFD to PLL1_MAIN_CLK is as below: 1. move PLL1_SW_CLK from 400M PFD to PLL1_MAIN_CLK; 2. change PLL1_MAIN_CLK's freq if necessary; There is chance that the PLL1_MAIN_CLK freq is higher than what we want, then after step1, system may hang as we use low voltage to run high freq. The correct flow should be as below: 1. make sure PLL1_MAIN_CLK is enabled; 2. make sure pLL1_MAIN_CLK freq is what we want; 3. move PLL1_SW_CLK from 400M PFD to PLL1_MAIN_CLK. Signed-off-by: Anson Huang <b20788@freescale.com>
2012-06-25ENGR00214736 [MX6SL]: Enable BUSFREQ at bootNancy Chen
Busfreq should be enabled at boot by default on i.MX6SL. Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
2012-06-25ENGR00214735 [MX6SL]: Set conservative governor as default governor.Nancy Chen
Set conservative governor as default governor. Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
2012-06-21ENGR00214367-3 imx6 usb charger: disable imx6 usb charger defaultRong Dian
disable imx6 usb charger default Signed-off-by: Rong Dian <b38775@freescale.com>
2012-06-21ENGR00213944-02: mmc: sdhci: [MX6] support SD v3.0 memory cards.Ryan QIAN
- Add variable pad speed setting per SD clk freq. - Add SD3.0 support on SD1, SD2, and SD3. - Enhance drive strength on SD pad to improve its compatibility. - change the definition of pad speed changing interface - combine pad speed setting for different SD host controllers into one function. Signed-off-by: Ryan QIAN <b32804@freescale.com> Acked-by: Lily Zhang
2012-06-21Merge remote branch 'fsl-linux-sdk/imx_3.0.15' into imx_3.0.15_androidXinyu Chen
Conflicts: arch/arm/mach-mx6/devices-imx6q.h drivers/power/sabresd_battery.c
2012-06-21ENGR00214337 MX6: Enable AXI cache for VDOA/VPU/IPU and set IPU high priorityWayne Zou
set IPU AXI-id0 Qos=0xf(bypass) and AXI-id1 Qos=0x7, mx6q use AXI-id0 for IPU display channel, it should has highest priority(bypass), and AXI-id1 for other IPU channel, it has high priority. Also, clear OCRAM_CTL bits to disable OCRAM read/write pipeline control. Signed-off-by: Wayne Zou <b36644@freescale.com>
2012-06-20ENGR00212633 [MX6SL]: Add support for SoC power optimization in Idle modeNancy Chen
Add support for SoC power optimization in Idle mode (1st phase): 1. ARM @ 198MHz. VDDARM_CAP @ 0.85V 2. AHB @ 24MHz, DDR @ 25MHz 3. PU regulator disabled when system is in IDLE. Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com> Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-06-20ENGR00214319: CAAM: Remove CAAM configs from mx6s defconfigTerry Lv
As MX6SL has replaced CAAM with DCP+RNGB, CAAM configs need to be removed from mx6s defconfig. Signed-off-by: Terry Lv <r65388@freescale.com>
2012-06-20ENGR00213726: CAAM: Amend crypto API configuration for caam operationTerry Lv
Previous configuration suppressed a number of crypto API features that caused misleading results when using the CAAM driver through the tcrypt. Enabling the API tests eliminated this. Also, added in other common ciphers and modes that, if lacking, would cause confusion with tcrypt behavior. Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com> Signed-off-by: Terry Lv <r65388@freescale.com>
2012-06-19ENGR00214199 [MX6]Need to lower ipg_perclk to 6M before init GPTAnson Huang
As Arik TO1.0 GPT use ipg_perclk as clock source, we need to lower it to 6M before init GPT, or the clock source freq will be wrong if we lower the ipg_perclk after GPT time already init. Signed-off-by: Anson Huang <b20788@freescale.com>
2012-06-19ENGR00214081-2 PM: Enable MAX11081 for sabresd_6dqLin Fuzhen
Enable MAX11081 for reading battery voltage Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
2012-06-19ENGR00213903 [MX6]Improve periph parent change flowAnson Huang
When bus freq is changed, we need to update periph clk's parent, better to use clk_set_parent API instead of changing the parent directly. Signed-off-by: Anson Huang <b20788@freescale.com>
2012-06-18ENGR00213997: Fix Section Mismatch warningRobby Cai
Fix: WARNING: vmlinux.o(.data+0x8c28): Section mismatch in reference from the variable mx6_gpmi_nand_platform_data to the function .init.text:gpmi_nand_platform_init() The variable mx6_gpmi_nand_platform_data references the function __init gpmi_nand_platform_init() If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console Signed-off-by: Robby Cai <R63905@freescale.com>
2012-06-18ENGR00213751: imx6sl: Add ELAN touchscreen support on EINK-DC3 boardRobby Cai
Add ELAN capacitive TS support on EINK-DC3 stacked on MX6SL_ARM2 board - configure the iomux setting (need 4.7K Ohm pull up on 'touch_int_b') - configure the i2c slave addr - configure the GPIO setting for ELAN ce/int/rst - update the defconfig Signed-off-by: Robby Cai <R63905@freescale.com>
2012-06-18ENGR00213749: imx6sl: Add keypad support on EINK-DC3 boardRobby Cai
Add the support for keypad on EINK-DC3 board which is stacked on ARM2 board. - configure the iomux setting - add dummy kpp clock to fool imx_keypad driver - add platform device for keypad - add key mapping (4x4 array) used on EINK-DC3 - update the defconfig for keypad driver Signed-off-by: Robby Cai <R63905@freescale.com>
2012-06-18ENGR00213684 MX6DL: emmc: mx6dl needs more iomux strength to emmc.Zhang Jiejing
this patch add more iomux strength to mx6dl's emmc. otherwise, -110 error when access emmc will occures. current test show this patch can improve on this issue. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
2012-06-18ENGR00213684 MX6DL: emmc: mx6dl needs more iomux strength to emmc.Zhang Jiejing
this patch add more iomux strength to mx6dl's emmc. otherwise, -110 error when access emmc will occures. current test show this patch can improve on this issue. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
2012-06-18Merge remote branch 'fsl-linux-sdk/imx_3.0.15' into imx_3.0.15_androidXinyu Chen
2012-06-15ENGR00212720 [MX6]Adjust CPU 672M setpoint voltageAnson Huang
Previous voltage for 672M is 1.05V, normal test is OK, but if CPU is busy in background and do the CPUFreq change as well, always fail the stress test at 672M setpoint, after increase it to 1.1V, stress test is OK. Signed-off-by: Anson Huang <b20788@freescale.com>
2012-06-15ENGR00213170-1 [MX6SL] Add resource needed by GPULarry Li
Prepare resourec such as memory, interrupt, clock, regester address needed by GPU. Signed-off-by: Larry Li <b20787@freescale.com>
2012-06-14ENGR00213158-1 IPU: Add IPU oneshot interrupt modeWayne Zou
Add IPU oneshot interrupt mode: IPU_IRQF_ONESHOT. Interrupt is not reenabled after irq handler finished. Signed-off-by: Wayne Zou <b36644@freescale.com>
2012-06-14ENGR00212516 PM: Add battery supoort for sabresd 6dqLin Fuzhen
Add battery support for sabresd_6dq Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
2012-06-14ENGR00213170-1 [MX6SL] Add resource needed by GPULarry Li
Prepare resourec such as memory, interrupt, clock, regester address needed by GPU. Signed-off-by: Larry Li <b20787@freescale.com>
2012-06-14ENGR00180919 [MX6]Update clock tree if BUS freq is changedAnson Huang
As DDR freq change is by modifying CCM register directly, we need to update the clock tree as well, or the clock tree will be broken. Also, we need to make sure the clock rate counting is right. Signed-off-by: Anson Huang <b20788@freescale.com>
2012-06-14Merge remote branch 'fsl-linux-sdk/imx_3.0.15' into imx_3.0.15_androidXinyu Chen
Conflicts: arch/arm/mach-mx6/board-mx6q_arm2.c arch/arm/mach-mx6/board-mx6q_sabreauto.c arch/arm/mach-mx6/board-mx6q_sabrelite.c arch/arm/mach-mx6/board-mx6q_sabresd.c drivers/video/mxc/mxc_ipuv3_fb.c
2012-06-14ENGR00213336 sabresd pfuze: support 1.2G by param which pass by u-bootRobin Gong
There is no fuse data for distinguish 1.2G or 1G, kernel need support passed param from u-boot that can know 1.2G or 1G. If 1.2G, will configure VDDSOC_IN &VDDARM_IN to 1.425V by pfuze and VDDSOC&VDDPU to 1.25V by internal ldo Signed-off-by: Robin Gong <B38343@freescale.com>
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