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2010-05-07tegra power: Fix gart suspend/resume operationstkasivajhula
Apply proper barriers to suspend/resume operations. The dmb() in suspend is required to prevent a race between the next ENTRY_ADDR write and the previous ENTRY_DATA read. The dsb+outer_sync() in resume() is needed to ensure that the writes and reads occur as expected. Change-Id: I2e66ecce6ceb4f4647bde82cb706b739affeb858 Reviewed-on: http://git-master/r/1291 Reviewed-by: Gary King <gking@nvidia.com> Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Tested-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
2010-05-02tegra odm: Enable USB-VBUS detection through pmu.Venkat Moganty
Enabled USB-VBUS detection through pmu on whistler for turning off USB power rail to reduce the USB power when there is no cable connection. Bug 667912: AVDD_USB_Power is consuming 3.82mW of power in OSIdle and ULP audio playback case. Tested on Android/whistler and USB power goes to 0mW. Change-Id: Ia4bdc327b6d1b86921c296cadc48c3a4a2c35e73 Reviewed-on: http://git-master/r/1245 Tested-by: Dara Ramesh <dramesh@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Tested-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2010-05-02tegra pmu: Add USB-VBUS detection through pmu.Venkat Moganty
Added functionality to detect the VBUS and turn on/off the USB power rail. Bug 667912: AVDD_USB_Power is consuming 3.82mW of power in OSIdle and ULP audio playback case. Change-Id: Ia64e5a04eff16c1ebec2afe1c7bc1e8f72f9da30 Reviewed-on: http://git-master/r/1224 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Dara Ramesh <dramesh@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Tested-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2010-05-02tegra usb:Modifications to usb power up/down sequenceVenkat Moganty
Removed helper thread and replaced it with Worker Queues in udc and ehci drivers to handle usbphy power up/down sequence. Made changes to turn off usb power rail based on vbus detection mechanism is selected as PMU. Fixed usb host LP0 exit sequence. Bug 667912: AVDD_USB_Power is consuming 3.82mW of power in OSIdle and ULP audio playback case. Change-Id: I3a77d0ecb4f0b81dafe705100451c42641f0bfb9 Reviewed-on: http://git-master/r/1221 Tested-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com> Tested-by: Dara Ramesh <dramesh@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Tested-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2010-04-29tegra accelerometer:Adding ODM Bosch accelerometer driver.vdumpa
Checking ODM Bosch accelerometer driver for BMA150 part. This is not a complete driver. The interrupts from BMA150 are not reliably received. The polling mode works fine. This driver need to be updated for changing config settings through sysfs interface. Change-Id: I1492c5661509ba23c3967ed3ea1908bfb4336948 Reviewed-on: http://git-master/r/1180 Reviewed-by: Gary King <gking@nvidia.com> Reviewed-by: Hoang Pham <hopham@nvidia.com> Tested-by: Hoang Pham <hopham@nvidia.com>
2010-04-29tegra dma: Correcting the typo error.Laxman Dewangan
Correcting the spelling error in enum definition TEGRA_DMA_REQ_ERROR_ABOTRED to TEGRA_DMA_REQ_ERROR_ABORTED. Tested on harmony. Change-Id: Ie28aea9f87c1a0a2d3f27ce6132fb3eb48eb59e6 Reviewed-on: http://git-master/r/1225 Reviewed-by: Ramachandrudu Kandhala <rkandhala@nvidia.com> Reviewed-by: Venkata (Muni) Anda <vanda@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Tested-by: Ramachandrudu Kandhala <rkandhala@nvidia.com>
2010-04-29tegra : Increase DMA region size to 4M for Tegra platforms.Venkata(Muni) Anda
Default value of 2MB for DMA allocations is not large enough to cover all the DMA allocation use cases of Tegra drivers. 4MB is a safe and working value. Change-Id: I1f1e9db64ece21e9eef94c909a36cb1a2f50ed68 Reviewed-on: http://git-master/r/1247 Reviewed-by: Venkata (Muni) Anda <vanda@nvidia.com> Tested-by: Venkata (Muni) Anda <vanda@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2010-04-28tegra DFS Clients: Adding DFS tag names for bunch of DFS clients.shranjan
This change should help in finding which drivers are sending busy hints at run time. Bug 475616: All DFS clients should specify client tags while registering with DFS Change-Id: Ic46cebba485dfc1e1b546276658bbcf04fe25d6f Reviewed-on: http://git-master/r/1205 Reviewed-by: Sharad Ranjan <shranjan@nvidia.com> Tested-by: Sharad Ranjan <shranjan@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2010-04-28tegra harmony: remove the WAR added to turn on disaply after resumeMayuresh Kulkarni
When this code was written, we were not aware of how to turn on harmony's display using a single key press. Also, after resume if none of the wake-locks is acquired then system immediately goes to suspend. To avoid this, we added this WAR to acquire a timed wake lock of 10 sec. This gives the user a chance to either press a key/insert-remove usb cable/insert-remove SD card after which the display turns on. Now that we have the way to turn on display by any press, this WAR is not needed. Tested on android + harmony (A02, R04 EC firmware) for LP0 and LP1. For bug 680652 - [SW] Harmony specific suspend_ops implementation Change-Id: I26492f01ed8cf07c5cf448c0e1f67dc99251aaf4 Reviewed-on: http://git-master/r/1236 Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Tested-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Tested-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2010-04-28tegra RM: Tuned DVFS NRT starvation and LC detection.Alex Frid
- Tuned CPU non real-time starvation (NRT) parameters to increase DVFS responsiveness: reduced boost degradation rate to 12%/sample (from 50%/sample); increased initial boost step to 10MHz. - Updated low corner (LC) detection: dropped activity margin from corner hit requirements; cut off NRT degradation tail (this should keep LP2 duty cycle unchanged despite NRT boost increase) Change-Id: I747e7342cb25d8d103577bd2ad01c92446340f42 Reviewed-on: http://git-master/r/1218 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Sharad Ranjan <shranjan@nvidia.com> Tested-by: Sharad Ranjan <shranjan@nvidia.com> Reviewed-by: Niranjan Wartikar <nwartikar@nvidia.com> Tested-by: Niranjan Wartikar <nwartikar@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2010-04-28tegra usb: Enable CONFIG_USB_SUSPENDyhsu
For Bug 679393 to enable selective suspend/resume of USB. Change-Id: I4013f9a3a3a7779f7537b75b419bdb81fcee3878 Reviewed-on: http://git-master/r/1231 Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Tested-by: Yu-Huan Hsu <yhsu@nvidia.com>
2010-04-27tegra usb: fine tuning CPU clock boost freq for USB deviceAbhishek Aggarwal
The CPU clock was previously boosted to 300 MHz for USB device on cable connect for performance optimization. Following issues were noted with this setting: 1. it is above low limit (250MHz) used to turn off slave CPU. Hence it will never be turned off when cable is connected. 2. it is also above PLLP 216MHz output. Hence high power PLLX will be kept alive. Reducing the CPU boost frequency to 200 MHz to address the above issues with minimal impact on the performance. Bug 654486: [whistler/android] - Large difference in USB MSD perf with DFS OFF. Change-Id: Ia57db137b493dd8fe8436ede7942df0661dad67b Reviewed-on: http://git-master/r/1228 Tested-by: Abhishek Aggarwal <aaggarwal@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2010-04-27nvmap: Export NvRmMemPinMult and NvRmMemUnpinMultAndrew Howe
Change-Id: I883ea945f7bac85d6b02530246fc2e0f23937dbe Reviewed-on: http://git-master/r/1219 Reviewed-by: Antti Hatala <ahatala@nvidia.com> Tested-by: Antti Hatala <ahatala@nvidia.com>
2010-04-26tegra lid support : disabled temporarilyBitan Biswas
lid close code was partially checked in. This is causing the screen orientation to change. Disabling the lid support temporarily. Bug 679243 : Android Harmony LVDS rotated into portrait Bug 635301 : [Android\ Whistler \ Harmony] Power off/ Lid (close/open) Button support in Android Tested on : harmony boot orientation restored. Change-Id: I9a5807af5860d2d9c602e9cc3b5ea2216063fa5f Reviewed-on: http://git-master/r/1210 Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Tested-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Tested-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2010-04-23[ARM] tegra: update defconfigs to match auto-generated valuesGary King
Change-Id: I274c8b80a5734e2b017e8fa9c85e994f435ed0ad Reviewed-on: http://git-master/r/1208 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-04-23[ARM] l2x0: rename CONFIG_CACHE_PL3X0 to CONFIG_CACHE_PL310Gary King
... to match expected config name from new korg l2x0 code Change-Id: Ia54867363b2087e8c68784d1a5553bb11a18113e Reviewed-on: http://git-master/r/1207 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-04-23[ARM] tegra: defconfig additionsSheshu Shenoy
Whistler Android: enable PPP, OUTER_CACHE_SYNC, UINPUT Whistler LDK: enable OTG_UTILS, OUTER_CACHE_SYNC Harmony Android: enable OUTER_CACHE_SYNC, UINPUT Harmony LDK: enable OUTER_CACHE_SYNC, USB_ETH, USB_ETH_RNDIS bug 635519 (UINPUT) bug 636848 (USB OTG) bug 673802 (OUTER_CACHE_SYNC) Change-Id: I35531fc1fbb440fdf5173e580cca8b51ea3c6423 Reviewed-on: http://git-master/r/1206 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-04-23tegra power: Clean low power implementations (LP2, LP1, LP0)tkasivajhula
Get rid of some unneeded variables, indented and cleaned things up. Change-Id: I06bf8df81de7f1e68f7175f5f507836a2a88a608 Reviewed-on: http://git-master/r/1145 Reviewed-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com> Tested-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-04-23tegra power: Remove literal usage from LP2/LP1tkasivajhula
The compiler was changing the literal ldr instructions to mov instructions, as a result of which things worked normally. Issues were seen when the compiler stopped automatically optimizing these instructions. Change-Id: I58f1bb018e6aa7a67e1a9ba177182e160dc64e9a Reviewed-on: http://git-master/r/1203 Reviewed-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com> Tested-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-04-23add NvOsShowError()Acorn Pooley
Change-Id: I35cce6b67b2ad0611c742c31ac8e4f6c5b271e3d Reviewed-on: http://git-master/r/1182 Reviewed-by: Acorn Pooley <apooley@nvidia.com> Tested-by: Acorn Pooley <apooley@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-04-23tegra usb: Modified UTMIP regs to prevent electrical test failures.Abhishek Aggarwal
Summary of changes to AP20 USB PHY: 1. UTMIP_XCVR_CFG0: a. UTMIP_XCVR_SETUP field is being set to 0x9. Its programming through fuses is disabled. b. UTMIP_XCVR_HSSLEW_MSB field is programmed to 0 for non-host mode. Its default value on reset is 1. 2. UTMIP_HSRX_CFG1: UTMIP_HS_SYNC_START_DLY field is now set to 0. Previously it was 9. 3. UTMIP_TX_CFG0: Removed programming of UTMIP_FS_PREAMBLE_J field to 1. It should be 0 which is its default value. 4. UTMIP_SPARE_CFG0: Removed programming of this reg since now it is not required to read fuses to obtain value for UTMIP_XCVR_SETUP field. 5. UTMIP_XCVR_CFG1: Programming UTMIP_XCVR_TERM_RANGE_ADJ field to 0x6. Bug 672008: AP20: USB3_UTMIP electrical parameters cause physical-level failures Change-Id: Idadff030d49584b25678179b876ab200f670af21 Reviewed-on: http://git-master/r/1198 Tested-by: Abhishek Aggarwal <aaggarwal@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-04-23tegra: Making the GMC pin group to pull up on harmony.Laxman Dewangan
The GMC group is used by UARTD in the harmony and by power on reset, this group's pullupdown is set to normal. So during kernel boot it throws some junk character in the serial terminal. Setting this group pullupdown to pull up resolve this issue. Change-Id: I28868cd87c88d542c5b29016b7c27ae29cfbc189 Reviewed-on: http://git-master/r/1159 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-04-23tegra-kernel: Fix section mismatch warningsBharat Nihalani
Bug 676157: Kernel builds in 9.12.8, 9.12.9 cause section mismatch warnings Change-Id: Ic288f077d24b03f9d6af2d20dcb01a1bfce25599 Reviewed-on: http://git-master/r/1195 Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Tested-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-04-23panjit touch: Adding the odm panjit touch screen driver.vdumpa
Checking in odm panjit touch screen driver. This is required for new harmony tablet board. This is disabled by default as of now. Also checking updated tegra-gpio.c to have the correct gpio lies info for harmony tablet. This is also disabled by default. Added the acceleremeter properties in the odm kit. The driver for accelerometer will be checked in later. updated copyright headers for panjit. Change-Id: I7089ddb11670670dc0aa683dce190bc619fb07e2 Reviewed-on: http://git-master/r/1139 Reviewed-by: Gary King <gking@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Tested-by: Krishna Reddy <vdumpa@nvidia.com>
2010-04-23tegra serial: Improving the rx flow.Laxman Dewangan
Following improvements are done in the uart rx and tx path: - Separate locks for rx and tx paths. - Implementing the continuous double buffering with same buffer for uart rx. - Deactivating the rts line only incase of if dma does not read the fifo i.e. nonmultiple of 4. - Handling the modem control signal chnage properly. - Created the separate workqueue for the receive to handle dma thresold callback as well as the rx uart interrupts. Tested on harmony and whistler with uart testcase and BT on harmony. we tested the simulatenous file transfer and the A2DP on BT-harmony and did not observe any glitches. Change-Id: Id451ca2f42e246b524a7c9e4bbf3aa832cd0d535 Reviewed-on: http://git-master/r/1172 Reviewed-by: Gary King <gking@nvidia.com> Reviewed-by: Anantha Idapalapati <aidapalapati@nvidia.com> Tested-by: Anantha Idapalapati <aidapalapati@nvidia.com>
2010-04-22tegra RM: Separated DDR2 and LPDDR2 EMC DFS parameters.Alex Frid
Separated EMC DFS parameters for DDR2 and LPDDR2 so they can be tuned independently. Kept all parameters for both SDRAM types unchanged with the exception of LPDDR2 EMC activity margin - set at 100% (2x); this change is a partial revert of commit I8467a52d that caused perf regression on LPDDR2 platforms (no perf regression is observed for DDR2). Change-Id: I193732a376e0a477aef3faf2348b4187d8aca40f Reviewed-on: http://git-master/r/1165 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-04-22tegra : lid supportBitan Biswas
Used EV_SW and SW_LID input events, and modified Android policy manager to respect lid events as wakeups. 1) kernel changes - added driver registration using gpio_keys library Bug 635301: [Android\Whistler\Harmony] Power off/ Lid (close/open) Button support in Android Tested on: harmony. lp1 suspend/wakeup using slider S4 right/left respectively. Change-Id: I694117d64e7319f2efda8251aa8b708ea200e279 Reviewed-on: http://git-master/r/1125 Reviewed-by: Gary King <gking@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Tested-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
2010-04-22tegra:making suspend(lp1) as default low power stateNarendra Damahe
Also disabling sd card detect as a wake source for harmony Change-Id: If826e916847b44086c531b63938861a47718b7da Reviewed-on: http://git-master/r/1183 Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Tested-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-04-21tegra RM: Upadted CPU clock control in LP2 state.Alex Frid
Upadted CPU clock control in LP2 state: - Disabled PLLX on entry to LP2 - Forced CPU divider 1:1 setting on entry to LP2, and restore divider on exit (speed up LP2 entry/exit) - Removed PLLC and PLLM from wake source consideration (commonly these PLLs are disabled in LP2 anyway, but using them in rare case when they are available may create dangerous over-clocking condition) Change-Id: Ied51ebee553766e66d6007e1149270e243df0543 Reviewed-on: http://git-master/r/1155 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-04-21kernel - Backporting explicit cpu_down and L2 cache shutdown from experimentalJitendra Lanka
Bug 673802 - [T20/Harmony/Warm boot] Warm boot stress test failed on Harmony. Backport the changes related to explicit cpu_down and L2 cache shutdown from experimental kernel branch to main line Tested on: Harmony Change-Id: I8615c7e5010ea7133941857cd400a9fb73c0bcc5 Reviewed-on: http://git-master/r/1151 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-04-20tegra:disabling usb0 vbus as a wake sourcetegra-9.12.10Narendra Damahe
Bug 651676, this is causing failure while entering system suspend when lp0 is lowest power state Change-Id: I4337fc00571e21f9a6d39706b74ec62522cb6d46 Change-Id: I4337fc00571e21f9a6d39706b74ec62522cb6d46 Reviewed-on: http://git-master/r/1166 Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Tested-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-04-20tegra power: Enable CPU standby line during initialization.Venkata(Muni) Anda
CPU power request line needs to be explicitly enabled so that PMUs with separate request lines for CPU and core rails will shutdown the CPU power rail as expected. Change-Id: I95bc048b6e1df9029e900d33c4c0f5aa63c008a7 Reviewed-on: http://git-master/r/1156 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Venkata (Muni) Anda <vanda@nvidia.com>
2010-04-20tegra ODM: Added support for new E1108 board (rev B).Alex Frid
Change-Id: I50cb153fd240818ca876dda53a58809740a272d2 Reviewed-on: http://git-master/r/1141 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-04-20[ARM] tegra: fix errors in tegra pinmux tables for SPI, NAND, OWRRaj Mailapalli
Bug 671189, 663161 Tested on Nand + android. Change-Id: I518d8a1b57a9766dc69a115b1189789f054c2d0e Reviewed-on: http://git-master/r/1088 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-04-20tegra pm: adding a delay of 2ms after writing to APBDEV_PMC_CNTRL_0Mayuresh Kulkarni
It seems that after writing SYSCLK_OE bit in APBDEV_PMC_CNTRL_0, a delay needs to be added for stabilization. Reviewed by Bharat. Tested on Harmony (A02, R04 EC firmware) for multiple flash and reboot. Bug 676490 - [T20/Harmony] Bootup failure on harmony-inconsistent (3/5 times) Change-Id: I1f45a86aa23ac00b43f0103285cceda970ee5b39 Reviewed-on: http://git-master/r/1160 Reviewed-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-04-19tegra power: Spurious KBC interrupt WAR. Explicitly disable KBC interrupt.tkasivajhula
The interrupt flag in the 32KHz domain might not be getting cleared correctly. Clear the kbc interrupt explicitly prior to LP0 to fix this. Change-Id: I68c93cb3130fd123e28f1c697b9314b1bbcf4c6e Reviewed-on: http://git-master/r/1154 Reviewed-by: Gary King <gking@nvidia.com> Reviewed-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com> Tested-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com>
2010-04-19tegra nvmap: Enable CONFIG_DEVNVMAP_RECLAIM_UNPINNED_VMvdumpa
Bug 663285 Enable nvmap to reclaim unpinned I/O virtual memory after it has been unpinned and re-use it for other objects. Checking in on behalf of yhsu. Change-Id: I27304b45a80ae0d2fcad9f126672fe6ff5ded2af Reviewed-on: http://git-master/r/1144 Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Tested-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Tested-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-04-16tegra:low power state selection based on ODMDATA for whistler and HarmonyNarendra Damahe
Change-Id: I6969716342df0b28db1167df9bca50a5c03ffb2f Reviewed-on: http://git-master/r/1138 Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Tested-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-04-16tegra power: Flush the L2 rams before entering LP0.tkasivajhula
LP0 turns off core voltage. As a result, the L2 rams need to be flushed prior to shutdown. The L2 cache will be re-enabled after returning from LP0. Change-Id: Ie6e69a3e5615393c5c6e7189b4d7e3559304e7f9 Reviewed-on: http://git-master/r/1036 Reviewed-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com> Tested-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-04-15tegra usb: Enabling busy hints for cpu clockAbhishek Aggarwal
To enhance the USB MSD performance, the busy hints for cpu clock have been enabled on cable connect and its frequency is being boosted to 300 MHz. Bug 654486: [whistler/android] - Large difference in USB MSD perf with DFS OFF Change-Id: I4471665bd02b7b49b368aec4aac5f1b89038c309 Reviewed-on: http://git-master/r/1114 Tested-by: Abhishek Aggarwal <aaggarwal@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-04-15tegra nvec: de-assert EC_REQUEST# properlyVarun Wadekar
Set the GPIO in a reasonable state before calling NvRmGpioConfigPins(Output) to avoid 5us~1ms low-pulse, since the low-pulse causes some EC firmwares to crash. reviewed by Artiste-Hsu tested on Harmony Change-Id: Ia30dfd10dfd16eec979f2a8e6ffc8286121a2eeb Reviewed-on: http://git-master/r/1126 Tested-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-by: Phillip Smith <psmith@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-04-15tegra:enable deep sleep as a lowest power mode for HarmonyNarendra Damahe
Change-Id: Ied68fde9cc9556088837ccaabfdd93c396777218 Reviewed-on: http://git-master/r/1130 Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Tested-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-04-15Enabled CONFIG_CGROUP_SCHED on WhistlerDavid Schalig
On Whistler enabled CONFIG_CGROUP_SCHED instead of CONFIG_USER_SCHED to be in sync with Harmony kernel config. Enables cgroup file system. Bug 669840 Change-Id: I4366b0ad0af5cb57fb7adc373347e081811d0590 Reviewed-on: http://git-master/r/1111 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-04-15tegra RM: Added PMU low power state configuration.Alex Frid
Added PMU low power state configuration to RM kernel suspend/resume. Included PMU interrupt control, and core rail control on platforms with combined cpu/core power request. Restricted core power groups gating to LP1 entry (core domain is down in LP0, anyway). Change-Id: If37ddfd42bd861b2cbc31767775583bd13549da8 Reviewed-on: http://git-master/r/1086 Reviewed-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com> Tested-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Tested-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-04-14tegra ODM: Updated EMC DVFS table on Whistler.Alex Frid
Updated EMC DVFS table on Whistler: - made sure RFC settings are above 5 for all entries - disabled DQS_PULLD for 150MHz entry and below - lowered operational voltage for 18MHz and 27MHz entries from 1.0V to 0.95V Change-Id: I682ed68bb5bfd4497a214065007159ab2fe042b7 Reviewed-on: http://git-master/r/1089 Reviewed-by: Sharad Ranjan <shranjan@nvidia.com> Tested-by: Sharad Ranjan <shranjan@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-04-14tegra RM: Disabled NOR clock.Alex Frid
Disabled NOR clock in RM ("orphan" boot clock). If/when NOR driver is added it will re-enable it as necessary. Change-Id: I5f9b15a5be86c594b6638c3110d9f1d8ba5db694 Reviewed-on: http://git-master/r/1116 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-04-13tegra uart: Fixing the tx and rx dma path issueLaxman Dewangan
Following issue has been fixed: - Blocking write was returning immediatly if data request is multiple of 4. - Blocking write was not able to complete if data length is nonmultiple of 4 and more than 4. - The close was taking too much time because proper timeout and fifo size was not configured. - Tx dma path optimized to fill more data to dma buffer if there is more pending chars in the buffer. - Tx path is fixed to properly signal the wakup event to tty layer. - RTS flow control is not getting set from second open even cflag is requested for that. - Rx dma was not receiving the correct data after second open. The multiple request was getting queued for the receive path at the time of closing. - Rx dma was started before uart controller is configured and it is creating to misbehave the dma. - Transfer count was not getting calculated in the dma driver. Pending issue: - Loosing the data id more than 32K of data was sennt is single shot. Debugging this. Tested on harmony with different testcase developed for testing the linux serial driver. Change-Id: I6ed9095dd6340d2b5e7ef036823d2e4e5a61abcc Reviewed-on: http://git-master/r/1065 Tested-by: Suresh Mangipudi <smangipudi@nvidia.com> Reviewed-by: Udaykumar Rameshchan Raval <uraval@nvidia.com> Tested-by: Udaykumar Rameshchan Raval <uraval@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-04-13Fixing emc_log for AP20shranjan
patch: removing extra spaces Change-Id: Icc7fa7d5744134c0846b99c77b90cd76f9f938fc Reviewed-on: http://git-master/r/1068 Tested-by: Sharad Ranjan <shranjan@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-04-12tegra RM: Reduced LP2 entry threshold.Alex Frid
Adjusted LP2 time padding factor to reduce LP2 entry threshold back to 5ms (commit ad159fa937e9d917737956d12d530b723cba2b13 set it to 12.5ms as a side effect of adding power good delay to LP2 turnaround time) Change-Id: I1f00803e5d043cc6e99aeb7b373c0bdbda56e0ed Reviewed-on: http://git-master/r/1087 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-04-12[ARM] clean slave processor bootup page tables from L2Gary King
by the time that the slave processors' page table pointers are written to memory, the L1 and L2 caches may already be enabled on the master, so the writes need to be forcefully cleaned to memory to ensure that the slave will be able to read it. patch originally submitted to 2.6.34 by RMK Change-Id: Id9952149ce17c693775ec2b21e9a0425465fb770 Reviewed-on: http://git-master/r/1067 Reviewed-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-17 21:03:52 +0000