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1.LDO ramp up time may be modified by ROM code
according to fuse setting, cpu freq driver use
fixed delay time which assume the LDO ramp up time
is the reset value of ANATOP register, need to set
it to reset value in regulator init.
2.The regulator set voltage should take care of
the ramp up time, calculate the ramp up time based
of register setting and to the delay, make sure that
when the set voltage function return, the voltage is
stable enough.
3.CPUFreq no need to use delay, it is already taken
care by regulator voltage setting.
Signed-off-by: Anson Huang <b20788@freescale.com>
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MTD partition for SPI-NOR was not aligned to 8K.
Replace its offset from MTDPART_OFS_APPEND to MTDPART_OFS_NXTBLK.
Signed-off-by: Alejandro Sierra <b18039@freescale.com>
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Fix chip select for SPI-NOR and
remove flags for no writeable partition for weim nor and
SPI-NOR
Signed-off-by: Alejandro Sierra <b18039@freescale.com>
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* Aline weim-nor partition layout with u-boot expected
offtsets
"bootloader" /dev/mtd0
"bootenv" /dev/mtd1
"kernel" /dev/mtd2
"rootfs" /dev/mtd3
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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* Aline spi-nor partition layout
* set correct chip-select value
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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Change 996M setpoint voltage according to datasheet,
lower VDDARM_CAP from 1.275V to 1.25V, and VDDSOC/PU_CAP
from 1.275V to 1.175V.
Signed-off-by: Anson Huang <b20788@freescale.com>
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We must set the DMA mask for esdhc device.
To avoid the following crash when we do not have highmem pages:
[<c0044f90>] (__dabt_svc+0x70/0xa0) from [<c00cf460>]
[<c00cf460>] (mempool_alloc+0x3c/0x108) from [<c00f4aa4>]
[<c00f4aa4>] (blk_queue_bounce+0xc0/0x2fc) from [<c023761c>]
[<c023761c>] (__make_request+0x20/0x2b8) from [<c0235bb4>]
[<c0235bb4>] (generic_make_request+0x3b4/0x4cc) from [<c0235d74>]
[<c0235d74>] (submit_bio+0xa8/0x128) from [<c01279c4>]
[<c01279c4>] (submit_bh+0x108/0x178) from [<c012baa0>]
[<c012baa0>] (block_read_full_pag+e0x278/0x394) from [<c00cd520>]
[<c00cd520>] (do_read_cache_page+0x70/0x154) from [<c00cd64c>]
[<c00cd64c>] (read_cache_page_async+0x1c/0x24) from [<c00cd65c>]
[<c00cd65c>] (read_cache_page+0x8/0x10) from [<c014c354>]
[<c014c354>] (read_dev_sector+0x30/0x68) from [<c014dd4c>]
[<c014dd4c>] (read_lba+0xa0/0x164) from [<c014e300>]
[<c014e300>] (efi_partition+0x9c/0xed4) from [<c014ca0c>]
[<c014ca0c>] (rescan_partitions+0x15c/0x480) from [<c012f190>]
[<c012f190>] (__blkdev_get+0x324/0x394) from [<c012f300>]
[<c012f300>] (blkdev_get+0x100/0x358) from [<c023e5f4>]
[<c023e5f4>] (register_disk+0x140/0x164) from [<c023e73c>]
[<c023e73c>] (add_disk+0x124/0x2a0) from [<c03a7528>]
[<c03a7528>] (mmc_add_disk+0x10/0x68) from [<c03a7820>]
[<c03a7820>] (mmc_blk_probe+0x15c/0x20c) from [<c039cc90>]
[<c039cc90>] (mmc_bus_probe+0x18/0x1c) from [<c0294e28>]
When our DDR size is small or reserved memory are large and
the lowmem can cover all the available pages for kernel,
the highmem pages will not be setup. That means the page_pool
for bounce queue can not be create in init_emergency_pool().
And page_pool will stay NULL without initialized.
In the mmc/card/queue.c the blk_queue_bounce_limit()
function will be called in mmc_init_queue() to
initialize the request_queue and it's bounce_gfp.
If we do not define the DMA mask for our platform,
then the BLK_BOUNCE_HIGH (lowmem pfn) will be set
as limit to queue bounce, which means the blk_queue_bounce
will use page_pool to iterate over the bio segment.
Under the circumstances that highmem is not setup,
the page_pool is null, and causes kernel crash.
After set the DMA mask for esdhci device, the page_pool
will not be used to iterate over the bio segment.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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Previous setting of PUPSCR is 0x202, which means there is only ~63us
for LDO ramp up, sometimes, system fail to resume by USB remote wake up,
increase this timing to fix USB remote wake up issue.
Signed-off-by: Anson Huang <b20788@freescale.com>
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1. Revert ENGR00231910 Do not disable PU regulator,revert the PU
regulator patch;
2. VPU reset register address is different on MX6 and MX5. It can
fix ENGR00230203 [Android_MX6DL_SD] Gallery: System hang after resume
from suspend during video playback. 20%
Signed-off-by: Hongzhang Yang <Hongzhang.Yang@freescale.com>
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If system enter suspend/resume during VPU encoding on Rigel, there will be
"VPU blocking: timeout." error . But there is ok if enter suspend/resume
during VPU decoding and enter suspend/resume during encoding/decoding on
Arik, until now we didn't know the root cause, so revert it firstly.
Because the previous patch about PU regulator is composed with four commits
and hard to revert, now we adopt simplest way that do not disable PU regulator
in low level. The negative impact is there will several mA increasment in
suspend, we will fix it ASAP.
Signed-off-by: Robin Gong <b38343@freescale.com>
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SD card card detection and NFC controller CS2 share
the same pin on ARD platform. However CS2 is not
connected to the socket. This signal was removed
from the sabreauto board file.
Signed-off-by: Alejandro Sierra <b18039@freescale.com>
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not set wm8958 codec as builtin in imx6_defconfig
Signed-off-by: Gary Zhang <b13634@freescale.com>
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There is 6% tolerance for PFM momde in standby so we need set 0.975V(>0.9V+%6)
for VDDSOC and VDDARM which maybe impact system resume ability.
Another two change is:
1.set VDDARM and VDDSOC standby voltage by setting PFUZE register directly,it
is not very friendly.So use more common "state_mem" in constrain of regulator
to set standby voltage.
2.align sabreauto code with sabresd
Signed-off-by: Robin Gong <b38343@freescale.com>
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In mx6q arm2 board, the gpmi conflicts with SD module.
But the defconfig has enabled the gpmi by default.
So we have to add a kernel cmdline to enable the gpmi by hand in arm2 board.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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Add scaling_available_freqs attribute in cpufreq for i.MX
can get cpufreq table info with:
cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies
996000 792000 396000
Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
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The USB FS eye test will fail in MX6 board if the 3V USB phy LDO is not enabled.
Setting enable bit (bit-0) of LDO 3p0 will make 3p0 LDO to use bandgap output as
reference voltage, LDO output will be accurate. And HW team suggest that it is
better to raise the voltage of USB 3p0 phy LDO 3.2V to pass the USB compliance
testing.
- Implement vdd3p0 regulator enable and disable function to support
enable and disable the LDO 3p0 regulator.
- Use regulator API to enable the USB 3p0 phy LDO and raise the LDO
to 3.2V during system boot up. And disable the LDO before system
enter suspend and enable the LDO again after system resume.
Signed-off-by: make shi <b15407@freescale.com>
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Only enable power gating for PXP and EPDC. The feature for ELCDIF still need to
be verified.
Signed-off-by: Robby Cai <R63905@freescale.com>
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Enable CONFIG_VIDEO_MXC_PXP_V4L2 option.
Signed-off-by: Robby Cai <R63905@freescale.com>
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* Add ad7280 I2C device support
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Oscar Luna <r01160@freescale.com>
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Add eCompass support on Sabreauto platform
Signed-off-by: Alejandro Sierra <b18039@freescale.com>
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Configuration file modified to support NAND flash, SPI-NOR,
WEIM NOR and SD card on the same image.
Bootloader arguments will be used to choose between them.
Arguments on uboot are:
spi-nor
weim-nor
By default NAND is configured if neither spi-nor or weim-nor are used
Signed-off-by: Alejandro Sierra <b18039@freescale.com>
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* Adv7180 use tvin io_init callback to configure csi0/ipu
mux settings mx6q_csi0_io_init.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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Write to the MMDC registers when resetting the MMDC after the
DDR I/Os have been floated.
This fixes the bug introduced by the commit:
"2a2f65bd07ad0f947794c2e5f2f825121805d663
MX6SL-Reset MMDC read FIFO in low power IDLE"
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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The REG_BYPASS_COUNTER(RBC) holds off interrupts when the PGC
block is sending signals to power gate the core. This is apart
from the RBC counter's basic functionality to act as counter to
power down the analog portions of the chip.
But the counter needs to be set/cleared only when no interrupts
are pending. And also for correct hold off the interrupts, enable the
counter as close to WFI as possible.
The RBC counts CKIL cycles (32KHz)
So follow the following steps to set the counter
in suspend/resume in mx6_suspend.S:
1. Mask all the GPC interrupts.
2. Write the counter value to the RBC
3. Enable the RBC
4. Unmask all the interrupts.
5. Busy wait for a few usecs to wait for RBC to start counting
in case an interrupt is pending.
4. Execute WFI
Reset the counter after resume in pm.c:
1. Mask all the GPC interrupts.
2. Disable the counter.
3. Set the RBC counter to 0.
4. Wait for 80usec for the write to get accepted.
5. Unmask all the interrupts.
With the above steps, we can minimize the PDNSCR and PUPSCR counters
in the GPC. The basic condition for the RBC counter:
RBC count >= 25 * IPG_CLK + PDNSCR_SW2ISO.
PDNSCR_SW2ISO = PDNSCR_ISO = 1 (counts in IPG_CLK)
PUPSCR_SW2ISO = PUPSCR_ISO = 2 (counts in 32K)
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Fix all build warnings in files:
arch/arm/mach-mx6/board-mx6sl_common.h
arch/arm/mach-mx6/board-mx6sl_evk.c
arch/arm/mach-mx6/clock_mx6sl.c
arch/arm/mach-mx6/cpu_regulator-mx6.c
arch/arm/mach-mx6/pm.c
arch/arm/mach-mx6/system.c
arch/arm/plat-mxc/dvfs_core.c
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
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MMDC can clock in bad data due to the glitches caused by
changing the setting of various DDR IO pads in low power
IDLE to save power. Solution is to reset the MMDC read FIFO
before the DDR exits self-refresh.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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If "debug_uart" is specified in the command line, uart will
be sourced from 24MHz XTAL. This is required for getting the
correct power measurements on MX6SL.
Certain analog power optimizations are done only if ALL PLLs
are bypassed on MX6SL. To verify this path, we need to ensure
that UART is not sourced from PLL3.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Update the VDDARM and VDDSOC voltages based on IMX6SLCEC_Rev0
datasheet.
As the voltages for ARM @ 198MHz and ARM @ 396MHz are the same
remove the 198MHz working point.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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1. Fix AHB clock not changed to 3MHz in IDLE mode
2. Fix system hangs in IDLE mode due to changes made for LOCKDEP
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
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1. Fix mutex_lock nested issue in idle mode
2. Fix mutex_lock nested issue in suspend mode
3. Fix spin_lock nested issue in busfreq
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
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Add csi v4l2 platform device only when 'csi' is assigned in cmdline.
Because there's pin conflicts between csi and epdc.
Signed-off-by: Robby Cai <R63905@freescale.com>
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For DQ and DL, we must make sure DDR can be accessed after resume,
our code did NOT get a valid base address for MMDC to exit from
DVFS mode, need to fix it.
According to ARM, we only need to save r0-r3 and r12 before calling
C function.
Signed-off-by: Anson Huang <b20788@freescale.com>
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issue:
Once entering low power idle mode, pll2_400 will be bypass which will change
the clk rate of sdhc root clk. so far, there's no mechanism to inform sdhc
for changing of root clk in current driver structure.
fix:
Revert "ENGR00226096 mx6sl: remove high set point for usdhc"
This reverts commit 97aee96a34ca63da0d1d602a19b3a444352e5803.
Acked-by: Robby CAI <r63905@freescale.com>
Signed-off-by: Ryan QIAN <b32804@freescale.com>
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Setup uart2 to enable bluetooth basic functionality on mx6sl evk board.
DMA mode was not enabled for uart2 operation.
Signed-off-by: Lionel Xu <Lionel.Xu@freescale.com>
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Currently, the sequence and functionality we use to enter and exit
suspend causes us to hang upon resuming. It appears that this is being
caused by two things. The first is the powering off of the 2p5 rail
which powers the IO pullups and pulldowns. The DQS pins were
configured as pull downs. The second is switching the DQS pins from
differential to CMOS mode (and back). This second problem only
occurs on a few EVK boards.
It is believed that these changes are causing glitches on the mmdc DQS
pins which is putting garbage in the FIFO (or causing some other FIFO
problem). This patch adds two mmdc0 FIFO resets after exiting the
suspend. Two are thought to be needed per previous FIFO reset
experience by Mike Kjar.
Since the MMDC0 FIFO will be cleaned each time, we can now remove
the code that configured the DQS lines as pull downs as we no
longer care if they float.
Signed-off-by: Robert Lee <robert.lee@freescale.com>
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According to the latest specification data, these rails should
go no lower than 900mV in standby mode. This patch modifies
the existing mx6sl board files and sets the pmic standby voltage
for these rails to be 925mV (extra 25mV to account for pmic accuracy).
Signed-off-by: Robert Lee <robert.lee@freescale.com>
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Need to ensure that DDR IO pads are not floated when
a peripheral that needs DDR is active, for ex SDMA.
Also need to keep IPMUX clock enabled even when ARM
is in WFI, so set the CCGR bits accordingly.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Different linker may use r12, we should save/restore all
registers(r0-r12) before calling C function to prevent
these registers from corruption in C code.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Although 400M bus setpoint can save some SOC domain power,
but it will also bring some additional power consumption
to DDR3, and the DDR performace's drop could also lead to
more heat generated by COREs which will spent more time
waiting for DDR data ready, also, there is not many usecases
that need this setpoint, all in all, we should remove 400M
setpoint.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Change STANDBY mode to support the following for MX6SL:
1. assert VSTBY
2. ARM is power gated.
3. XTAL is ON
4. LDO 2P5 is disabled, weak 2P5 is enabled.
5. LDO 1p1 is enabled.
Implement this for a higher power but lower latency on resume
from STANDBY mode.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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* Fix imx_dma_data duplicate struct definition
* Rename struct as name conflicts with imx_dma_data
struct defined at arch/arm/plat-mxc/include/mach/dma.h
* Update copyrigth year.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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MX6SL and MX6DL have only 128KB of IRAM. Fix the
code so the right size is passed to iram_init()
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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- add platform data for csi driver
- change the regulator name to reflect the voltage really used
- select OSC as csi parent clock to get 24MHz
- add an boot option to use csi feature while filter out the EPDC/SPDC, since
there are pin conflicts with xPDC.
- both ov5640 and ov5642 are verified okay, ov5640 is used by default.
- remove IPU from update_defconfig
Signed-off-by: Robby Cai <R63905@freescale.com>
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- remove IPU define
- add csi camera define
Signed-off-by: Robby Cai <R63905@freescale.com>
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Add sii902x GPIO and IOMUX setting to mx6sl evk board.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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-Add CONFIG_FB_MXC_SII902x_ELCDIF variable to mx6s config files.
-Default enable CONFIG_FB_MXC_ELCDIF_FB,
CONFIG_FB_MXC_SEIKO_WVGA_SYNC_PANEL
and CONFIG_FB_MXC_SII902x_ELCDIF.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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Before, PU regulator only be turned off in DSM, which means it kept on in
system normal mode even GPU/VPU driver didn't run. To decrease power number,
PU regulator can be disabled/enabled by GPU/VPU driver, and the voltage value
is tracked by VDDARM which change in cpufreq driver.The patch including:
1.implement PU regulator enable/disable interface in anatop regulator driver
2.remove gpu_power_down and gpu_power_up in system suspend/resume flow.
3.skip change pu regulator set if it has been disabled.
Note: There is three power supply on VDDPU:
a).Use internal anatop PU regulator, VDDDPU_IN is fixed. In this case,VDDPU_CAP
can be turned off or dynamic change by internal anatop(track with VDDSOCi_CAP).
In other words, it use "cpu_vddvpu" regulator as PU regulator,not only in GPU/
VPU driver, but also in cpufreq driver.Sabresd,Sololite EVK is in this case if
disable CONFIG_MX6_INTER_LDO_BYPASS.
b).Use external pmic regulator as PU regulator, it means in LDO bypass way
(CONFIG_MX6_INTER_LDO_BYPASS).But VDDPU_IN is connected with VDDSOC_IN. Because
VDDSOC can't be turned off for ever, and VDDPU track with VDDSOC always, we
remove "pu_id", so that cpufreq driver will never touch it.But GPU/VPU driver
will turn off/on VDDPU_CAP by disabling/enabling "cpu_vddvpu".In this case,
although VDDPU_IN is supplied by external pmic in hardware level, but we can't
turn off external pmic directly, because it connect with VDDSOC_IN.So only we
can do is turn off VDDPU_CAP by internal anatop regulator("cpu_vddvpu").Sabresd
,Sololite EVK is in this case if enable CONFIG_MX6_INTER_LDO_BYPASS.
c).Use external pmic regulator as PU regulator, it means in LDO bypass way
(CONFIG_MX6_INTER_LDO_BYPASS). And VDDPU_IN is in dependent with VDDSOC_IN(
whether short in VDDPU_IN with VDDPU_CAP directly or not).In this case,the only
thing we need to do is that add the right external vddpu regulator name to
"pu_id" in their boad file, and nothing else.
Just like below (arch/arm/mach-mx6/board-mx6sl_evk.c):
static struct mxc_dvfs_platform_data mx6sl_evk_dvfscore_data = {
.reg_id = "VDDCORE",
.soc_id = "VDDSOC",
*******************************************************************
.pu_id = "what you used VDDPU_IN regulator name from external pmic"
*******************************************************************
.reg_id = "cpu_vddgp",
.soc_id = "cpu_vddsoc",
.pu_id = "cpu_vddvpu",
......
Signed-off-by: Robin Gong <b38343@freescale.com>
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Add the following power optimizations when all PLLs
are either disabled or in bypass:
1. Disable 2P5 in system IDLE mode and enable weak 2P5.
2. Set OSC bias current to -37.5% just before the WFI instruction
and set it back to 0% after WFI.
3. Enable the low power bandgap and power down the regular
bandgap.
Also lower AHB and AXI to 3MHz in this mode.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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HDMI AUDIO in evk comes from SPDIF TX, and add SPDIF TX support
to implement HDMI AUDIO feature
Signed-off-by: Gary Zhang <b13634@freescale.com>
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- Due to usdhc ADMA mode has issue working with low bus freq, in
driver usdhc has been configured to SDMA mode already. So it is
not necessary to keep high set point flag any more.
Signed-off-by: Ryan QIAN <b32804@freescale.com>
Acked-by: Dong Aisheng <b29396@freescale.com>
Acked-by: Robby CAI <r63905@freescale.com>
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