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path: root/drivers/gpu/drm/i915/intel_cdclk.c
AgeCommit message (Expand)Author
2018-07-05drm/i915: Mark expected switch fall-throughsGustavo A. R. Silva
2018-06-15drm/i915/icl: implement DVFS for ICLPaulo Zanoni
2018-06-11drm/i915/skl: Add warn about unsupported CDCLK ratesImre Deak
2018-05-03drm/i915: Adjust eDP's logical vco in a reliable place.Rodrigo Vivi
2018-04-23drm/i915/audio: set minimum CD clock to twice the BCLKAbhay Kumar
2018-04-05Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jik...Linus Torvalds
2018-03-27treewide: Fix typos in printkMasanari Iida
2018-02-14drm/i915/vlv: Add cdclk workaround for DSIHans de Goede
2018-02-13drm/i915/icl: add the main CDCLK functionsPaulo Zanoni
2018-02-09drm/i915: Use INTEL_GEN everywhereTvrtko Ursulin
2018-02-06drm/i915/bxt, glk: Increase PCODE timeouts during CDCLK freq changingImre Deak
2018-02-01drm/i915/bxt, glk: Avoid long atomic poll during CDCLK changeImre Deak
2018-02-01drm/i915/bxt, glk: Increase PCODE timeouts during CDCLK freq changingImre Deak
2018-01-19drm/i915/icp: Get/set proper Raw clock frequency on ICPAnusha Srivatsa
2018-01-18drm/i915: Add tracking for CDCLK bypass frequencyImre Deak
2018-01-18BackMerge tag 'v4.15-rc8' into drm-nextDave Airlie
2018-01-04drm/i915: Apply Display WA #1183 on skl, kbl, and cflLucas De Marchi
2017-12-23drm/i915/vlv: Add cdclk workaround for DSIHans de Goede
2017-12-22drm/i915: Apply Display WA #1183 on skl, kbl, and cflLucas De Marchi
2017-11-30drm/i915: Make ips_enabled a property depending on whether IPS is enabled, v3.Maarten Lankhorst
2017-10-25drm/i915/cnl: Allow 2 pixel per clock on Cannonlake.Rodrigo Vivi
2017-10-25drm/i915: Perform a central cdclk state sanity checkVille Syrjälä
2017-10-25drm/i915: Sanity check cdclk in vlv_set_cdclk()Ville Syrjälä
2017-10-25drm/i915: Adjust system agent voltage on CNL if required by DDI portsVille Syrjälä
2017-10-25drm/i915: Use cdclk_state->voltage on CNLVille Syrjälä
2017-10-25drm/i915: Use cdclk_state->voltage on BXT/GLKVille Syrjälä
2017-10-25drm/i915: Use cdclk_state->voltage on SKL/KBL/CFLVille Syrjälä
2017-10-25drm/i915: Use cdclk_state->voltage on BDWVille Syrjälä
2017-10-25drm/i915: Use cdclk_state->voltage on VLV/CHVVille Syrjälä
2017-10-25drm/i915: Start tracking voltage level in the cdclk stateVille Syrjälä
2017-10-25drm/i915: Clean up some cdclk switch statementsVille Syrjälä
2017-10-11drm/i915: Move rps.hw_lock to dev_priv and s/hw_lock/pcu_lockSagar Arun Kamble
2017-09-12drm/i915: Increase poll time for BDW FCLK_DONEMarta Lofstedt
2017-08-31drm/i915: Consolidate max_cdclk_freq check in intel_crtc_compute_min_cdclk()Ville Syrjälä
2017-08-31drm/i915: Track minimum acceptable cdclk instead of "minimum dotclock"Ville Syrjälä
2017-06-29drm/i915: reintroduce VLV/CHV PFI programming power domain workaroundGabriel Krisman Bertazi
2017-06-12drm/i915/cnl: Allow dynamic cdclk changes on CNLRodrigo Vivi
2017-06-12drm/i915/cnl: Implement CNL display init/unit sequenceVille Syrjälä
2017-06-12drm/i915/cnl: Implement .set_cdclk() for CNLVille Syrjälä
2017-06-12drm/i915/cnl: Implement .get_display_clock_speed() for CNLVille Syrjälä
2017-06-02drm/i915/cnp: Get/set proper Raw clock frequency on CNP.Rodrigo Vivi
2017-05-05drm/i915: Fix rawclk readout for g4xVille Syrjälä
2017-04-06drm/i915/glk: limit pixel clock to 99% of cdclk workaroundMadhav Chauhan
2017-03-22drm/i915: Implement cdclk restrictions based on Azalia BCLKPandiyan, Dhinakaran
2017-03-22drm/i915/glk: Apply cdclk workaround for DP audioPandiyan, Dhinakaran
2017-03-13drm/i915: Use new atomic iterator macros in cdclkMaarten Lankhorst
2017-03-07drm/i915: remove potentially confusing IS_G4X checksPaulo Zanoni
2017-02-08drm/i915: Replace the .modeset_commit_cdclk() hook with a more direct .set_cd...Ville Syrjälä
2017-02-08drm/i915: Nuke the VLV/CHV PFI programming power domain workaroundVille Syrjälä
2017-02-08drm/i915: Move PFI credit reprogramming into vlv/chv_set_cdclk()Ville Syrjälä
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