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According to tps80031 datasheet, all 3 interrupt status registers should
be read, before writing to clear them. The old code used interleaved status
read/clear, which may drop interrupts.
Bug 914740
Change-Id: I4c9c0b7c623ea0fe01d90e9a531ff2e9d34f125c
Signed-off-by: David Schalig <dschalig@nvidia.com>
Reviewed-on: http://git-master/r/69941
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
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With this commit below changes to ricoh583 MFD are done:
1. Updating cache copy of int enable register.
2. Changing the prototypes for bulk read & write APIs.
3. Updating rtc platform data structure.
bug 902137
Change-Id: I616d86628addaaa04f3faec035120bd6f9569603
Signed-off-by: venu byravarasu <vbyravarasu@nvidia.com>
Reviewed-on: http://git-master/r/70010
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
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To making robust sleep and wakeup, added sleep_enable into
suspend operation.
Bug 849360
Bug 903301
Reviewed-on: http://git-master/r/66322
(cherry picked from commit ea059cd32c67c72b57000cc5a969741dbf37770d)
Change-Id: I0bafbb3e4d589c0db0842a87132e0cf70e722af3
Signed-off-by: Jin Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/67381
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Supporting the sleep configuration through platform data.
Rearranging clock initialization to take external power control.
Reviewed-on: http://git-master/r/67076
(cherry picked from commit 9da9d369bdbe988b98eec9b63085dfdb26de8237)
Change-Id: I40c5a8608522dbc322e148b5d569e8f5a00faa21
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/67331
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Enable the track control of the LDO4 only when it is
controlled by the PWRREQ1.
bug 822562
Reviewed-on: http://git-master/r/66096
(cherry picked from commit 2140cfb4fa9ba304b199c0144d02af12f1f691b5)
Change-Id: Ibcee5f224647772bde58716c28beae8b6315190f
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/67329
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Some of the values are not supported in the LDO2 configuration
when using in track mode due to hw issue in tps80031 and
tps80032-ES1.0.
Adding proper check before configuring the LDO2 in this case.
bug 898613
Reviewed-on: http://git-master/r/65441
(cherry picked from commit 58e3672102825b662ea904b46b6c1efbf639365b)
Change-Id: I4e63a932d32c7cb2d13a07611acfa0b7dae649cc
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/66327
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
Rebase-Id: R8b818dcb4fdaab118426df32144f846a0ab00fb3
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Adding configuration parameter through platform data
to shutdown the PMIC when shutdown signal in input pin
SHUTDB is active.
bug 900732
Reviewed-on: http://git-master/r/65443
(cherry picked from commit 9327b9815e9791f56f95e0e691c1f1e15cf39b04)
Change-Id: I200c6f8755a55ad1875ba54c9c88a77e0937fb38
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/66325
Rebase-Id: Rcabdd1c5d217bfd201b241f443701d9253625df7
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The Tegra IRQ driver was modified to use ARM GIC driver on kernel-2.6.39.
After that, it has to pass correcting irq flags for ARM GIC when irq request.
Bug 892696
Change-Id: I92e3c24309c2528db4adfd69041f601d627a856d
Signed-off-by: Jin Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/65695
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R38a176520f7216c5637ecc0c8dee3f24f648ac9e
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Moving sleep enable setting from suspend to resume.
And add sleep enable setting into probe.
Bug 849360
Reviewed-on: http://git-master/r/60656
(cherry picked from commit 9ba5f1f22d73fe62d0f509fd6cad26f34e25a017)
Signed-off-by: Jin Park <jinyoungp@nvidia.com>
Change-Id: I7275a5f8d8e0f8d75826854c91946e82d52c8278
Reviewed-on: http://git-master/r/65694
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Re4a4c87dd95180c17680c258b37490bdb3179634
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Acknowledge the tps6591x interrupt by processor only
when it is enabled by client. The acknowledge is done
by writing 1 to INT_STS register.
bug 896151
Reviewed-on: http://git-master/r/64824
(cherry picked from commit 31fbb94516e5b600ad536e35c95e64b525b21f61)
Change-Id: I7f4328f6084f6e94884ac4a87c5c3a247f7fa99d
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/65453
Rebase-Id: R4803a1635b5404226679de09dc15260ff60d44e6
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Using new IRQ apis.
Change-Id: I9eb73a970862c65b3aa7eb6b9c4bd0e4ab5112ba
Reviewed-on: http://git-master/r/62971
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Rebase-Id: Rc1be7da663c58c0093ab7c10f396968ad087e19f
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Moving the configuration function for configuring the
rail control through the PREQ line to core from regulator
driver.
Fixing the correct voltage configuration for the LDO2 based
on TRACK mode.
Reviewed-on: http://git-master/r/63503
(cherry picked from commit 9190130f6cf1ba0bae3231321841ebe4ad94a54e)
Change-Id: I7dd511da7f809a44b1e66706054c0a4c57c36323
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/64055
Rebase-Id: R433728b4c83ccaf6f3ae2734412a90d9c89b6a2c
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Moving the sleep sequence configuration for the pmu from
regulator driver to core driver so that other than power rails,
gpio can also use these APIs.
Reviewed-on: http://git-master/r/62901
(cherry picked from commit 7c2817b42785302c3d9a779c817f70163fabee71)
Change-Id: I9b8584cfd507b34596eee41e9ea799df76c26e5f
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/64098
Rebase-Id: R5a6aead9fdda64bf26c0d59a17f794177e82b640
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The sleep enable is required that AP can be placed MAX77663 into sleep mode
by pulling EN1 input low.
Bug 849360
Original Author : Jinyoung Park
Reviewed-on: http://git-master/r/59477
(cherry picked from commit 469106a1f8cf8d080f06ae0d2e8d0b2aa4bf3e4b)
Reviewed-on: http://git-master/r/62378
(cherry picked from commit 42c8b2466ead1a9382b87d9753afad7d3d7b9b72)
Change-Id: Id205c691bf629c080a533e5d38ef2f3823d35703
Reviewed-on: http://git-master/r/63758
Reviewed-by: Min-wuk Lee <mlee@nvidia.com>
Tested-by: Min-wuk Lee <mlee@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: Rbab33031a6556f229a0bf6aef57f906a95152340
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Supporting the different rails control through the external
control signal PWRREQ1 and PWRREQ2.
Reviewed-on: http://git-master/r/61898
(cherry picked from commit fc07ccae30b61a92fa0b77ee6b2b7c8d43176bbe)
Change-Id: Id6322ef251e4b87673d3a647efb1f0d74b8e0815
Reviewed-on: http://git-master/r/62912
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R687c186e89635a5bd4e3f399709cdf3520936a3f
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Adding gpadc driver for TPS8003x controller
bug 872697
Reviewed-on: http://git-master/r/56987
(cherry picked from commit 9e0a4ef0f800d40d04587538f47ff656fab70971)
Change-Id: I8687d18023f174324d8bb818d73a9bdf8b7ac8f0
Reviewed-on: http://git-master/r/61858
Reviewed-by: Syed Rafiuddin <srafiuddin@nvidia.com>
Tested-by: Syed Rafiuddin <srafiuddin@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Rebase-Id: R984a39824def8aa26b21a6baff86c638a2a75b28
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Correcting typo in the error messages.
bug 822562
Reviewed-on: http://git-master/r/60414
(cherry picked from commit 0accfaa34f91a19ae2aa8eba1f9fc1853ee91576)
Change-Id: Id99fc31bf7c00cab452999c6d133125f16f04e76
Reviewed-on: http://git-master/r/61437
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Rebase-Id: Rb88e19b9510813424033dee100dd3d10f75dca7a
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Configuring the pins in gpio mode when it is used as gpio.
Configuring the correct value of bits when setting the output value.
bug 822562
Reviewed-on: http://git-master/r/58276
(cherry picked from commit b854f309151342689b82bd653738eb94c87db4a4)
Change-Id: I7474d1771d83650db9be71db1f578fd0a50ad19d
Reviewed-on: http://git-master/r/59288
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Rebase-Id: Rf0619d6a3d24059dab15c39c5800a5fd7ee6779b
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For board specific configuration, adding GPIO attributes such as push-pull,
pull-up, pull-down, direction, output level and alternate into platform data.
Bug 849360
Signed-off-by: Jin Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/54429
(cherry picked from commit 3c5148a04fbc50c3200efe8793b8850ca07e05c2)
Reviewed-on: http://git-master/r/55149
(cherry picked from commit c2b439c884808c8452fc32930b6bb5dd66c9c5b4)
Change-Id: I52f360e045358e01740cada440438864a8fc5fe4
Reviewed-on: http://git-master/r/56356
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R605eab7d8d562497cca811bb5931e695cb951542
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Bug 849360
Signed-off-by: Jin Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/54428
(cherry picked from commit 6c06d12f10bc221cde89f5a1738b9f003796dd45)
Reviewed-on: http://git-master/r/55148
(cherry picked from commit 45466efa9c551cd2e5ee05d217a30a1c4342a7cd)
Change-Id: Iad256cf4d6e21e963987df04bd30a1f563ae1d12
Reviewed-on: http://git-master/r/56355
Tested-by: Jinyoung Park <jinyoungp@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: R2b513f87f2e21240821a0a2d05e9e1a861fcc7fb
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Fixed that updating wrong value into cache value after i2c write
in the max77663_cache_write function.
Bug 849360
Change-Id: I62ba38bc2a10f0240cbbefeb71ab5337308d79df
Signed-off-by: Jin Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/51517
(cherry picked from commit da82c830774b6d63f148d4fc9c23922d1c86a0a3)
Reviewed-on: http://git-master/r/54693
(cherry picked from commit a9f47c7de19faf4480c93f1874399345738276f4)
Reviewed-on: http://git-master/r/55470
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Rebase-Id: R93fec5fedf29fc6b52a3f79b4688c28916582934
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The mfd core was updated that removed size_t data_size and
renamed void *platform_data to void *mfd_data in struct mfd_cell.
The new mfd API, mfd_get_data(), was added for mfd device.
It return from struct platform_device to right value of mfd_data
and platform_data.
Change-Id: I9b61d0ac0139be840c328fc0b266752d27815cf5
Signed-off-by: Jin Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/54912
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: Rc0b7b7d376c1bab14eab86a9bdfa4cd5b970bbf8
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The irq core is updated to pass struct irq_data to irq operations.
Updating the MAX77663 driver to new irq APIs.
Change-Id: Id845c1de9d4a98a60993201b9b7740a0633f54fe
Signed-off-by: Jin Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/54674
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Radd1bec604f982a2342842e9681087dd7bf06259
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Rebase-Id: R9e1b0704895a0c413708387071ef2ab2514bcf68
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The irq need to set as wake interrupt to wake from sleep
when interrupt receiving from MAX77663 PMU.
Bug 868996
Signed-off-by: Jin Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/50694
(cherry picked from commit 4bbdf8764bbc262215ab33996e3a91473e7a7e68)
Change-Id: I1489e9a4ea501ac668e040a73ad20fa1fd6544fb
Reviewed-on: http://git-master/r/54634
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: Rba7e15fbb7f58e304aee22d7d39fdbea8e552095
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Add RTC driver for Maxim PMU MAX77663.
Bug 849360
Original-Change-Id: Ia7c910a852527f6a7bf5d2622cb1f76fd72222cd
Signed-off-by: Jin Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/49584
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Rebase-Id: R716e08b9f98c3be480877009bef0db99ccf8043e
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Without this, the IRQ isn't marked as VALID on ARM platforms, and cannot
be requested
Change-Id: Ia2d57dc91b1fac20fc219db4dc2a53e91814428e
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Reviewed-on: http://git-master/r/50552
Rebase-Id: Ra4c788df4357554e86a794e2e91ef403996929c8
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ARM GIC does not allow IRQF_TRIGGER_FALLING.
Change-Id: I9f1430de871b8bce2d1648459e69f43e501515aa
Reviewed-on: http://git-master/r/49624
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: R73c61230fa3ad7657674b248011bb672ffc9315e
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ARM requires an extra step to clear IRQ_NOREQUEST, which it
sets on behalf of every irq_chip.
Change-Id: I7c096b1164f9bf6fb2d24ed1e07c69e217ecebf8
Reviewed-on: http://git-master/r/49189
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: Rc6618ecb83a221bd7da3697d86e55974ee795bec
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Fixed invalid top level interrupt mask register.
And unmasked global interrupt mask bit to receive interrupt signal
from max77663.
Bug 849360
Bug 867797
Original-Change-Id: I7e72b33e3974cf5c7ecc8dd7ad31da19894e59dc
Signed-off-by: Jin Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/48937
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: Rb9113c9fb005d7fb53f76fba82885df87ad8ec85
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Handling watch dog interrupt properly.
bug 841080
Original-Change-Id: I09fe1433005537d3294b16f2959ddd5abf1d8b24
Reviewed-on: http://git-master/r/48364
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Rebase-Id: R8e7f26a9fa5f291fa4b08302f2962e3c0fd9f305
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Adding charging rail ID for registering as regulator.
Original-Change-Id: I654f8d040be5387bc8d6949e0338db6d4fdd5ed4
Reviewed-on: http://git-master/r/48208
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Ramachandrudu Kandhala <rkandhala@nvidia.com>
Rebase-Id: R57f4505477c2bea7e3be5b5f6e7a61e665014181
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Adding core driver for the Powermanagement system device
RICOH 583.
bug 822562
Original-Change-Id: I8a21b42800bd9043f901689ed354618165c42534
Reviewed-on: http://git-master/r/40035
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Rc2821a3f6493ffe8a8ec7a67c214c09b67775433
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Displaying the jtag and eeprom version number of tps8003x
to get informative message during kernel boot.
Original-Change-Id: I10f737a01957da095ab84dd6b6894a9bf73dc39d
Reviewed-on: http://git-master/r/47307
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Rebase-Id: R470501e42a891bf24e9d37a6fe5bc4543424c306
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Add mfd core driver for Maxim PMU MAX77663.
Bug 849360
Bug 854414
Original-Change-Id: I6699540fd7d0f7b428a1be64cf06f7cd65b5b32e
Signed-off-by: Jin Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/41503
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: Rc0f0a67db8b7d554bada7dd6b3e103ab30b374d4
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Adding the TPS6591x gpio definition in tps6591x core header
files.
bug 849976
Original-Change-Id: I1f7a7cc38e220c091ccf44db5af6e43c34daa1cd
Reviewed-on: http://git-master/r/41040
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Rcaf75875841aab0b12f3876086245701eb754669
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Adding public definition in the 80031 header so that client
can used directly in place of defining at client level.
Original-Change-Id: Ifb64e0ffc83bc29c470d08a49d0915613a677537
Reviewed-on: http://git-master/r/40208
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R981610616a78797050538c2a4eb5160ea11384c8
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Creating framework so that tps80031 driver can be instantiated with the
name of tps80032 also and it can provide the device/chip info to its
client.
bug 820885
Original-Change-Id: I1c40b7c6bec1f4abbc670aaa4317fad49e5d308a
Reviewed-on: http://git-master/r/38859
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Rebase-Id: R4953c404fb2af827b53a0173ac6a06806d2f2112
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There is multiple independent case for charge control interrupt and
so exposing each of the case as separate interrupt number.
bug 842072
Original-Change-Id: I500d7e921e07b43de4eefdde2590f045022d8169
Reviewed-on: http://git-master/r/38732
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
Rebase-Id: R2a6a949e0c38731dd28af9c8bc67289f53c0066f
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Original-Change-Id: Ic68fb22749dae71751c64326e0912d6267f1c886
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Rebase-Id: Rd8742c88232a033d8648443bff0271727e713ff1
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The state register is read and write register, if read, it returned
current state, not current written value in register.
So if it want to write the value into state register, it must unconditional
write the value, don't use update(read and compare and then write).
Bug 838189
Original-Change-Id: I2555875a822f159e664b0834af2d00073c859acd
Signed-off-by: Jin Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/38396
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Rebase-Id: Ra90d4ccbe0373bbdad44422e8ff6798eea96019a
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Based on platform, it is require to control the regulator
output through the peripheral power request signal to pmu.
Supporting this type of platform configuration to control
output voltage by sw as well as through PREQ input line.
bug 839809
bug 829405
Original-Change-Id: Ifa19b9062ca2a2c5cae84de1f311a33cec094ad0
Reviewed-on: http://git-master/r/38936
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>
Rebase-Id: R396800524fcea5c74711aec305c29229d32a0908
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Implementing power off functionality to turn off the device.
bug 833661
Original-Change-Id: I2a08f96de7a9814967c774530659f4db47946acc
Reviewed-on: http://git-master/r/35054
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Tested-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Rebase-Id: R9266dff9162e4d6e372c7807275c0f22b349464d
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Rebase-Id: R52ff2d9f5642bfa8b4b41bdfbad32179e92ee2a6
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Rebase-Id: Rdfd4a02d970463fe7bbb21b45e028bdec410e8a7
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Rebase-Id: Rb47edba0c8ede6ef160120776d155445c9223558
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Original-Change-Id: I2d30f3ce900896805b99288e69a22e734d6c3911
Reviewed-on: http://git-master/r/32717
Reviewed-by: Pritesh Raithatha <praithatha@nvidia.com>
Tested-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: R4e34356ab5a8bb6a80421b705453bbe5c7725548
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This change adds the possibility of addressing all addresses on the
tps80031 I2C Bus. The interrupt registers and SMPS1/2 and VIO require
using different I2C addresses to be reached correctly.
bug 830904
Original-Change-Id: I1b5b0d03e531c3c8a0551e5049055930e742e10f
Reviewed-on: http://git-master/r/34866
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Matt Wagner <mwagner@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Rebase-Id: R9e4cc4aaaf79ae8f1e72c0210705b2944510d064
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Protecting the tps6591x register writes/update/clearing bit/setting bit
through lock.
Also fixed some of logical error.
Original-Change-Id: I2df44d65a62027c4a03d3c770655bebe3b394b7b
Reviewed-on: http://git-master/r/33145
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
Rebase-Id: R749310b1b8336b99aa2a8cde97ddc6e32b4e105e
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Adding the init configuration parameter for initializing the gpio of
tps6591x pmic device.
The configuration parameter is passed through platform data.
bug 821295
Original-Change-Id: If83e0b7edfec4d15a879fcf9085506573efbc1ac
Reviewed-on: http://git-master/r/32613
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: R1dd0ccb4d04f30e1861e4859a675edd7a9a19ede
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