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Add gpio irq masking in irq_sync_unlock.
Change-Id: I008caf58ae82d9ed888f4720f54675e9106f027d
Signed-off-by: Jinyoung Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/98664
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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Unmasked EN0 rising interrupt to generate fast PMU_INT by
EN0(POWER_KEY).
Bug 930883
Change-Id: I9a3d8c4f564e83deea86fbd3d05f14933a0b0f65
Signed-off-by: Jinyoung Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/98665
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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We found missed irq could be happened if clear all INT_STS_x register in one time.
Shadow register pushes the irq status after the first byte of INT_STS_x was cleared
The proposed way to clear interrupt is to write only one INT_STS_x register.
It will also clear the other two ones.
Bug 952476
Reviewed-on: http://git-master/r/93453
Signed-off-by: Steve Kuo <stevek@nvidia.com>
(cherry picked from commit 0c92f32e9e03defaeac991518b26134e59ef4db6)
Change-Id: I76179be4847f59a1687926b9b0dde6ebd3f58aa4
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/100306
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Disable Hard Reset on long press of power key.
Bug 893517
Change-Id: Ic328a04e917aa1bed6780e6f9a2f1c575f84fb68
Signed-off-by: Ashwini Ghuge <aghuge@nvidia.com>
Reviewed-on: http://git-master/r/96687
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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Bug 958089
(cherry-picked from commit 7f4c6d6b9dd2b06984b59dcd60d92026cab4c87c)
Reviewed-on: http://git-master/r/92053
Change-Id: I0f2bdb5482fdcb508808d2d58771d74a05b5597f
Signed-off-by: Tom Cherry <tcherry@nvidia.com>
Reviewed-on: http://git-master/r/94117
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
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It is not recommended to use the flag I2C_M_NOSTART in first
message.
The documentation kernel/Documentation/i2c/i2c-proocol says:
Flag I2C_M_NOSTART:
In a combined transaction, no 'S Addr Wr/Rd [A]' is generated at some
point. For example, setting I2C_M_NOSTART on the second partial message
generates something like:
S Addr Rd [A] [Data] NA Data [A] P
If you set the I2C_M_NOSTART variable for the first partial message,
we do not generate Addr, but we do generate the startbit S. This will
probably confuse all other clients on your bus, so don't try this.
Change-Id: I8a8a4f6f91a1b53b6d443588ab18704cf100fd50
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/93187
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Tested-by: Bandi Krishna Chaitanya <bandik@nvidia.com>
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Fixing build error reported by Stephen Rothwell:
drivers/built-in.o: In function `rc5t583_i2c_init':
rc5t583.c:(.init.text+0xb3db): undefined reference to `i2c_register_driver'
drivers/built-in.o: In function `rc5t583_i2c_probe':
rc5t583.c:(.devinit.text+0x8fa0): undefined reference to `regmap_init_i2c'
drivers/built-in.o: In function `rc5t583_i2c_exit':
rc5t583.c:(.exit.text+0x708): undefined reference to `i2c_del_driver'
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
(cherry picked from commit 5364d0b8640dd15e5c0b3ba40d0e874764b1bc88)
Change-Id: If1cfde6c6e0e52b4e55b07401afcd91a895b8905
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/91799
Reviewed-by: Automatic_Commit_Validation_User
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Ricoh power management IC RC5T583 contains is multi
functional device having multiple sub devices inside this.
This device has multiple dcdc/ldo regulators, gpios, interrupt
controllers, on-key, RTCs, ADCs.
This device have 4 DCDCs, 8 LDOs, 8 GPIOs, 6 ADCs, 3 RTCs etc.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Cherry-picked from mainline
1b1247dd75aa5cf5fae54a3bec7280046e9c7957
Change-Id: I5d3bcfb45e232a1a9a210ec14815356ae1918c5d
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/91798
Reviewed-by: Automatic_Commit_Validation_User
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MAX77663 PMU doesn't allow PWR_OFF and SFT_RST setting in ONOFF_CFG1
at the same time. So if it try to set PWR_OFF and SFT_RST to ONOFF_CFG1
simultaneously, handle only SFT_RST and ignore PWR_OFF.
Bug 949650
Change-Id: I90c602e22c813b05fcd9047153cea3ed2cbd596f
Signed-off-by: Jinyoung Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/87981
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Johnny Qiu <joqiu@nvidia.com>
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Implementing the function irq_set_wake() for the interrupts
supported by pmu.
Change-Id: I7dab75d82becbb557af5e1c38f6ed7c93e6761cb
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/86907
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This reverts commit 11c94f0d529a089f8cc37311258fd518be576383.
Stat LED control through PMU GPIO should be implemented in another
way. No need to touch PMU driver.
Change-Id: Iecde818425640616df0a92339e1c0e8b323800bd
Signed-off-by: Johnny Qiu <joqiu@nvidia.com>
Reviewed-on: http://git-master/r/86828
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
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Merge commit '7cccbdc84487616c3dbe493b04bfa1f362f4bc56'
into origin/android-tegra-nv-3.1
Conflicts:
drivers/base/regmap/regmap.c
Change-Id: I7c74b1745e592390538419a2c8026a3ba29be8ea
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
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Using regmap apis for accessing the device registers and
using RBTREE caching mechanims for caching registers.
Enabling caching of the registers which is used for voltage
controls. By doing this, the modify_bits operation is faster as
it does not involve the i2c register read from device, just read
from cache. This results faster set voltage operation.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
cherry picked from mainline commit
0e7018c7b161dc5544f7af862dc59e0b9a0dbd20
Change-Id: Ie0bc1fd32f1c7f7b80004b30ec9ba615d4c29360
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/86349
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Implementing irq_set_wake() so that device should able
to wakeup the system through different interrupt provided
by this device like gpios, onkey, rtc etc.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
cherry picked from mainline
commit 4f5148777f15413a16a5a8751c959828a7fc001c
Change-Id: I894d2e0584f3439a0f7ca7a083337f64bede52b6
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/85126
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irq_base of the tps65910 irq platform data should be
initialized with the board provided irq_base data.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
cherry picked from mainline
commit e2aaed2403078ce919d9cf8091ec0ece8e3f12ad
Change-Id: I9861b612feb85d9b53095d221f09e3059b3b1371
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/85125
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Initialize pm_power_off based on use_power_off passed as platform
data.
Bug 943129
Change-Id: I0a158d226a046809a6d62cf8d9881152cfc2ab83
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/84946
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
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Bug 920845
Bug 931371
Change-Id: I7c03c7f2f16aee1be636c2f8fd8ad18cf7539eae
Signed-off-by: Johnny Qiu <joqiu@nvidia.com>
Signed-off-by: Hao Tang <htang@nvidia.com>
Reviewed-on: http://git-master/r/83724
Reviewed-by: Kerwin Wan <kerwinw@nvidia.com>
Reviewed-by: Simone Willett <swillett@nvidia.com>
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Instead of forcing the board files to register this themselves, just add
a bool to the platform data to let the board files opt into this.
Change-Id: I4993275f31b0539c62249830d6a1180fb2719df8
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Reviewed-on: http://git-master/r/83600
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
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Instead of forcing the board files to register this themselves, just add
a bool to the platform data to let the board files opt into this.
Change-Id: I831c93026f8343d9962e174a3591e6832c5219d8
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Reviewed-on: http://git-master/r/83598
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
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Instead of forcing the board files to register this themselves, just add
a bool to the platform data to let the board files opt into this.
Change-Id: Id3342142e5e7b49d2e16a83889d0b6a1cace1d95
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Reviewed-on: http://git-master/r/83595
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
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Instead of forcing the board files to register this themselves, just add
a bool to the platform data to let the board files opt into this.
Change-Id: Ide3d6cbc49584c3ed993f30b1396c8ae56d87b3b
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Reviewed-on: http://git-master/r/83594
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
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Instead of forcing the board files to register this themselves, just add
a bool to the platform data to let the board files opt into this.
Change-Id: Ia545f23b95f9727932aaf3f3b64a109dae0f2448
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Reviewed-on: http://git-master/r/83592
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
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MAX77663 used on Kai has different I2C slave address from the one
used on PM298. We should add option in platform data to specifiy
the address.
Change-Id: Iaec0a09bbd2b7a37741d8a867be203165d098a15
Signed-off-by: Johnny Qiu <joqiu@nvidia.com>
Reviewed-on: http://git-master/r/83297
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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TPS65910 can be used without interrupts.
Hence let probe succeed in case interrupt can't be
configured and let Kernel only to complain about it
Signed-off-by: Afzal Mohammed <afzal@ti.com>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
cherry picked from mainline's commit
1e351a95b6fda20e16b64a698bae505765080308
Change-Id: Ib619d906f0cc9668c08e156d85eb940f29945771
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/77529
Reviewed-by: Automatic_Commit_Validation_User
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The function is not actually cleaing the bitmask.
Signed-off-by: Marcus Folkesson <marcus.folkesson@gmail.com>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
cherry picked from mainline's commit:
8f6a459a9daa6ce76d7c192f2cb3047fffb45ec8
Change-Id: I53d59ba72ecca513ef4b1ad265d578e493007660
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/77528
Reviewed-by: Automatic_Commit_Validation_User
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Put the power rails into Low-Power Mode during sleep mode,
if SLP_LPM is enabled and the power rail's power mode is GLPM.
Bug 924686
Change-Id: I460f8bfa6be73a440a4924160d8e271695fc4973
Reviewed-on: http://git-master/r/75626
Signed-off-by: Jin Park <jinyoungp@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/75890
Reviewed-by: Automatic_Commit_Validation_User
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This PMIC MFD driver provides-
PMIC register read/write access
support for interrupt handling.
bug 909648
Change-Id: I7f1a22e055b08b9cd31e987c94589c2a8c857d73
Signed-off-by: venu byravarasu <vbyravarasu@nvidia.com>
Reviewed-on: http://git-master/r/73135
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/74894
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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commit 3d6271f92e98094584fd1e609a9969cd33e61122 upstream.
Without turning the MADC clock on, no MADC conversions occur.
$ cat /sys/class/hwmon/hwmon0/device/in8_input
[ 53.428436] twl4030_madc twl4030_madc: conversion timeout!
cat: read error: Resource temporarily unavailable
Signed-off-by: Kyle Manna <kyle@kylemanna.com>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Change-Id: Ib7ef0c519dd78c3bbd2e9903675c2ec16e38831e
Reviewed-on: http://git-master/r/74228
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Tested-by: Varun Wadekar <vwadekar@nvidia.com>
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commit 8653be1afd60d6e8c36139b487e375b70357d9ef upstream.
Check inuse variable before trying to access twl_map to prevent
dereferencing of uninitialized variable.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Change-Id: I5518e7a8f7964cb79760b2ca6736e8997a6e388b
Reviewed-on: http://git-master/r/74186
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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mask the GPIO_SET bit (0x1) before decide set it or not by the input
parameter 'value'
Signed-off-by: Haley Teng <hteng@nvidia.com>
Reviewed-on: http://git-master/r/60425
Reviewed-on: http://git-master/r/66589
(cherry picked from commit d7ac2209e0a3783004fba240eea87a8e569d3745)
Change-Id: I33c69c9aaaf3c9b624fabbcbcab80e75de706d38
Reviewed-on: http://git-master/r/71962
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Haley Teng <hteng@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
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According to tps80031 datasheet, all 3 interrupt status registers should
be read, before writing to clear them. The old code used interleaved status
read/clear, which may drop interrupts.
Bug 914740
Change-Id: I4c9c0b7c623ea0fe01d90e9a531ff2e9d34f125c
Signed-off-by: David Schalig <dschalig@nvidia.com>
Reviewed-on: http://git-master/r/69941
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
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With this commit below changes to ricoh583 MFD are done:
1. Updating cache copy of int enable register.
2. Changing the prototypes for bulk read & write APIs.
3. Updating rtc platform data structure.
bug 902137
Change-Id: I616d86628addaaa04f3faec035120bd6f9569603
Signed-off-by: venu byravarasu <vbyravarasu@nvidia.com>
Reviewed-on: http://git-master/r/70010
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
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To making robust sleep and wakeup, added sleep_enable into
suspend operation.
Bug 849360
Bug 903301
Reviewed-on: http://git-master/r/66322
(cherry picked from commit ea059cd32c67c72b57000cc5a969741dbf37770d)
Change-Id: I0bafbb3e4d589c0db0842a87132e0cf70e722af3
Signed-off-by: Jin Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/67381
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Supporting the sleep configuration through platform data.
Rearranging clock initialization to take external power control.
Reviewed-on: http://git-master/r/67076
(cherry picked from commit 9da9d369bdbe988b98eec9b63085dfdb26de8237)
Change-Id: I40c5a8608522dbc322e148b5d569e8f5a00faa21
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/67331
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Enable the track control of the LDO4 only when it is
controlled by the PWRREQ1.
bug 822562
Reviewed-on: http://git-master/r/66096
(cherry picked from commit 2140cfb4fa9ba304b199c0144d02af12f1f691b5)
Change-Id: Ibcee5f224647772bde58716c28beae8b6315190f
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/67329
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Some of the values are not supported in the LDO2 configuration
when using in track mode due to hw issue in tps80031 and
tps80032-ES1.0.
Adding proper check before configuring the LDO2 in this case.
bug 898613
Reviewed-on: http://git-master/r/65441
(cherry picked from commit 58e3672102825b662ea904b46b6c1efbf639365b)
Change-Id: I4e63a932d32c7cb2d13a07611acfa0b7dae649cc
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/66327
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
Rebase-Id: R8b818dcb4fdaab118426df32144f846a0ab00fb3
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Adding configuration parameter through platform data
to shutdown the PMIC when shutdown signal in input pin
SHUTDB is active.
bug 900732
Reviewed-on: http://git-master/r/65443
(cherry picked from commit 9327b9815e9791f56f95e0e691c1f1e15cf39b04)
Change-Id: I200c6f8755a55ad1875ba54c9c88a77e0937fb38
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/66325
Rebase-Id: Rcabdd1c5d217bfd201b241f443701d9253625df7
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The Tegra IRQ driver was modified to use ARM GIC driver on kernel-2.6.39.
After that, it has to pass correcting irq flags for ARM GIC when irq request.
Bug 892696
Change-Id: I92e3c24309c2528db4adfd69041f601d627a856d
Signed-off-by: Jin Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/65695
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R38a176520f7216c5637ecc0c8dee3f24f648ac9e
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Moving sleep enable setting from suspend to resume.
And add sleep enable setting into probe.
Bug 849360
Reviewed-on: http://git-master/r/60656
(cherry picked from commit 9ba5f1f22d73fe62d0f509fd6cad26f34e25a017)
Signed-off-by: Jin Park <jinyoungp@nvidia.com>
Change-Id: I7275a5f8d8e0f8d75826854c91946e82d52c8278
Reviewed-on: http://git-master/r/65694
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Re4a4c87dd95180c17680c258b37490bdb3179634
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Acknowledge the tps6591x interrupt by processor only
when it is enabled by client. The acknowledge is done
by writing 1 to INT_STS register.
bug 896151
Reviewed-on: http://git-master/r/64824
(cherry picked from commit 31fbb94516e5b600ad536e35c95e64b525b21f61)
Change-Id: I7f4328f6084f6e94884ac4a87c5c3a247f7fa99d
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/65453
Rebase-Id: R4803a1635b5404226679de09dc15260ff60d44e6
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Using new IRQ apis.
Change-Id: I9eb73a970862c65b3aa7eb6b9c4bd0e4ab5112ba
Reviewed-on: http://git-master/r/62971
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Rebase-Id: Rc1be7da663c58c0093ab7c10f396968ad087e19f
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Moving the configuration function for configuring the
rail control through the PREQ line to core from regulator
driver.
Fixing the correct voltage configuration for the LDO2 based
on TRACK mode.
Reviewed-on: http://git-master/r/63503
(cherry picked from commit 9190130f6cf1ba0bae3231321841ebe4ad94a54e)
Change-Id: I7dd511da7f809a44b1e66706054c0a4c57c36323
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/64055
Rebase-Id: R433728b4c83ccaf6f3ae2734412a90d9c89b6a2c
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Moving the sleep sequence configuration for the pmu from
regulator driver to core driver so that other than power rails,
gpio can also use these APIs.
Reviewed-on: http://git-master/r/62901
(cherry picked from commit 7c2817b42785302c3d9a779c817f70163fabee71)
Change-Id: I9b8584cfd507b34596eee41e9ea799df76c26e5f
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/64098
Rebase-Id: R5a6aead9fdda64bf26c0d59a17f794177e82b640
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The sleep enable is required that AP can be placed MAX77663 into sleep mode
by pulling EN1 input low.
Bug 849360
Original Author : Jinyoung Park
Reviewed-on: http://git-master/r/59477
(cherry picked from commit 469106a1f8cf8d080f06ae0d2e8d0b2aa4bf3e4b)
Reviewed-on: http://git-master/r/62378
(cherry picked from commit 42c8b2466ead1a9382b87d9753afad7d3d7b9b72)
Change-Id: Id205c691bf629c080a533e5d38ef2f3823d35703
Reviewed-on: http://git-master/r/63758
Reviewed-by: Min-wuk Lee <mlee@nvidia.com>
Tested-by: Min-wuk Lee <mlee@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: Rbab33031a6556f229a0bf6aef57f906a95152340
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Supporting the different rails control through the external
control signal PWRREQ1 and PWRREQ2.
Reviewed-on: http://git-master/r/61898
(cherry picked from commit fc07ccae30b61a92fa0b77ee6b2b7c8d43176bbe)
Change-Id: Id6322ef251e4b87673d3a647efb1f0d74b8e0815
Reviewed-on: http://git-master/r/62912
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R687c186e89635a5bd4e3f399709cdf3520936a3f
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Adding gpadc driver for TPS8003x controller
bug 872697
Reviewed-on: http://git-master/r/56987
(cherry picked from commit 9e0a4ef0f800d40d04587538f47ff656fab70971)
Change-Id: I8687d18023f174324d8bb818d73a9bdf8b7ac8f0
Reviewed-on: http://git-master/r/61858
Reviewed-by: Syed Rafiuddin <srafiuddin@nvidia.com>
Tested-by: Syed Rafiuddin <srafiuddin@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Rebase-Id: R984a39824def8aa26b21a6baff86c638a2a75b28
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Correcting typo in the error messages.
bug 822562
Reviewed-on: http://git-master/r/60414
(cherry picked from commit 0accfaa34f91a19ae2aa8eba1f9fc1853ee91576)
Change-Id: Id99fc31bf7c00cab452999c6d133125f16f04e76
Reviewed-on: http://git-master/r/61437
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Rebase-Id: Rb88e19b9510813424033dee100dd3d10f75dca7a
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Configuring the pins in gpio mode when it is used as gpio.
Configuring the correct value of bits when setting the output value.
bug 822562
Reviewed-on: http://git-master/r/58276
(cherry picked from commit b854f309151342689b82bd653738eb94c87db4a4)
Change-Id: I7474d1771d83650db9be71db1f578fd0a50ad19d
Reviewed-on: http://git-master/r/59288
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Rebase-Id: Rf0619d6a3d24059dab15c39c5800a5fd7ee6779b
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For board specific configuration, adding GPIO attributes such as push-pull,
pull-up, pull-down, direction, output level and alternate into platform data.
Bug 849360
Signed-off-by: Jin Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/54429
(cherry picked from commit 3c5148a04fbc50c3200efe8793b8850ca07e05c2)
Reviewed-on: http://git-master/r/55149
(cherry picked from commit c2b439c884808c8452fc32930b6bb5dd66c9c5b4)
Change-Id: I52f360e045358e01740cada440438864a8fc5fe4
Reviewed-on: http://git-master/r/56356
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R605eab7d8d562497cca811bb5931e695cb951542
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Bug 849360
Signed-off-by: Jin Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/54428
(cherry picked from commit 6c06d12f10bc221cde89f5a1738b9f003796dd45)
Reviewed-on: http://git-master/r/55148
(cherry picked from commit 45466efa9c551cd2e5ee05d217a30a1c4342a7cd)
Change-Id: Iad256cf4d6e21e963987df04bd30a1f563ae1d12
Reviewed-on: http://git-master/r/56355
Tested-by: Jinyoung Park <jinyoungp@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: R2b513f87f2e21240821a0a2d05e9e1a861fcc7fb
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