Age | Commit message (Collapse) | Author |
|
The irq need to set as wake interrupt to wake from sleep
when interrupt receiving from MAX77663 PMU.
Bug 868996
Change-Id: I2081b7f7bee6a575b38d2e4408f1edce2fdc864e
Signed-off-by: Jin Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/50694
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
Add RTC driver for Maxim PMU MAX77663.
Bug 849360
Change-Id: Ia7c910a852527f6a7bf5d2622cb1f76fd72222cd
Signed-off-by: Jin Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/49584
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
|
|
Fixed invalid top level interrupt mask register.
And unmasked global interrupt mask bit to receive interrupt signal
from max77663.
Bug 849360
Bug 867797
Change-Id: I7e72b33e3974cf5c7ecc8dd7ad31da19894e59dc
Signed-off-by: Jin Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/48937
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
Handling watch dog interrupt properly.
bug 841080
Change-Id: I09fe1433005537d3294b16f2959ddd5abf1d8b24
Reviewed-on: http://git-master/r/48364
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
|
|
The tps6586x_gpio_set function is resetting all other GPIO pins.
We need to update the right GPIOxOUT bit of the GPIOSET2 register instead
of overriding the full value.
Also Inverted GPIO and subdevices initialization.
When using a fixed voltage regulator, this allows to declare
and initialize it conveniently from the "subdev" list.
Bug: 829647
Change-Id: I1480c2d1f2bee549ebc81fef264841c9a9e4daaa
signed-off-by: Preetham Chandru <pchandru@nvidia.com>
Reviewed-on: http://git-master/r/47809
Reviewed-by: Allen R Martin <amartin@nvidia.com>
|
|
Adding charging rail ID for registering as regulator.
Change-Id: I654f8d040be5387bc8d6949e0338db6d4fdd5ed4
Reviewed-on: http://git-master/r/48208
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Ramachandrudu Kandhala <rkandhala@nvidia.com>
|
|
Adding io mutex into I2C update function to prevent race condition
problem.
Signed-off-by: Jin Park <jinyoungp@nvidia.com>
Change-Id: Ibff85a825a6716bfc88eea55704bbbcc565cf962
Reviewed-on: http://git-master/r/48136
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
Adding core driver for the Powermanagement system device
RICOH 583.
bug 822562
Change-Id: I8a21b42800bd9043f901689ed354618165c42534
Reviewed-on: http://git-master/r/40035
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
|
|
Displaying the jtag and eeprom version number of tps8003x
to get informative message during kernel boot.
Change-Id: I10f737a01957da095ab84dd6b6894a9bf73dc39d
Reviewed-on: http://git-master/r/47307
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
|
|
Add mfd core driver for Maxim PMU MAX77663.
Bug 849360
Bug 854414
Change-Id: I6699540fd7d0f7b428a1be64cf06f7cd65b5b32e
Signed-off-by: Jin Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/41503
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
Adding the TPS6591x gpio definition in tps6591x core header
files.
bug 849976
Change-Id: I1f7a7cc38e220c091ccf44db5af6e43c34daa1cd
Reviewed-on: http://git-master/r/41040
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
|
|
Adding public definition in the 80031 header so that client
can used directly in place of defining at client level.
Change-Id: Ifb64e0ffc83bc29c470d08a49d0915613a677537
Reviewed-on: http://git-master/r/40208
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
|
|
Creating framework so that tps80031 driver can be instantiated with the
name of tps80032 also and it can provide the device/chip info to its
client.
bug 820885
Change-Id: I1c40b7c6bec1f4abbc670aaa4317fad49e5d308a
Reviewed-on: http://git-master/r/38859
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
|
|
There is multiple independent case for charge control interrupt and
so exposing each of the case as separate interrupt number.
bug 842072
Change-Id: I500d7e921e07b43de4eefdde2590f045022d8169
Reviewed-on: http://git-master/r/38732
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
|
|
The state register is read and write register, if read, it returned
current state, not current written value in register.
So if it want to write the value into state register, it must unconditional
write the value, don't use update(read and compare and then write).
Bug 838189
Change-Id: I2555875a822f159e664b0834af2d00073c859acd
Signed-off-by: Jin Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/38396
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
|
|
Based on platform, it is require to control the regulator
output through the peripheral power request signal to pmu.
Supporting this type of platform configuration to control
output voltage by sw as well as through PREQ input line.
bug 839809
bug 829405
Change-Id: Ifa19b9062ca2a2c5cae84de1f311a33cec094ad0
Reviewed-on: http://git-master/r/38936
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>
|
|
Implementing power off functionality to turn off the device.
bug 833661
Change-Id: I2a08f96de7a9814967c774530659f4db47946acc
Reviewed-on: http://git-master/r/35054
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Tested-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
|
|
Change aat2870_bl suspend and resume event source to backlight driver
from platform driver.
Clean-up codes.
Bug 813111
Change-Id: If04b77bf0c3c3118f05107db6ffeaea7a21cdfac
Signed-off-by: Jin Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/35390
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
Change-Id: I2d30f3ce900896805b99288e69a22e734d6c3911
Reviewed-on: http://git-master/r/32717
Reviewed-by: Pritesh Raithatha <praithatha@nvidia.com>
Tested-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
This change adds the possibility of addressing all addresses on the
tps80031 I2C Bus. The interrupt registers and SMPS1/2 and VIO require
using different I2C addresses to be reached correctly.
bug 830904
Change-Id: I1b5b0d03e531c3c8a0551e5049055930e742e10f
Reviewed-on: http://git-master/r/34866
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Matt Wagner <mwagner@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
|
|
Protecting the tps6591x register writes/update/clearing bit/setting bit
through lock.
Also fixed some of logical error.
Change-Id: I2df44d65a62027c4a03d3c770655bebe3b394b7b
Reviewed-on: http://git-master/r/33145
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
|
|
Adding the init configuration parameter for initializing the gpio of
tps6591x pmic device.
The configuration parameter is passed through platform data.
bug 821295
Change-Id: If83e0b7edfec4d15a879fcf9085506573efbc1ac
Reviewed-on: http://git-master/r/32613
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
|
|
Adding core and regulator driver for the TI pmu device tps80031.
Following functionality is added:
- Basic core driver interface to access register.
- Regulator driver.
- gpio driver.
- interrupt support from pmu.
- clock 32 initialization.
bug 830904
bug 829658
Change-Id: I41e732c0b5d0472209798552b5264038e5a97ee4
Reviewed-on: http://git-master/r/33109
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
|
|
The mpu80031 is having the register compatibility with
twl6030 and so the mpu80031 driver is based on twl6030
register programming.
But mpu80031 has capability of generating 32KHz which
is not there in twl6030. Adding subclass for mpu80031
to identify this feature and adding support for 32KHz
clock generation.
bug 829520
Change-Id: Icac2b0913fb680a472ebbcdc2ec3a54d1df0ebf1
Reviewed-on: http://git-master/r/32595
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
|
|
Adding backlight, regulator and mfd driver for AnalogicTech AAT2870.
Bug 813111
Signed-off-by: Jin Park <jinyoungp@nvidia.com>
Change-Id: I0621a25545708d260285545b184f4689a32fa16b
Reviewed-on: http://git-master/r/32366
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
Adding controls for the following items
1. PMU SLEEP state enable/disable
2. Keep 32KHz clock out on sleep mode
3. Keep thermal monitor on sleep mode
4. Keep LDO full load capability on sleep mode
5. Keep high speed internal clock on sleep mode
3. Turn off power rails on sleep mode
Change-Id: I389bca4a4d7ff9ae264727af8e93dcec796d3c0c
Reviewed-on: http://git-master/r/32222
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Chih-Lung Huang <lhuang@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
|
|
Adding all tps6591x register dump through the debugfs interface.
This will help to find out the configuration of different sub module
inside the pmic.
Change-Id: I9bf3c1c4cb8cc5d29e81b48bad21bfb9ca91d8fa
Reviewed-on: http://git-master/r/29675
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
|
|
Implemention direction_input() of the tps6591x-gpio and returing
correct value from gpio based on direction.
Change-Id: I114a7101c2a14b61b2e475bdab547ea7601f6b93
Reviewed-on: http://git-master/r/29627
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
|
|
Adding the TI 6025 PMU regulator driver.
Original-Change-Id: I8ad675711bbe2ae942bcc0e32b711883eae215b4
Reviewed-on: http://git-master/r/27342
Tested-by: Venkata Nageswara Penumarty <vpenumarty@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Change-Id: Ib91f033c557bb7f4c87522ae4f5c7922a62f71f8
|
|
Implementing power off functionality to turn off the device.
To power off device, setting the PWR_OFF_SEQ bit in the PMU's
DEVCTRL_REG register, and then clearing the DEV_ON bit in the
same register
bug 787957
Original-Change-Id: I3564f7918745e61d1a8debc0e4840e32fa4da782
Reviewed-on: http://git-master/r/24111
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Ramachandrudu Kandhala <rkandhala@nvidia.com>
Change-Id: I06d81f6d3439e780f5779946d2af1765b8a2fb0e
|
|
If the system is woken by an tps interrupt to AP, tps' irq handler
gets called and it tries to communicate on i2c. i2c adapters
resume later which causes communication failures in tps' irq
handler. the right way is to disable tps' irq ion AP while suspending
in order to avoid such i2c communication failures.
tps interrupt will still b able to wake AP from suspend.
Original-Change-Id: I29c83aa80e2662793c5e9b278ad1b7efd46616be
Reviewed-on: http://git-master/r/22410
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Tested-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Change-Id: Ie917b0b617bf9c0c90bfce15948340e2393ed0ce
|
|
Masking all interrupts from tps6591x by default and configuring
the PMU interrupt to active low.
Original-Change-Id: I2a40bb5f50d7f749debe1a8a478680acf69767a4
Reviewed-on: http://git-master/r/22066
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com>
Change-Id: I676785668026e4ef02a076f70bdb9d292263b346
|
|
Calling the client isrs from tps6591x isrs.
Original-Change-Id: Ic0caf1a3802c24df1cf76087e319a3417be88117
Reviewed-on: http://git-master/r/20887
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Change-Id: I2b67d6689b9884a6917aa9882e1f86ad8b6a484c
|
|
Disabling all interrupts mask of pmu during init as no client have
registered for interrupt.
Once client registers the interrupt, the corresponding interrupt
get enabled.
Original-Change-Id: I5c263476174a63bd7253683637acf7ab5d9ebf11
Reviewed-on: http://git-master/r/17485
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Kaushik Sen <ksen@nvidia.com>
Change-Id: I602a70bef98c45aac0d5241cad7f140825ca33fc
|
|
Adding regulator and mfd core driver for TI TPS6591x PMIC family.
Original-Change-Id: I65c0e4758094f211f7e9f0944423bd935c1893c4
Reviewed-on: http://git-master/r/16529
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
Change-Id: I2f82c178e3db0998e7c1a5a3b6b8e49832deaf59
|
|
apis added to program max8907c regulator to power down and up core supply rail
via the pwren signal on enter and exit deep sleep mode.
Bug 817378
Change-Id: I5af04db22b6c84fc4359c1a0cf209710ca144159
Reviewed-on: http://git-master/r/28434
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
This reverts commit d64db664f2e8d6f4d08db249135011e32d54bc7a.
Change-Id: I8de61440cbbe5a12f8cf2d045e7035b9a0ab7369
Reviewed-on: http://git-master/r/22775
Tested-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
Add an api to power off max8907c by setting power off bit in RESET_CNFG reg.
Bug 799957
Bug 800602 (Cold boot)
Change-Id: Ie0206d684a86fecc75273c1d3b087bb2d47b4c56
Reviewed-on: http://git-master/r/22385
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
if the system is woken by an alarm, tps' irq handler
gets called and it tries to communicate on i2c. i2c adapters
resume later which causes communication failures in tps' irq
handler. the right way is to disable tps' irq while suspending
in order to avoid such i2c communication failures.
Change-Id: I8487c8b9039d2736acf66e8b02463658428bd5a3
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/21099
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
This change allows the max8907c to wake the system when receiving an
irq. It also masks all non-wake conditions from causing an irq when
going into suspend and unmasks these conditions when resuming to not
cause spurious wake-up events.
Change-Id: I5eadb929ff4aded8a6ec11426ab424f0f692c042
Reviewed-on: http://git-master/r/20100
Tested-by: Thomas Cherry <tcherry@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
tps6586 does not support burst writes. i2c writes have to be
1 byte at a time.
Change-Id: Iaf4fd9a3c1b983a3bb9a1ef680e03b14a69d736b
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/18561
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
Clean up portions of max8907c.c driver
Add capability for bulk i2c read and write
Add capability for second i2c bus for rtc
Add capability for irq handling for rtc and battery charger
Change-Id: I6c2c2c42591aee766635a2e32a7404bb2591f4a7
Reviewed-on: http://git-master/r/16613
Tested-by: Thomas Cherry <tcherry@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
Conflicts:
arch/arm/mach-tegra/fuse.c
drivers/misc/Makefile
Change-Id: I300b925d78b31efe00c342190d8dbd50e2e81230
|
|
|
|
commit bd7c72ed18d719c1fb0fdf6ff9042d8ab78fdf71 upstream.
Without this the IRQ base will not be correctly configured for the
subdevices.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
|
|
commit b93cef556162b0f33399bfe5f307c54f51554e09 upstream.
Some newer device revisions add a second parent ID. Support this in
the device validity checks done at startup.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
|
|
Replaced write to GPIO pin with read-modify write as old value was
overwritten.
Change-Id: I679994ba920b70f90a2b1654ee2c0fcc3e08d02e
Reviewed-on: http://git-master/r/14540
Reviewed-by: Amit Kamath <akamath@nvidia.com>
Tested-by: Amit Kamath <akamath@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
Conflicts:
arch/arm/mach-tegra/board-ventana-power.c
drivers/mfd/tps6586x.c
Change-Id: Ic8c46d4251d6e71fa2900b7e876f87e256299bc4
|
|
... and convert it to a dev_info print at probe time.
There are many variants of this chip with different values of VERSIONCRC.
The set of values is large, and not useful to enumerate. All are SW
compatible. The difference lies in default settings of the various power
rails, and other similar differences. The driver, or clients of the
driver, shouldn't be affected by this, since all rails should be
programmed into the desired state in all cases for correct operation.
Derived-from-code-by: Andrew Chew <achew@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
|
|
The interface for this device should be identical to that of the
TPS658521A.
Signed-off-by: Andrew Chew <achew@nvidia.com>
Acked-by: Mike Rapoport <mike@compulab.co.il>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
|