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path: root/drivers/rtc/rtc-tps6586x.c
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2011-11-30rtc: tps6586x: Fix for proper wakealarmWei Ni
In the driver probe function, call device_init_wakeup() before registering rtc device, so that wakealarm sysfs will be created. BUG=889820 Change-Id: I957fdffb02cd7e43dd96db0794e2e9f8dc7bd3ee Signed-off-by: Wei Ni <wni@nvidia.com> Reviewed-on: http://git-master/r/58937 Reviewed-by: Allen Martin <amartin@nvidia.com> Reviewed-on: http://git-master/r/63244 Rebase-Id: R9e078974bd9e773443b19492b83d25694f4582c2
2011-11-30rtc : tps6586x: move NULL checking to the front.Jubeom Kim
Reviewed-on: http://git-master/r/37866 (cherry picked from commit 4299db4686321fb3017f9118a36610898f172639) Original-Change-Id: Icbfef4dc5604506d30592317c94a7d4fc1bcf16c Reviewed-on: http://git-master/r/39582 Tested-by: Jubeom Kim <jubeomk@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: R7d8f5628cde155fe54d31f37eeacb4b5bb4962d1
2011-11-30rtc: tps6586x: fix error in setting alarm1Ken Chang
Alarm1 expiration time is set based on rtc value. Should not compare the absolute rtc value with the valid range of alarm1 directly, expiration time from now is used instead. Bug 832563 Original-Change-Id: I338e7ee684b5cad6b2fba99b5ac4ec6cff9b75cd Reviewed-on: http://git-master/r/34295 Tested-by: Ken Chang <kenc@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-by: Yu-Fong (Foster) Cho <ycho@nvidia.com> Rebase-Id: Rb4f233478ea418ddf5a7ae9e1d782dbc5c97cbde
2011-11-30rtc: tps6586x: fix alarm1 overflowKen Chang
tps6586 alarm1 has a 24-bit register, however LSB 10 bits [9:0] are used as a counter of ticks per second. Therefore, the valid range is within 0x3FFF seconds (14-bit width). Check the value set to alarm1. Change the value to (current rtc[23:10] minus 1) if the target value is larger than 0x3FFF (4 hours). If no such fix, there might be overflow issues when alarm1 is enabled, and the system might wakes up unexpectedly. This change is to keep the system in suspend state as long as possible if alarm is enabled. Bug 827056 Original-Change-Id: Icb310132e08b56642179d92dfe00a34bfd28982a Reviewed-on: http://git-master/r/32700 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Ken Chang <kenc@nvidia.com> Reviewed-by: Yu-Fong (Foster) Cho <ycho@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-by: ChihJen Hsu <chhsu@nvidia.com> Rebase-Id: Receaa52de2019ef4a02403312afa1385e5642caf
2011-11-30rtc: fix tps6586x startup crashDan Willemsen
The rtc_device_register() call has changed semantics so that it will immediately call out to rtc_read_alarm() and since the callbacks require the drvdata to be set, we need to set it before the registration call to vaoid NULL dereference. Based on 9cf3b5fa6f7b246784d62a2a7637a871290c9ab9 Rebase-Id: R641c71563fd9b41a92b2d6679c04edf94ed36e25
2011-11-30rtc : tps6586x: avoid RTC time is getting slowerDaehyoung Ko
To ensure an accurate read of the RTC registers during the required multi-byte read operation, the PMU RTC is designed with the following protection scheme - A circuit detects a write/read and locks the RTC_COUNT4 value by keeping the RTC in a suspended mode - During the suspended mode, a secondary counter is used to keep track of all counts that would have normally incremented the RTC - After the read is complete, the value of the secondary counter is added back to the RTC registers and thereby keeping the RTC accurate - The backup counter allows for a 1ms RTC suspend mode duration when the RTC prescaler is enabled. i2c needs to generate a 2 msgs when reading. - the address setup(write RTC_COUNT4 operation), hence start locking the RTC_COUNT4 - the data transfer (read RTC_COUNT4 operation),release locking it. this may allow the CPU to execute other portions of code in between the two operation. The fix is to start a PMU RTC access by reading the register prior to the RTC_COUNT4 so that access of the RTC PMU registers will be guaranteed to always occur within the 1ms time period. - the address setup(write RTC_COUNT4-1 operation), so there is no locking the RTC_COUNT4 - the data transfer (read RTC_COUNT4 operation), starting locking the RTC_COUNT4 and release locking the RTC_COUNT4 in one operation, so it will be guaranteed within 1ms Bug 811075 Original-Change-Id: Ie07472a329f6a0eed11e6a039cd93307bb5276a0 Reviewed-on: http://git-master/r/27537 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R0279c3dac03756636596c504e623b7159ee474f7
2011-11-30rtc: tps6586x RTC clock fixAndre Sihera
Specified OSC_SRC_SEL flag to force clock signal to be taken from an externally generated source rather than be calculated internally. This should raise the accuracy to within +/-2 seconds/24 hours. Bug 811075 Bug 810537 Original-Change-Id: I7b7c4e4d752fdc03b81239f362a1d6f7aa4d3b92 Reviewed-on: http://git-master/r/27222 Reviewed-by: Andre Sihera <asihera@nvidia.com> Tested-by: Andre Sihera <asihera@nvidia.com> Reviewed-by: David Schalig <dschalig@nvidia.com> Reviewed-by: Scott Peterson <speterson@nvidia.com> Rebase-Id: Re6e093fb517b06f7218e55e2ac7b8d15764d9c57
2011-11-30[TPS658x RTC] Correct reg RTC_CTRL usageDavid Schalig
Correct PRE_BYPASS (clock scaler 32kHz/1kHz select) bitfield. Add platform data to tune RTC XTAL capacitance in board file. Bug 798832, Tested on Ventana/wake via Alarm Clock Original-Change-Id: I82d67610a815866707fc1db934d7d4d7cf93d883 Reviewed-on: http://git-master/r/22402 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Reviewed-by: David Schalig <dschalig@nvidia.com> Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Rebase-Id: Rf54ae72ccdf2538dcaed60590aa98780a365628b
2011-11-30rtc: tps6586x: avoid enabling/disabling of same irqVarun Wadekar
alarm_irq_enable can enable/disable irqs and the same irq will be enabled/disabled in set_alarm. Bug 770380 Original-Change-Id: Ibd006e83028cea5cd251d789d258a5549bfa34ce Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/18661 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: R9cec649a63d4553d20806804cc5400b6e6ccb60e
2011-11-30rtc: tps6586x: enable irqs while settings alarmsVarun Wadekar
Bug 770380 Original-Change-Id: I8950a3ef2259b233b1711b266fa7d29270d95bfd Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/18565 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: Ra059906c34e171e4cd28e9e07dc4770dd2624793
2011-11-30mfd: tps6586x: fix alarm1 supportVarun Wadekar
instead of clearing the irq for alarm enable/disable, the proper bit in RTC_CONFIG has to be set/cleared. tps6586 does not support 1/sec update counter so remove support for update_irq_enable. replace it with alarm_irq_enable. Original-Change-Id: Iee66a6625e810169253a750faf3f12d20d65d7d9 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/17990 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: Rc6bdf71591a07e90f7bb3b7c6b519a76fd9e86ca
2011-11-30rtc: tps6586x: Fix error in RTC tick calculationsLowell Dennis
In the TPS6586x PMU/PMIC RTC support code, when converting from seconds to ticks using a shift operator, the most significant bits were being lost due to seconds being a 32-bit value and ticks being a 64-bit value. A hard cast was added to avoid this loss. Reviewed-by: Lowell Dennis <ldennis@nvidia.com> Tested-by: Lowell Dennis <ldennis@nvidia.com> Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Reviewed-by: Peter Zu <pzu@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Signed-off-by: Robert Morell <rmorell@nvidia.com> Signed-off-by: Colin Cross <ccross@android.com>
2011-11-30rtc: tps6586x: add alarm support to tps6586x driverGary King
Signed-off-by: Gary King <gking@nvidia.com>
2011-11-30mfd: tps6586x: add RTC driver for TI TPS6586xGary King
Change-Id: Ie22a19b662fda6365b1c514aaf83c9de12fabbd4 Signed-off-by: Gary King <gking@nvidia.com>
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