Age | Commit message (Collapse) | Author |
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Add inline wrappers for device_prep_slave_sg() and device_prep_dma_cyclic()
interfaces to hide new parameter from current users of affected interfaces.
Convert current users to use new wrappers instead of direct calls.
Suggested by Russell King [https://lkml.org/lkml/2012/2/3/269].
Signed-off-by: Alexandre Bounine <alexandre.bounine@idt.com>
Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
cherry-picked from mainline commit
16052827d98fbc13c31ebad560af4bd53e2b4dd5
Change-Id: I929a49556539621a0546829e88b3caa498c94be2
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/94463
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To terminate request from dma, use the tegra_dma_cancel() inplace of
tegra_dma_dequeue().
The api tegra_dma_dequeue() is getting to be obsolete.
Change-Id: I297e67433a2118377ecb9b028dcf8fa82e09f0e2
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/91752
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ashwini Ghuge <aghuge@nvidia.com>
Tested-by: Ashwini Ghuge <aghuge@nvidia.com>
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Making sure that SCLK frequency should be maintain on minimum
require value during spi transfer. This is require to proper
functioning of spi controller.
bug 949393
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/89526
Cherry-picked from commit
7d83f658b39b2ab1a5105eec7649246fddea7325
Change-Id: I60fa0fef98e5f2882c646c29e1773194deddd6da
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/90296
Reviewed-by: Automatic_Commit_Validation_User
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Fixing the logic to clear/set spi cs level on default command
register.
Change-Id: I55e130ecb02dae6e11ad7048730ed11df9848e94
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/86888
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
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Removing checkpatch error and warnings from spi driver
resulted from checkpatch.
Change-Id: I92160e802781b583048f46a93dee7d2465689cc0
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/85163
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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When dma coherant buffer need to be access by cpu or apb dma,
it is require to calling the dma_sync_single_for_cpu() when cpu
wants to access it and dma_sync_single_for_device() when dma
wants to access the buffer.
Change-Id: I62fc7fced782f3fc2d145c0d5416a4c8cbe30715
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/85138
Reviewed-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
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The dma client should use the tegra_dma_dequeue_req() for
dequeue the dma request.
Change-Id: I1f433c85ffec997d8c608e08509c48c72b27120a
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/77804
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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Used run time apis for clock controls i.e. clock enable/
disable in place of direct clock apis.
Using of runtime pm api was already implemented but it was
missed on probe where it was calling clock_disable.
Fixing this issue.
bug 928541
Change-Id: I511467bd1cbe05f2a05d219d19236426a30d05d5
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/78156
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Reviewed-by: Ashwini Ghuge <aghuge@nvidia.com>
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Bug 886806
Original commit: http://git-master/r/59905
Change-Id: Ia8d64f3810d6157c6029180cd9a3cf98c2d3cb4c
Signed-off-by: Ashwini Ghuge <aghuge@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/74896
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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When fifo is read, it can contain valid data bits and random bits
in rest of the fifo.
Reading only valid bits from fifo and resetting rest to zero
before sending to client.
Change-Id: I961279048aada6087b323ab6730bf72706730917
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-on: http://git-master/r/70534
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Fixed warning message
Bug ID: 912669
Change-Id: I3090c35a5d0725102c101b10a99914510a272fa4
Reviewed-on: http://git-master/r/69444
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Rebase-Id: Rbc628711479b187a90437bea94776066c7a58b54
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These changes have no effect if CONFIG_GCOV_KERNEL is not set in
defconfig. It is easier to trigger GCOV for kernel if this patch
is in by only setting the before mentioned flag.
Change-Id: I8aade309da2da62c4b3889bd84e4123ba8f182da
Signed-off-by: Juha Tukkinen <jtukkinen@nvidia.com>
Reviewed-on: http://git-master/r/62999
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Rebase-Id: R4c238f707f1db600f188ae83426336753992b7be
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Change-Id: If544ad6382b8321f8c5e94e0a8a7679d36c48b67
Reviewed-on: http://git-master/r/52239
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Amlan Kundu <akundu@nvidia.com>
Reviewed-on: http://git-master/r/62044
Reviewed-by: Manoj Chourasia <mchourasia@nvidia.com>
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>
Rebase-Id: Rc0e69778b981cba9a5dfd1b55ece16d5f43cf22e
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The clock control apis can be sleepable in tegra platform as
spi require frequency/voltage boosting.
Moving the clock controls api out of spin lock context.
bug 874841
Reviewed-on: http://git-master/r/56869
(cherry picked from commit b316a4e4fd82f1af9af920079119c56bf271c3be)
Change-Id: I8fc824de02cb3af54f6331efa0500c79e806bb03
Reviewed-on: http://git-master/r/57315
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R601bd69547ec2612f42d24da29a2f8a5d3fb1fb8
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Avoiding the suspend of the system if the spi transfer is
in progress for current transfer queue.
bug 864987
Reviewed-on: http://git-master/r/56599
(cherry picked from commit 0ba8ed371f2937a095752a0edbc15ed75664644a)
Change-Id: Ife7ae8a7d66a66d047ee2c8829d16017571b4d58
Reviewed-on: http://git-master/r/57001
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Rebase-Id: Rc66d6c7ae51ea6709d5e47331fef30c87029b343
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Exporting with GPL flag of the api spi_tegra_register_callback()
for registering for callback.
Original-Change-Id: Ic3cbbca226071002824f1b6089dc2ccec796cc07
Reviewed-on: http://git-master/r/49663
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Rebase-Id: R0c7ce298c123e380398c512effe0b6b20685fdd9
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Providing the different clock source option through platform data
to select best clock source based on required interface frequency.
bug 851642
Original-Change-Id: I18bf817b63cf1afac7db3969f266cc5fcaeee81e
Reviewed-on: http://git-master/r/41226
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Rebase-Id: Ra4e4573414ef2c4e72cdcb4cd5625e242cfb4ec6
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- Initialized the read_words value.
- (tspi->irq < 0) is not valid
because tspi->irq is unsigned value.
Reviewed-on: http://git-master/r/37868
(cherry picked from commit 4c0d22c83294ca081e90f588fdcb67fdc54fff23)
Original-Change-Id: Ic37df9d29e305699abeda1f8b8aa48b7fcd9b394
Reviewed-on: http://git-master/r/39583
Tested-by: Jubeom Kim <jubeomk@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: R8e088031295c334cf3026ee8a49738605b7fcf7f
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Change SOC conditionals to make them more forward-looking.
Original-Change-Id: Ib60db4e690c2f396afdec962616d735548b5a8a9
Reviewed-on: http://git-master/r/32706
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
Rebase-Id: Ra0885f203904e0bd4bdd06c23b6aa7e03e7ec3bc
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By changing the dma allocation API to take the client name, it is easy
to track who is allocated the DMA channels when we run out of the
DMA channels.
Original-Change-Id: I016011cfd74089fed0da1bc0f121800017ce124a
Reviewed-on: http://git-master/r/28031
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Original-Change-Id: I048bcb87f95ee6d8ad2fdce993a1758dc5071666
Rebase-Id: R29b9645ecbe209f571018c6e707bfdd9cd65ad5d
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When spi device calls the setup, the interface to that device
should be configured immediately. For this, it is required
to configure controller in setup call.
Original-Change-Id: I77795c476729fe7403529a45cdf99d5732ad0784
Reviewed-on: http://git-master/r/27607
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
Original-Change-Id: I9a3f200dbea7d8cc057bb5413e790c28578e77cf
Rebase-Id: R7e9907797bf951a9f7b9b6db0a440b3796dc977c
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Adding spi slave driver for tegra socs.
The interface is same as the master spi but spi controller
will work in slave mode.
Original-Change-Id: Ibf00e9d16e7bac675dd431a35e866bf56030f033
Reviewed-on: http://git-master/r/27605
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Ramachandrudu Kandhala <rkandhala@nvidia.com>
Original-Change-Id: I1d770ae52371bae5869b03c69f86c06fb9cdc9fa
Rebase-Id: R6d1726c2b899437eed4dd8681403ed0f63f53265
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Original-Change-Id: I158d2be97c795313e7e74ce9fb4ec0bdc7d95496
Reviewed-on: http://git-master/r/27559
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Hiro Sugawara <hsugawara@nvidia.com>
Reviewed-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I0ff198daa548ed2837f7fb1794013bf0adf7e5a1
Rebase-Id: R61892d66dc9efd02f691a3ac75f92dd5d6d17078
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Supporting the hw based CS to communicate to spi device. This
provides the constraints in hold and setup time of CS before
clock start and clock ends.
The hw based CS can be selected if spi client provide the option
through the device controler data and only one transfer per
message is requested.
Original-Change-Id: I56d5e466361cb8b3710646e01494ddac46791ae4
Reviewed-on: http://git-master/r/23988
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Amit Kamath <akamath@nvidia.com>
Reviewed-by: Ramachandrudu Kandhala <rkandhala@nvidia.com>
Original-Change-Id: I52b1dcdefa199cd11ae7f838c61411a6268a2d32
Rebase-Id: Rd9f2c70e8c8551ea5ca6ce698a172ef00c08ca67
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Following are the fixes;
- Supportng half duplex.
- Only using SW based CS.
- Write to readback with command register does not work. Fixing issue.
- Using cpu based transfer for smaller size and dma based for larger size.
- reading proper transfer status after every transaction.
bug 791149
bug 791780
Original-Change-Id: I293b3f1b571276f5d8fe4ad4da67f827926e4b73
Reviewed-on: http://git-master/r/20581
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Amit Kamath <akamath@nvidia.com>
Rebase-Id: R29f88f7509bdb182f05916ecf31e1090b1b9d017
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disable unstable packed spi mode
Original-Change-Id: I81a11a0f5dd9515ff1430ccfcc7d2ed7371e79b3
Reviewed-on: http://git-master/r/16105
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R010fbce5f63a377fa9661f3bdd89523c497989ec
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Enabled clocks at spi_setup
Fixed problem with endianness for 16 bit word size
Fixed issue with small packet size less than fifo depth
Fixed typo that enabled RX and TX by default
Integration from http://git-master/r/#change,14536
Original-Change-Id: I2cea3bdcb6a19780087671131a848095354105a3
Reviewed-on: http://git-master/r/15949
Reviewed-on: http://git-master/r/16048
Reviewed-by: Amit Kamath <akamath@nvidia.com>
Tested-by: Amit Kamath <akamath@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: Ra7c9c381f2ae897d002853c9965252ba28dc28ac
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- DMA burst size can be set to 1, 4, or 8 depending on requested size
- PACKED MODE support
- When bits per word is 32, no endian conversion is needed; so use
memcpy to copy from client buf to dma buf or vice versa
- Do spi_complete operation in the last dma complete callback
- Reducing the loop-count from 500 to 50, thus making sure suspend is
not stuck.
bug 747979
bug 765062
Original-Change-Id: I67fe1405e1cda886e9229b26dff5ebd80fd67247
Reviewed-on: http://git-master/r/12799
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: R34ee80275312587666359ed2e0e8dab468068daf
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for spi/slink, depending on transfer size,
burst size can be set to 1, 4, or 8.
bug 747979
Original-Change-Id: Ieae0285d374e7d0eb6c2c2e633f8cafbb2b51b3a
Reviewed-on: http://git-master/r/12076
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: R366881cc8a4ba50cdd815b97f52b4e7d4dfb1ee6
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for spi/slink, set dma burst size based on
transfer size.
bug 747979
Original-Change-Id: I8c3c0a0410648a25190847590b9ac0304fb1105f
Reviewed-on: http://git-master/r/11752
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: R63f68e541c427778a412c5f09e656fb18da5f05d
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To avoid running out of DMA channels, use the shared DMA channel
for all four Tegra spi controllers.
Change-Id: Iff644253cf7fae36aa2e42321a1ded35a728da4f
Signed-off-by: Colin Cross <ccross@android.com>
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Some SPI devices require a delay between the CS and when the clock
starts. Increase SS_SETUP to accommodate these devices.
Change-Id: I301e3583e70c722cadde5a9f91119881805dd3a5
Signed-off-by: Greg Meiste <w30289@motorola.com>
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Save/restore SLINK_COMMAND_0 register.
Wait for in-progress transactions to complete before suspend.
Reject and WARN_ON transactions when suspended.
Change-Id: I0527781f0bf95781afa3a35a68282cde2f0189ae
Signed-off-by: Todd Poynor <toddpoynor@google.com>
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commit 1458d160de3f1862aeaac57447ba96e7857ac52b upstream.
Currently there is a request_mem_region(r->start, ..
followed by r->start += pdata->regs_offset;
And then in remove
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
release_mem_region(r->start, resource_size(r));
Here the offset addition is not taken care. Fix the code for the
same.
Signed-off-by: Shubhrajyoti D <shubhrajyoti@ti.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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We found that adding load, Rx data sometimes drops.(with DMA transfer mode)
The cause is that before starting Rx-DMA processing, Tx-DMA processing starts.
This causes FIFO overrun occurs.
This patch fixes the issue by modifying FIFO tx-threshold and DMA descriptor
size like below.
Current this patch
Rx-descriptor 4Byte+12Byte*341 --> 12Byte*340-4Byte-12Byte
Rx-threshold (Not modified)
Tx-descriptor 4Byte+12Byte*341 --> 16Byte-12Byte*340
Rx-threshold 12Byte --> 2Byte
Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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Add recovery processing in case FIFO overrun error occurs with DMA transfer mode.
Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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We found Rx data sometimes drops.(with non-DMA transfer mode)
The cause is read complete condition is not true.
This patch fixes the issue.
Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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During processing 1 command/data series,
SSN should keep LOW.
However, currently, SSN becomes HIGH.
This patch fixes the issue.
Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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Currently, in case of reading date from SPI flash,
command is sent twice.
The cause is that tx-memory clear processing is missing .
This patch adds the tx-momory clear processing.
Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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If CPM mode is not used, the fsl_dummy_rx variable is never allocated. When
the cleanup attempts to free it, the reference count is zero and a WARN is
generated. The same CPM mode check used in the initialize is applied to the
free as well.
Tested on 2.6.33 with the previous spi_mpc8xxx driver. The renamed
spi-fsl-spi driver looks to have the same problem.
Signed-off-by: Jeff Harris <jeff_harris@kentrox.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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commit 22a85e4cd51 (spi/imx: add device tree probe support) broke spi-imx usage
when the SPI chipselect is the one internal to the controller.
On a mx31pdk board the following error is seen:
Registering mxc_nand as whole device
------------[ cut here ]------------
WARNING: at drivers/gpio/gpiolib.c:101 gpio_ensure_requested+0x4c/0xf4()
autorequest GPIO-0
Modules linked in:
[<c0014410>] (unwind_backtrace+0x0/0xf4) from [<c0025754>] (warn_slowpath_common+0x4c/0x64)
[<c0025754>] (warn_slowpath_common+0x4c/0x64) from [<c0025800>] (warn_slowpath_fmt+0x30/0x40)
[<c0025800>] (warn_slowpath_fmt+0x30/0x40) from [<c0198688>] (gpio_ensure_requested+0x4c/0xf4)
[<c0198688>] (gpio_ensure_requested+0x4c/0xf4) from [<c01988c8>] (gpio_direction_output+0xa0/0x138)
[<c01988c8>] (gpio_direction_output+0xa0/0x138) from [<c01ed198>] (spi_imx_setup+0x38/0x4c)
[<c01ed198>] (spi_imx_setup+0x38/0x4c) from [<c01eb5d0>] (spi_setup+0x38/0x50)
[<c01eb5d0>] (spi_setup+0x38/0x50) from [<c01eb85c>] (spi_add_device+0x94/0x124)
[<c01eb85c>] (spi_add_device+0x94/0x124) from [<c01eb960>] (spi_new_device+0x74/0xac)
[<c01eb960>] (spi_new_device+0x74/0xac) from [<c01eb9b8>] (spi_match_master_to_boardinfo+0x20/0x40)
[<c01eb9b8>] (spi_match_master_to_boardinfo+0x20/0x40) from [<c01eba88>] (spi_register_master+0xb0/0x104)
[<c01eba88>] (spi_register_master+0xb0/0x104) from [<c01ec0b4>] (spi_bitbang_start+0x104/0x17c)
[<c01ec0b4>] (spi_bitbang_start+0x104/0x17c) from [<c02c2c4c>] (spi_imx_probe+0x2fc/0x404)
[<c02c2c4c>] (spi_imx_probe+0x2fc/0x404) from [<c01c2498>] (platform_drv_probe+0x18/0x1c)
[<c01c2498>] (platform_drv_probe+0x18/0x1c) from [<c01c1058>] (driver_probe_device+0x78/0x174)
[<c01c1058>] (driver_probe_device+0x78/0x174) from [<c01c11e0>] (__driver_attach+0x8c/0x90)
[<c01c11e0>] (__driver_attach+0x8c/0x90) from [<c01c0860>] (bus_for_each_dev+0x60/0x8c)
[<c01c0860>] (bus_for_each_dev+0x60/0x8c) from [<c01c0088>] (bus_add_driver+0xa0/0x288)
[<c01c0088>] (bus_add_driver+0xa0/0x288) from [<c01c179c>] (driver_register+0x78/0x18c)
[<c01c179c>] (driver_register+0x78/0x18c) from [<c0008490>] (do_one_initcall+0x34/0x178)
[<c0008490>] (do_one_initcall+0x34/0x178) from [<c03a5204>] (kernel_init+0x74/0x118)
[<c03a5204>] (kernel_init+0x74/0x118) from [<c000f65c>] (kernel_thread_exit+0x0/0x8)
---[ end trace 759f924b30fd5a44 ]---
Fix this issue by using the original chip select logic and make spi-imx to work again.
Tested on a mx31pdk that uses the hardware SPI chipselect pins and also
on a mx27pdk that uses GPIO as SPI chipselect.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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The remove function in the PL022 driver cannot abort the remove
function any way, so restructure the code so as not to make that
assumption. Remove will now proceed no matter whether it can
stop the transfer queue or not.
Reported-by: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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* 'spi/next' of git://git.secretlab.ca/git/linux-2.6: (34 commits)
spi/imx: add device tree probe support
spi/imx: copy gpio number passed by platform data into driver private data
spi/imx: use soc name in spi device type naming scheme
spi/imx: merge type SPI_IMX_VER_0_7 into SPI_IMX_VER_0_4
spi/imx: do not use spi_imx2_3 to name SPI_IMX_VER_2_3 function and macro
spi/imx: use mx21 to name SPI_IMX_VER_0_0 function and macro
spi/imx: do not make copy of spi_imx_devtype_data
spi/dw: Add spi number into spi irq desc
spi/tegra: Use engineering names in DT compatible property
spi/fsl_spi: fix CPM spi driver
mach-s3c2410: remove unused spi-gpio.h file
spi: remove obsolete spi-s3c24xx-gpio driver
mach-gta2: remove unused spi-gpio.h include
mach-qt2410: convert to spi_gpio
mach-jive: convert to spi_gpio
spi/pxa2xx: Remove unavailable ssp_type from documentation
spi/bfin_spi: uninline fat queue funcs
spi/bfin_spi: constify pin array
spi/bfin_spi: use structs for accessing hardware regs
spi/topcliff-pch: Support new device ML7223 IOH
...
Fix up trivial conflict in arch/arm/mach-ep93xx/Makefile
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It adds device tree probe support for spi-imx driver.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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It copies gpio number passed via platform data embedded pointer into
driver private data, so that we do not need to refer to this embedded
pointer passed by platform data after probe function exits.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Cc: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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Software defined version number is not stable enough to be used
in device type naming scheme. The patch changes it to use implicit
soc name for spi device type definition. In this way, we can easily
align the naming scheme with device tree binding, which comes later.
It removes fifosize from spi_imx_data and adds devtype there, so that
fifosize can be set in an inline function according to devtype.
Also, cpu_is_mx can be replaced by inline functions checking devtype.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Cc: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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The only difference between SPI_IMX_VER_0_7 and SPI_IMX_VER_0_4 is
.config function. The patch uses cpu_is_mx35 (to be removed) as the
temporary solution to consolidate functions spi_imx0_4_config and
spi_imx0_7_config into mx31_config. As a result, type SPI_IMX_VER_0_7
can be merged into SPI_IMX_VER_0_4.
It also renames function spi_imx0_4_reset to mx31_reset to keep
consistency with other function naming.
A couple of redundant macros, MX3_CSPISTAT and MX3_CSPISTAT_RR,
together with the useless type SPI_IMX_VER_0_5 also get cleaned up.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Cc: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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It's confusing to use spi_imx2_3 to name SPI_IMX_VER_2_3 function
and macro, as it easily make people think of imx2 and imx3. It's
better to use specific soc name just like what other SPI_IMX_VER
do. For SPI_IMX_VER_2_3 case, it will be mx51. To distinguish it
from CSPI on mx51, mx51_ecspi might be a good choice.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Cc: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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SPI_IMX_VER_0_0 covers i.mx21 and i.mx27. It makes more sense to
use mx21 rather than mx27 to name SPI_IMX_VER_0_0 function and
macro, since i.mx21 comes out ealier than i.mx27.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Cc: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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