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path: root/drivers/spi
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2017-11-29Merge tag 'tegra-l4t-r21.6' into toradex_tk1_l4t_r21.6Marcel Ziswiler
Merge NVIDIA's latest Linux for Tegra aka L4T R21.6 Linux kernel changes from git://nv-tegra.nvidia.com/linux-3.10.git commit: b271e8fa67a6d9c4600274a25636cfe00fdd1b68 Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Dominik Sliwa <dominik.sliwa@toradex.com>
2017-11-29Revert "spi-tegra114: Warning when clock rate switch fails"Marcel Ziswiler
This reverts commit 8fdf8dc5afdb02625084356ebd7c0d1c7494a00e. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Dominik Sliwa <dominik.sliwa@toradex.com>
2017-09-20spi: tegra: fix warning when using controller-dataDominik Sliwa
Tegra spi driver was using devm_kzalloc before dev was bound. Signed-off-by: Dominik Sliwa <dominik.sliwa@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2016-09-29spi-tegra114: Warning when clock rate switch failsDominik Sliwa
When setting transfer clock rate out of bounds old clock rate was used without any notice. Signed-off-by: Dominik Sliwa <dominik.sliwa@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2016-08-24spi: tegra: support polling modeKrishna Yarlagadda
Added support to use polling mode instead of interrupts through a property in dt Bug 1679083 Change-Id: Ic82ab592822cc96bacda05124d38ddd913e09af9 Reviewed-on: http://git-master/r/840233 (cherry picked from commit cd1c4db5adc8317572106099da37fa434245e699) Reviewed-on: http://git-master/r/1009988 (cherry picked from commit b29ce03a6b7ebb306ff157640470dd5ab99c6f6b) Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com> Reviewed-on: http://git-master/r/1175213 Reviewed-by: Matthew Pedro <mapedro@nvidia.com> Tested-by: Matthew Pedro <mapedro@nvidia.com>
2016-08-24spi: tegra: Reduce register accessKrishna Yarlagadda
Reduce register accesses to SPI as it is dependent on slow, variable SPI clock frequency. Bug 1675619 Change-Id: I5d638b8f95d9207fbad1e30e21234fc7433e03b3 Reviewed-on: http://git-master/r/1009503 (cherry picked from commit 890a422a7b75507c33b53f1ca4c512f7911d61c4) Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com> Reviewed-on: http://git-master/r/1174582 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2016-08-24spi: tegra: option to boost register accessKrishna Yarlagadda
SPI register access for T210 and earlier chips depend on SPI clock frequency. Provided an option to set SPI clock at max frequency for register access. Bug 1675625 Change-Id: Ie52c83cd4602604822462d9f02ddf31ead83aafc Reviewed-on: http://git-master/r/1009782 (cherry picked from commit a2ccd28f2850538064668568432fee5d70a22e82) Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com> Reviewed-on: http://git-master/r/1174581 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2014-06-18spi: tegra114: Move IST work to caller threadShardar Shariff Md
Remove IST(interrupt service thread) and move that functionality to caller thread Bug 1501764 Change-Id: Id310c75939be62a5121f2b2f68f14a146256b4aa Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com> Reviewed-on: http://git-master/r/399627 (cherry picked from commit f6366d4f846425bbfa0d8e919a974eff7429862f) Reviewed-on: http://git-master/r/424075 GVS: Gerrit_Virtual_Submit Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2014-06-05Merge branch 'linux-3.10.40' into rel-21Ishan Mittal
Bug 200004122 Conflicts: drivers/cpufreq/cpufreq.c drivers/regulator/core.c sound/soc/codecs/max98090.c Change-Id: I9418a05ad5c56b2e902249218bac2fa594d99f56 Signed-off-by: Ishan Mittal <imittal@nvidia.com>
2014-04-07spi: tegra: convert to standard DMA DT bindingsChaitanya Bandi
By using dma_request_slave_channel_or_err(), the DMA slave ID can be looked up from standard DT properties, and squirrelled away during channel allocation. Hence, there's no need to use a custom DT property to store the slave ID. Change-Id: Id75c29442d39a7252eb591235a5b44511957afb7 Acked-by: Mark Brown <broonie@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Chaitanya Bandi <bandik@nvidia.com> Reviewed-on: http://git-master/r/389699 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2014-03-27arm: tegra: vcm30t124: [2/3] spidev board supportYousuf A
Bug 1454650 Enabling registration of spi1/2/3/5 in vcm30t124. Change-Id: I42f1709e8551a4867864ace4b0bf576c9847d135 Signed-off-by: Yousuf A <yousufa@nvidia.com> Reviewed-on: http://git-master/r/386683 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Sandeep Trasi <strasi@nvidia.com> Tested-by: Sandeep Trasi <strasi@nvidia.com>
2014-03-27arm: tegra: vcm30t124: [3/3] spidev board supportYousuf A
Bug 1454650 Enabling registration of spi1/2/3/5 in vcm30t124. Change-Id: I579d36c0ae8203cc1e2119073718ecf206423fec Signed-off-by: Yousuf A <yousufa@nvidia.com> Reviewed-on: http://git-master/r/386682 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com> Reviewed-by: Sandeep Trasi <strasi@nvidia.com>
2014-03-23spi: spi-ath79: fix initial GPIO CS line setupGabor Juhos
commit 61d1cf163c8653934cc8cd5d0b2a562d0990c265 upstream. The 'ath79_spi_setup_cs' function initializes the chip select line of a given SPI device in order to make sure that the device is inactive. If the SPI_CS_HIGH bit is set for a given device, it means that the CS line of that device is active HIGH so it must be set to LOW initially. In case of GPIO CS lines, the 'ath79_spi_setup_cs' function does the opposite of that due to the wrong GPIO flags. Fix the code to use the correct GPIO flags. Reported-by: Ronald Wahl <ronald.wahl@raritan.com> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-03-13Merge branch 'linux-3.10.33' into dev-kernel-3.10Deepak Nibade
Bug 1456092 Change-Id: I3021247ec68a3c2dddd9e98cde13d70a45191d53 Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
2014-02-24arm: tegra: spi:Increase transfer timeout to 10secShardar Shariff Md
Increasing transfer timeout from 1sec to 10sec as timeout issue is happening during stress tests sporadically, this timeout is root caused due to delay in SPI ISR thread switch. Bug 1451201 Change-Id: I1b500590875548b618139855cce8a9f4dcdac186 Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com> Reviewed-on: http://git-master/r/372903 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2014-02-22spi: Fix crash with double message finalisation on error handlingGeert Uytterhoeven
commit 1f802f8249a0da536877842c43c7204064c4de8b upstream. This reverts commit e120cc0dcf2880a4c5c0a6cb27b655600a1cfa1d. It causes a NULL pointer dereference with drivers using the generic spi_transfer_one_message(), which always calls spi_finalize_current_message(), which zeroes master->cur_msg. Drivers implementing transfer_one_message() theirselves must always call spi_finalize_current_message(), even if the transfer failed: * @transfer_one_message: the subsystem calls the driver to transfer a single * message while queuing transfers that arrive in the meantime. When the * driver is finished with this message, it must call * spi_finalize_current_message() so the subsystem can issue the next * transfer Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org> Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-02-13spidev: fix hang when transfer_one_message failsDaniel Santos
commit e120cc0dcf2880a4c5c0a6cb27b655600a1cfa1d upstream. This corrects a problem in spi_pump_messages() that leads to an spi message hanging forever when a call to transfer_one_message() fails. This failure occurs in my MCP2210 driver when the cs_change bit is set on the last transfer in a message, an operation which the hardware does not support. Rationale Since the transfer_one_message() returns an int, we must presume that it may fail. If transfer_one_message() should never fail, it should return void. Thus, calls to transfer_one_message() should properly manage a failure. Fixes: ffbbdd21329f3 (spi: create a message queueing infrastructure) Signed-off-by: Daniel Santos <daniel.santos@pobox.com> Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-02-13spi/bcm63xx: don't substract prepend length from total lengthJonas Gorski
commit 86b3bde003e6bf60ccb9c09b4115b8a2f533974c upstream. The spi command must include the full message length including any prepended writes, else transfers larger than 256 bytes will be incomplete. Signed-off-by: Jonas Gorski <jogo@openwrt.org> Acked-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-01-30arm: tegra: spi: Clear status variablesShardar Shariff Md
- Clear tx_status, rx_status variable for every transfer - Add log to check for any spurious interrutps Bug 1445171 Change-Id: I48d7003ad0aa69b1d9275cddd1b060941489d556 Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com> Reviewed-on: http://git-master/r/361401 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2014-01-28arm: tegra: spi: terminate dma during timeoutShardar Shariff Md
Terminate the dma when spi transaction times out. Bug 1445171 Change-Id: If29c049ba37dcee9e5e1af213c47a0356f890961 Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com> Reviewed-on: http://git-master/r/360419 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
2014-01-28arm: tegra: spi: Use PIO_EN to start PIO transferShardar Shariff Md
Use PIO_EN bit to start the cpu based transfer instead of DMA_EN bit Bug 1445171 Change-Id: I7b28aa2066a71c4ffe02d0e61714e04cc54b03b5 Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com> Reviewed-on: http://git-master/r/360795 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2014-01-19arm: tegra: spi: Enable LE_BTYE formatShardar Shariff Md
By default enable Little Endian byte format Change-Id: I1fb3cc363aa708c34a5af3fe47b94ccf17590d40 Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com> Reviewed-on: http://git-master/r/351201 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
2014-01-19arm: tegra: spi: get ctrl data from child node.Shardar Shariff Md
Get the controller data from child node (controller-data) of spi client node. spi client dt node should provide cdata entries as below. Ex: <spi-client>@<bus_num> { ... controller-data { nvidia,enable-hw-based-cs; nvidia,cs-setup-clk-count = <10>; nvidia,cs-hold-clk-count = <10>; nvidia,rx-clk-tap-delay = <0>; nvidia,tx-clk-tap-delay = <16>; } ... }; Change-Id: I3fc66d9131ebc70bda60c3d15a0b3fef532bc998 Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com> Reviewed-on: http://git-master/r/356941 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2013-12-27arm: tegra: spi: add controller data dt supportShardar Shariff Md
Add DT support for spi controller data. spi client dt node should add cdata entries as below. Ex: <spi-client>@<bus_num> { ... nvidia,enable-hw-based-cs; nvidia,cs-setup-clk-count = <10>; nvidia,cs-hold-clk-count = <10>; nvidia,rx-clk-tap-delay = <0>; nvidia,tx-clk-tap-delay = <16>; ... }; Bug 1422369 Change-Id: I8255643ef00fed486baf707edbf77b1b91586579 Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com> Reviewed-on: http://git-master/r/345354 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2013-10-31spi: tegra114: fix typosEdgardo Handal
Change-Id: Iaa3ecbf4877de835c8ca6b6b11948f4ad4772b5a Signed-off-by: Edgardo Handal <ehandal@nvidia.com> Reviewed-on: http://git-master/r/302956 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
2013-10-30arm: tegra: spi: Add tegra_spi_cs_low callbackShardar Shariff Md
added tegra_spi_cs_low() callback, called from spi core for spi client users to set chip select state(low/high). Bug 1371286 Change-Id: Ifea4282a46f88c1744c44e6fd6dee7d98d72bc05 Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com> Reviewed-on: http://git-master/r/303904 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2013-10-30spi: Add spi_cs_low() callbackShardar Shariff Md
spi_cs_low() callback is added for spi client users to set chip select state(low/high). prototype: int spi_cs_low(struct spi_device *spi, bool state); Bug 1371286 Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com> Change-Id: I4b2374202267338246262d902d6492d35dc755fb Reviewed-on: http://git-master/r/303902 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2013-10-21arm: t124: spi: Fix in setting RX_TAP_DELAYShardar Shariff Md
RX_TAP_DELAY should be set even if controller data(cdata) as tap delay should be set depending on speed Change-Id: Ia584be5c6bfd1e71166b4241ff127c22e1a7aeaf Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com> Reviewed-on: http://git-master/r/301756 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2013-09-16arm: tegra12: spi: Set RX_TAP_DELAY depending on speedShardar Shariff Md
Set rx_tap_delay to 10 when speed > 35MHz and board specific rx_clk_tap_delay data is zero. Bug 1245131 Change-Id: Ie38469dac8d80737da5e45b9022ef1276b7fc883 Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com> Reviewed-on: http://git-master/r/273189 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2013-09-16arm: tegra: spi: fix rx_tap_delayShardar Shariff Md
Instead on using rx_tap_delay value, tx_tap_delay value is passed to SPI_RX_TAP_DELAY macro resulting in undesired value in command2 reg. Change-Id: I4592e98b240a7d23a81507bddf80e81008f73a7d Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com> Reviewed-on: http://git-master/r/271475 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2013-09-14ARM: tegra: Use <linux/clk/tegra.h> instead of <mach/clk.h>Dan Willemsen
So that the upstream common clk infrastructure can live side by side. Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Change-Id: I0fe0ef8cd207d27b707821eed838c75b8ec04025
2013-09-14arm: tegra: spi: cleanup: remove old spi tegra11 driverShardar Shariff Md
Removing old spi_tegra11.c driver and its instances Change-Id: Id2302c484eeb780ae481e1edc9a25234a4fd77f2 Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com> Reviewed-on: http://git-master/r/251189 Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com> Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>
2013-09-14fixup! spi: Tegra11: Port all fixes from t30 to tegra11Dan Willemsen
2013-09-14SPI: tegra114: rename clock_always_onDan Willemsen
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
2013-09-14spi: tegra11: Update debug printVijay Mali
dev_info -> dev_dbg Reviewed-on: http://git-master/r/199996 (cherry picked from commit 74d60d171164695d7bff372247bc2e2d4591ac02) Change-Id: Ib5b57f09333810aab3dff1e6328b096a331d0722 Signed-off-by: Vijay Mali <vmali@nvidia.com> Reviewed-on: http://git-master/r/214804 Reviewed-by: Scott Peterson <speterson@nvidia.com>
2013-09-14gcov-kernel: Add GCOV_KERNEL := y to MakefilesJuha Tukkinen
These changes have no effect if CONFIG_GCOV_KERNEL is not set in defconfig. It is easier to trigger GCOV for kernel if this patch is in by only setting the before mentioned flag. Change-Id: I8aade309da2da62c4b3889bd84e4123ba8f182da Signed-off-by: Juha Tukkinen <jtukkinen@nvidia.com> Reviewed-on: http://git-master/r/62999 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Rebase-Id: R4c238f707f1db600f188ae83426336753992b7be
2013-09-14spi: tegra114: add spi driverLaxman Dewangan
Add spi driver for NVIDIA's Tegra114 spi controller. This controller is different than the older SoCs spi controller and there is a change in register interface also. This driver supports the: - non DMA based transfer for smaller transfer i.e. less than FIFO depth. - APB DMA based transfer for lager transfer i.e. more than FIFO depth. - Runtime PM for clock gating. - registration through DT and platform board files. Change-Id: I30ab59a29d80b191843878994227945261ae8e17 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/202032 Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com> Tested-by: Nitin Kumbhar <nkumbhar@nvidia.com> (cherry picked from commit 8b21af40fc68e280a1e7f0168928d1b97b61b6ba)
2013-09-14spi: tegra11: moving to clk prepare APIsSivaram Nair
The clk_enable/clk_disable pair of APIs are replaced with clk_prepare_enable and clk_disable_unprepare. This is needed for the migration to common clk framework. Bug 920915 Change-Id: Ieb05e10b35c6271c05f31a2651b7713b4722e236 Signed-off-by: Sivaram Nair <sivaramn@nvidia.com> Reviewed-on: http://git-master/r/172214 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2013-09-14spi: tegra: Fix uninitialized variableKunal Agrawal
The function spi_tegra_resume has uninitialized variable "spi". Initialized it to NULL to prevent build failure. Bug 1179578 Change-Id: Iaf7b82438e473ca0a8792ce55571ce4baf1ef5fe Signed-off-by: Kunal Agrawal <kunala@nvidia.com> Reviewed-on: http://git-master/r/165857 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2013-09-14spi: tegra11: Set MODE bits before setting CS bitKunal Agrawal
Implemented change to set the MODE bits first and then set CS and other bits of the command register. Bug 1168218 Change-Id: I87bd94b8fac5821f11e575e53ee5694d6cad6d2c Signed-off-by: Kunal Agrawal <kunala@nvidia.com> Reviewed-on: http://git-master/r/161184 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2013-09-14spi: tegra11: add NULL checkSri Krishna chowdary
fix coverity issue. Add Null check before dereferencing t->tx_buf and tspi->cur. Bug 1046331 Change-Id: I2ff53b1945b4ee9a0d87e23816df7f2a3f1464fe Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com> Reviewed-on: http://git-master/r/159542 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com> Rebase-Id: Rdfdd30e776c7196b41e28943b22d6a9b19a9d4b1
2013-09-14spi: tegra11: set value of SPI FIFO depthKunal Agrawal
The value of SPI FIFO depth has been now set to 64. Change-Id: I9c1ab1bddc4635d4ec1696f5763a5822d688ad71 Signed-off-by: Kunal Agrawal <kunala@nvidia.com> Reviewed-on: http://git-master/r/146822 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Rebase-Id: Rd3e4390529d444caf36124a7e5b0b08e0da2656b
2013-09-14spi: tegra11: add support for HW based CSLaxman Dewangan
Add support for HW based CS and add configuration for CS setup time and hold time. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/140617 (cherry picked from commit 90dcafb1414c8e3cb53bbdf518758210aa73f21b) Change-Id: If746f74145d3cd0804bb8dccdd8f1d0e3c2ebf3b Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/143270 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: R6cb1f9dbba6d78ca2cf4bc1917a1dad4b3b8b8ab
2013-09-14spi: tegra11: support for rx/tx clock tap delayLaxman Dewangan
The spi tegra11 have the configuration for rx and tx clock tap delay which need to be configure based on the spi interface speed. It also depends on the platform on which it is running. Addign support for configuring this parameter through platform file. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/140615 (cherry picked from commit b7742640eb264677a47f9944b7711ddbf07bd723) Change-Id: I4caa2a8405d56f9d85622f540fe6b36e49c2bf39 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/143269 GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: R26ddc25bd03148f6d366f1e2e336eb91f40d619f
2013-09-14spi: tegra11: setclock source based on the speedLaxman Dewangan
Change the clock source to reach the speed based on minimum power and nearest require speed. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/139733 (cherry picked from commit 28102ea1efe53fabf033a3ef31797923c2fed77c) Change-Id: I4150e97fdccb140fbf5b401a68d2ca4e9802e1ac Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/143268 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: R28b87a14a2c9ff8a5b94b2cc438f3a4dc16982f5
2013-09-14spi: tegra11: make sure SCLK is enable during transferLaxman Dewangan
Make sure that SCLK is enabled when spi trasnfer is in progress. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/139732 (cherry picked from commit 4be79e0c084fb7b01a95fccb8d2144b7b9fc16d0) Change-Id: Ie9f7d398c776d4b9d9e7cfb91bc0eec054183ce4 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/143267 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: R4e02d8fde5de9d45299afc41e7eda55e0ed44151
2013-09-14spi: tegra: fix dma based transfer issueKunal Agrawal
Tegra11 spi controller not require the Tx fifo to be fill before enabling dma. Removing this checks. Signed-off-by: Kunal Agrawal <kunala@nvidia.com> Reviewed-on: http://git-master/r/135160 (cherry picked from commit c9f0787bd10a9dc17eeb6587a67493e0d042160a) Change-Id: I366c191b9db6d713389307a1bc9904b2d8b0b064 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/143266 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: Re0d82749b714584d6ee14c567d37d91379dd133b
2013-09-14spi: tegra11: Set speed as per client requestLaxman Dewangan
The speed was set for 12M. Now removing this fixed speed and configuring based on client request. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/135047 (cherry picked from commit d4b2de17c941d10c7d1297646c766bd261f82d0f) Change-Id: I4977a85a0f0a7a9378406458b94f5d7d6f75e271 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/143265 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: Re7d5face4e1023f4493a45b05aacbbda53aa8b9f
2013-09-14spi: tegra: Handle active high CS.Laxman Dewangan
Handling active HIGH CS propery as: - Low in idle state. - High during transfer. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/134883 (cherry picked from commit 8a52f4b515e46f839bc4520c77db83b26cd6a7ca) Change-Id: Ic90825031415f434bf5ebaf4c6d0aea4c3e932a2 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/143264 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: R16b990c93ad0ed51cb2302509142209bf6115444
2013-09-14spi: Tegra11: Port all fixes from t30 to tegra11Laxman Dewangan
Fix multiple issue in tegra11 driver which includes: - Half duplex support. - Proper selecting CS. - Port fixes from T30 to T114 driver. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/134607 Change-Id: Ica26924ebbf11c11307fc73ec3f8b2f607b2ff4a Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/143263 GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: R3b4b9247edeb98b7618efa22f0bf535ec0719402
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-15 06:33:08 +0000