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path: root/drivers/video/tegra/dc/dc.c
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2011-11-30video: tegra: dc: disable windows on dc disableJon Mayo
When disabling a display, also disable its windows. This forces applications to resend windows on hotplug and resume or they will see a blank screen. Bug 871107 Reviewed-on: http://git-master/r/50204 (cherry picked from commit 969fe6f1a6b5e28cf6de75937fd100c73e6a99b4) Change-Id: I7c1fc3f45fab3d839794b7955409af8ca04bef2d Reviewed-on: http://git-master/r/56504 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rcea75fc63222079f7db4cae95b4952aaee9a2d0d
2011-11-30video: tegra: dc: add ioctl for setting gamma lutDavid Schalig
Adds ioctl TEGRA_DC_EXT_SET_LUT to dc_ext driver for setting a DC window's color palette. Bug 868060 Change-Id: I57ffcf3a3f91e76efd1c7f1f972b73c2edbaed82 Reviewed-on: http://git-master/r/56392 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Rebase-Id: R712c71151d0c3e3d274279f334bedf312e26e75d
2011-11-30video: tegra: dc: improve underflow statisticsJon Mayo
Collect individual underflow counts for underflow statistics to provide a more accurate number of underflows. Changed stats to use 64-bit numbers due to the larger numbers involved, about 100x from previously. Reviewed-on: http://git-master/r/52940 (cherry picked from commit 1d39d430ad90a027be43323f65eef85a3a30faab) Change-Id: I4d253346dfcb01185a93a7602b7a1c971ea1ebb4 Reviewed-on: http://git-master/r/56301 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rf931d627fedc7ce8d9a37c1c54bb76aa2caf9ff1
2011-11-30video: tegra: provide blank that clears screenJon Mayo
Only clear the display when ioctl FBIOBLANK is FB_BLANK_NORMAL is used This indicates that display should still be powered on and is useful when HDMI audio needs to remain active but no content is displayed on screen. bug 857117 bug 868916 Reviewed-on: http://git-master/r/53608 (cherry picked from commit 234a39002a5a4daa364271ed357de14cff06f6a9) Change-Id: I5a3c3bf5180100e0d1a410bd11ddb60d22562276 Reviewed-on: http://git-master/r/56299 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R349ae85c159dfd3d1be279964d341ba402fc54ca
2011-11-30video: tegra: dc: Enable dc to support simulation interrupt.Chao Xu
Change-Id: Ieb83730f81fb54b56699ebae7d2061d2214af8e7 Reviewed-on: http://git-master/r/54797 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Ref298804f5442b3cba812a7bd4485f825677e7ef
2011-11-30video: tegra: dc: add debug messages to dump window attributesNitin Kumbhar
Various attributes of windows which are currently being updated are displayed with these debug messages. It also adds debug messages to show processes using overlays. (cherry picked from commit 8d64abf98cb3c8a4ffed5f1a903b2d26960933fc) Reviewed-on: http://git-master/r/51979 Change-Id: I5149eb10fb1c7f4f333cd07f0f1c8350bf1e2ed9 Reviewed-on: http://git-master/r/54417 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rc122ff232b3a0b47ede148f65581200ca0135d32
2011-11-30tegra: dc: Workaround a simulator bug.Chao Xu
- Workaround the simulator issue that WIN_x_UPDATE fields are not cleared. Change-Id: I8060a32740e7641eebefe650cee13fd49260df03 Reviewed-on: http://git-master/r/52994 Tested-by: Chao Xu <cxu@nvidia.com> Reviewed-by: Mark Stadler <mastadler@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com> Rebase-Id: R2f813f017b8c009146c1c4a8dac80333a833e3fd
2011-11-30video: tegra: dc: Update dc for simulation.Chao Xu
- Enable interrupt on simulator. - Remove timeout for sync windows event wait. Change-Id: I157ea100d42f4ae0b0f142d024da886b044be7ba Reviewed-on: http://git-master/r/52993 Tested-by: Chao Xu <cxu@nvidia.com> Reviewed-by: Mark Stadler <mastadler@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com> Rebase-Id: R0c166f0dcb6d4ca196ca9e6d4fdfb810588c6871
2011-11-30ARM: tegra: call latency_allowance functions only for siliconYudong Tan
Change-Id: Icc97af53cef2c66cd335d66b960fdb211e5839a2 Reviewed-on: http://git-master/r/52456 Tested-by: Yudong Tan <ytan@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R6a5601582b06e40c0d673c430257faf51ef76d2b
2011-11-30video: tegra: dc: errdiff dithering limited to 1280Jon Mayo
the errdiff dithering mode is limited to 1280 pixels per line. There was some confusion and 640 was used in code and documentation. Bug 803059 Original-Change-Id: Ia802cc5bca72cf55621487f18369278be254de72 Reviewed-on: http://git-master/r/49538 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R07c12fe503cc58942fe81d381d15c0134c2e56d2
2011-11-30video: tegra: dc: Separate allocations for U and VRobert Morell
Currently, dc_ext only takes a single nvmap memory ID per overlay, even in the YUV case (the U and V planes are expected to be differentiated using an offset from the beginning of the nvmap allocation). This is problematic for some software flows, such as certain video interlacing algorithms that will vary the luma plane while keeping the chrome plane constant. This change allows dc_ext clients to specify a different nvmap allocation for each of the Y, U, and V planes. If a YUV surface is used and no U or V plane allocation is specified, the old behavior is preserved: the U and V offsets are assumed to be within the same allocation as Y. Note: this changes the behavior of the offset parameter: the old code added offset to offset_u and offset_v when using it. The new code treats all three offsets as relative to the beginning of the allocation. It also fixes a bug in the code where offset was applied twice to the Y plane. I believe this is safe because the presence of this bug means that no existing clients are using offset != 0 (or if they are, they're already broken). Signed-off-by: Robert Morell <rmorell@nvidia.com> Bug 850882 Original-Change-Id: I230e03db25baaae73a3bdc0d45a2aec162b87fa4 Reviewed-on: http://git-master/r/41471 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Ra6dd17a50de7150edf104d2a6c9b3b9949919022
2011-11-30video: tegra: dc: disable irq on controller enableJon Mayo
Mask interrupts in _tegra_dc_controller_enable before calling enable_irq. Bug 864602 Change-Id: I93e16d4cb5ea01ed8f112acd43132d6407aed82a Reviewed-on: http://git-master/r/50178 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rf1c43274e5bc54b106f7c150a3c839648ea06bd1
2011-11-30video: tegra: dc: use 1/2.1 efficiency factorJon Mayo
Use a 48% efficiency factor when calculating EMC clock. Bug 868860 Original-Change-Id: I469c8120d754210951936b49465b0a2d31fa6825 Reviewed-on: http://git-master/r/49312 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R71260dc9f361ca66c14733b68baaffcee597970d
2011-11-30video: tegra: dc: Fix smartdimmer brightness update issue.Krishna Reddy
When dc is disabled, don't perform smartdimmer brightness update. Accessing dc registers when dc is disabled causes cpu lockup. Bug 866024 Original-Change-Id: Ibe5ef46fe6c3cbc622021c5d6a57c6f4bc11fe78 Reviewed-on: http://git-master/r/49064 Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Tested-by: Krishna Reddy <vdumpa@nvidia.com> Rebase-Id: R5f2f9b3e7aeff39d84b1c3b37e6270cbea8479ed
2011-11-30video: tegra: dc: correct rounding of bandwidth for window BMichael Frydrych
Patch eb81b378 had a sideeffect in that bandwidth of window B may have no longer been rounded up to 1MBs, contrary to original intention. This patch fixes it. Original-Change-Id: Idaba2923e0316245e284e19e1a995adf1bd9cd35 Reviewed-on: http://git-master/r/47133 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Rebase-Id: Rbd6c56777241c2886f714d4de32a642354b69a67
2011-11-30video: tegra: overlay: Modified overlay flipping for DSI one-shot mode.Kevin Huang
Bug 858957 Bug 861244 Original-Change-Id: Id9584e9f81d96d86d328c80e3c30efb36613f725 Reviewed-on: http://git-master/r/42817 Reviewed-by: Kevin Huang <kevinh@nvidia.com> Tested-by: Kevin Huang <kevinh@nvidia.com> Reviewed-by: Robert Morell <rmorell@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: Rc27fa2be5a956c999527a54fc089299212eff8e1
2011-11-30nvhost: Move include files to kernel/includeTerje Bergstrom
To prepare for kernel modularization, nvhost include files need to be moved from mach-tegra/include to kernel/include. At the same time user space specific part is split into nvhost_ioctl.h. Bug 854182 Original-Change-Id: I3694a40d786028733310ecf5b59341282af571be Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/43211 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rc4fadf65d59ddfb5bb924e7adfccd39e86a0b2c7
2011-11-30video: tegra: dc: fix CEA timings for hdmiJon Mayo
Fixes the issue that timings are 1 clock too long in 720p and 1080p. Bug 847774 Original-Change-Id: I3925ec1e64537daa27d6e697abe522ea17a87e1e Reviewed-on: http://git-master/r/42488 Reviewed-by: Kevin Huang <kevinh@nvidia.com> Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Tested-by: Jonathan Mayo <jmayo@nvidia.com> Rebase-Id: Rafbae1d4ae46bb13509af7ca59709e9f526bf6eb
2011-11-30video: tegra: Expose vblank syncpointRobert Morell
This change adds support for userspace to query the syncpoint that display autoincrements every vblank. This can be useful for applications to time buffer submissions to throttle rendering and prevent excessive host stalls. bug 818525 Original-Change-Id: I050e4dcd08609da802f10eeec5b70da181b21717 Signed-off-by: Robert Morell <rmorell@nvidia.com> Reviewed-on: http://git-master/r/40529 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rac929d8ba6b14e469fef4c2753b040e02fae0b8e
2011-11-30video: tegra: Add userspace CSC controlRobert Morell
This adds configurability of the per-window color space conversion support in the Tegra display controller through the dc extension interface. The CSC matrix defaults to its previously-hardcoded values, but can be overridden by userspace. bug 818525 Original-Change-Id: I00d8e48dd38a40e5b8c36d4624d31c834e5cd9de Signed-off-by: Robert Morell <rmorell@nvidia.com> Reviewed-on: http://git-master/r/40527 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R1f445ab544b4c06f56dde1e3f0e9db3c930a9c14
2011-11-30video: tegra: Allow fractional input rectsRobert Morell
This change makes the input rect for Tegra windows be a 20.12 fixed-point number instead of an integer. This allows software to specify sub-pixel precision. bug 818525 Original-Change-Id: I130f63b68159ed896d1113ea537307997875ca40 Signed-off-by: Robert Morell <rmorell@nvidia.com> Reviewed-on: http://git-master/r/40526 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R848e901645aa49776d4dc41fa4210b6b594a8d84
2011-11-30video: tegra: Only attempt filtering when supportedRobert Morell
The Tegra display windows are not entirely symmetric; only some of them support filtering in either direction. This change makes the kernel only enable filtering when it's supported by the hardware. bug 818525 Original-Change-Id: I0f85f52fcc5c6785c75003c54c8aee12fcd0a220 Signed-off-by: Robert Morell <rmorell@nvidia.com> Reviewed-on: http://git-master/r/40524 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R7306a484983f91d501bcb122d5fc3cf25c5006d7
2011-11-30video: tegra: Wire up output connectednessRobert Morell
This makes the core dc driver keep track of whether a particular input in enabled. It is up to the output ops to maintain the connected status if a detect op is plugged in, otherwise it is assumed that the output is always connected. bug 818525 Original-Change-Id: I794d7e2db347f63bbb1a7d80bca1a53d9d10c210 Signed-off-by: Robert Morell <rmorell@nvidia.com> Reviewed-on: http://git-master/r/40522 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rfeeae486b6a39b95d9f1d95b697132b476735f50
2011-11-30video: tegra: Prevent hang when output disabledRobert Morell
This adds code to track when the dc is disabled and prevent flips or cursor moves. This prevents system hangs since the dc is powergated when it's disabled. bug 818525 Original-Change-Id: I061da1f6a831fa14a216520e603e0fbc5dbb0437 Signed-off-by: Robert Morell <rmorell@nvidia.com> Reviewed-on: http://git-master/r/40519 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rb648ef48bd3528344cf090c49093dcb258c20150
2011-11-30video: tegra: nvhost: Use a syncpoint per windowRobert Morell
Reserve one syncpoint per window per display controller instead of one for the entire display controller. This is necessary to allow multiple windows on a single display controller to flip asynchronously. bug 818525 Original-Change-Id: Ide1de2bf2ed0bfea7f6abe9aa93815efd0824db1 Signed-off-by: Robert Morell <rmorell@nvidia.com> Reviewed-on: http://git-master/r/40516 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R49886938a74e71db0c8f53edc8ac45e5015ffe84
2011-11-30video: tegra: Remove fbdev SET_NVMAP and FLIP ioctlsRobert Morell
This is necessary so that multiple clients can open /dev/fb* at the same time. The functionaly has been moved to the dc extension device nodes. bug 818525 Original-Change-Id: I299e060fce3bb9e3cbf976f3d94dbabc4b3f1654 Signed-off-by: Robert Morell <rmorell@nvidia.com> Reviewed-on: http://git-master/r/40515 Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Rebase-Id: R32908db3f1e344eea13d628f0341600ed698783d
2011-11-30video: tegra: Implement FLIP dc extension ioctl.Robert Morell
This is very similar to the tegra_fb FLIP ioctl. bug 818525 Original-Change-Id: Iba32ab5bf730b575477c62a8ae4394f1779ef65e Signed-off-by: Robert Morell <rmorell@nvidia.com> Reviewed-on: http://git-master/r/40514 Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Rebase-Id: R9a79363b09d2df38bec4b8a8666f97b1feff76ff
2011-11-30video: tegra: Add skeleton support for extensionsRobert Morell
This adds the infrasturcture for an enhanced driver interface to program extended capabilities of the Tegra display controller. It exposes a new set of device nodes for userspace clients distinct from the traditional fbdev device nodes. This is necessary due to limitations in the fbdev infrastructure that don't allow drivers to store file-private data. bug 818525 Original-Change-Id: I06cecf894792b9904c73f9ebcdeb746ff7455f6e Signed-off-by: Robert Morell <rmorell@nvidia.com> Reviewed-on: http://git-master/r/40512 Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Rebase-Id: Rfa3969804d7f52c841be1ff96305c9463077e1c5
2011-11-30driver: video: dc: Add check_ref_to_sync() in dc.Kevin Huang
Add new function to check display timing restrictions. Bug 847774 Original-Change-Id: I986f0211bafcdd0223257fe07863e8a79f03388c Reviewed-on: http://git-master/r/44409 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R88a1d1358640b7118074e2efa964d56a3e524f74
2011-11-30video: tegra: dsi: Optimize DSI suspend flow.Kevin Huang
- Added power saving mode to reduce power consumption. It supports disable whole dsi module, source clock and panel in early suspend. - Fixed synpt error in DSI resume. Bug 859593 Bug 858500 Original-Change-Id: I9a734db2192776a2a66ecf2b9075b3d50356e4e8 Reviewed-on: http://git-master/r/45681 Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com> Tested-by: Chih-Lung Huang <lhuang@nvidia.com> Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Rebase-Id: R5f508e0bfbaa840efc1bb8cf4f12d9707dd7cedf
2011-11-30video: tegra: dc: window bandwidth calculationsMichael Frydrych
Determine which windows are overlapping, and apply bandwidth calculations for emc clock scaling and latency allowance appropriately. Bug 856234 Bug 850602 Original-Change-Id: If587c46e8929b3885b25125f054f5cc2d22b2b58 Reviewed-on: http://git-master/r/44772 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R841ce1734a7afab1311d3367a72ba9755d6d539c
2011-11-30video: tegra: dc: Set PWM pin to SFIO in defaultMin-wuk Lee
Set PWM pin to SFIO before it is configured to DC output pin: Having too early SFIO setting for this pin makes black screen in display transition from bootloader to kenel and android since backlight can be turned off. Bug 858120 Original-Change-Id: I952aa73c50d1df57b1cedf0a5f9ffee0044048ea Reviewed-on: http://git-master/r/44304 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R89903c1f14f1b867638834bd1581d8637b079c94
2011-11-30video: tegra: add 504MHz pll_d rate for HDMIJoseph Lehrer
To support the 25.2MHz pixel clock frequency required for CEA-861-B format 1: 640x480p at 59.94Hz bug 837571 (cherry picked from commit d03e629f3f428d0666a559e8a5c5f94419107ad3) Original-Change-Id: I4f12b9333f31a2df6b1029acf5faffb7802f170c Reviewed-on: http://git-master/r/40380 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Re7907dc7bb4b61cd1af284a722a2b208d34e4687
2011-11-30video:tegra:dsi Add dsi one-shot mode support.Kevin Huang
Add support for DSI one-shot mode in dsi driver. Bug 848524 Original-Change-Id: Ic849d00775c8f08c202496abbd5dc49b141178a9 Reviewed-on: http://git-master/r/35810 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R71c9fa4a4b887b53fbae0d2097b44d3d26d9ac0e
2011-11-30ARM: tegra: clock: Optimize power consumption of DSI module.Kevin Huang
- Disable phy clock at early suspend. - Set DSI to LP mode at early suspend Bug 847254 Bug 848069 Original-Change-Id: Ia53fa3be5280172bc5aede12cef3ca06e07ea7f5 Reviewed-on: http://git-master/r/39245 Reviewed-by: Kevin Huang <kevinh@nvidia.com> Tested-by: Kevin Huang <kevinh@nvidia.com> Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Rebase-Id: Ra8be9383813904f9514cfca59455e40f5aa32346
2011-11-30video: tegra: dc: fix tiled memory efficiencyXin Xie
Tegra3 also supports LPDDR2 which has no tiled memory inefficiency as in DDR3. This patch adds one memory controller API to retrive tiled memory efficiency. BUG 847731 Original-Change-Id: I407914c6035389b696040947e7aebc6ecdb92bb1 Reviewed-on: http://git-master/r/40074 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R5675398d3066d01d3d46f26267eddbba1accc815
2011-11-30tegra: video: dc: disp1 and overlay at 204MHzVinayak Pane
Overlay was requesting emc 400MHz always during video playback. Playback happens in overlay which was calculated incorrectly. Reducing it to match accurate requirement. Calculate overlay EMC bandwidth requirement same as DC. Original-Change-Id: I5816d9ca1b42cd04048ca16b3e23e6d6ea312137 Reviewed-on: http://git-master/r/42507 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rc82d603742d5f9b5769b3f18a84ef8e718782b3b
2011-11-30video: tegra: dc: disable underflows for fpgaJon Mayo
For non-silicon platforms(fpga and simulation) disable all underflow interrupts. Original-Change-Id: Idda78cd5a8e1fda7fac672a259ed05c95876752b Reviewed-on: http://git-master/r/42286 Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Tested-by: Jonathan Mayo <jmayo@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: Rd37cc00d1ad527fae58834be3b225238d1ec8c49
2011-11-30video: tegra: dc: Fix no_vsync hang issue.Gaurav Sarode
no_vsync was causing random hangs due to unwanted interrupts were enabled on default. Fix bug 801463 Original-Change-Id: I8dabf4b9b7b98cd64f2caff94efe949e2768bdd2 Reviewed-on: http://git-master/r/40616 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R2aeb2a584b04dd36317bbd405e907ab6f45c2a41
2011-11-30tegra: video: dc: prevent division by zeroJon Mayo
Do not pass 0 to PICOS2KHZ() macro, as it causes Division by zero in kernel. Bug 850852 Original-Change-Id: Ice913aaf756719aaf49bf6fab54b5f1618fb07d5 Reviewed-on: http://git-master/r/41116 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rc77772df52dfd42db53be2c8cb4281a04262ad69
2011-11-30video: tegra: dc: apply latency allowance windowsJon Mayo
Calculate per window bandwidth and apply latency allowance factors to each active window. Reuses much of the emc bandwidth code. Bug 820273 Original-Change-Id: I24f9c5749d8ea646c5f5861cfe19c73536dbf7dc Reviewed-on: http://git-master/r/40134 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rb7c7fb7813fbd61302e51e86e86cab4063e7050b
2011-11-30video: tegra: dc: remove emc clock workerJon Mayo
remove the support to delay changing emc clock. Bug 850852 Original-Change-Id: Ibc125e7789ad96059c53c82eb51091afd7b880fc Reviewed-on: http://git-master/r/40133 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rc136721574d4337ce8538abcf852d4d64857cdbf
2011-11-30video: tegra: dc: only set supported filtersJon Mayo
Not all windows are created equal, only set vertical or horizontal filters when the window supports them. Bug 850852 Original-Change-Id: I69b40ff47fd8ed8499857408c249ddd35299ae95 Reviewed-on: http://git-master/r/40132 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R339412d8ca44cd3bbe69f4af8c9bdde32a6d56c7
2011-11-30video: tegra: dc: clean up dynamic emc codeJon Mayo
refactor emc code and centralize it in one place. Bug 850852 Original-Change-Id: Icddd270d1ea4f47de11aa3633dd2dbb205a15742 Reviewed-on: http://git-master/r/40131 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R50b0fc763281d1ce1b0758caf5e42bfb2d4a3050
2011-11-30tegra: video: dc: Add sys interface to read display CRC.Kevin Huang
- Add attribute in sys to read TEGRA_DC_CRC_CHECKSUM_LATCHED - Fix some minor formatting issue of dc_sysfs.c Bug 834332 Original-Change-Id: I48f75fcb1d5403ab40d0da438200a5552ba4e6ff Reviewed-on: http://git-master/r/37912 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rde819259112b14ed1ae67b41d66b1785d68a2b7f
2011-11-30video: tegra: dc: Remove tegrafb dependencyRobert Morell
The common dc.c code shouldn't include tegrafb.h; this breaks modularity. Fortunately, it was only being used to count windows, and there's a non-FB-specific version of that. Original-Change-Id: I81a082ce9cf6f7da32da0c2399344c017863c6ee Signed-off-by: Robert Morell <rmorell@nvidia.com> Reviewed-on: http://git-master/r/39300 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rf9ef44ad4e17af87126f017b014915a7b9ab8df2
2011-11-30video: tegra: dc: print bandwidth warning onceXin Xie
In some stress tests, calculated EMC bandwidth is more than allowed EMC bandwidth and print out too many warning. Change to print the warning only once. BUG 847731 Original-Change-Id: Ia369d4295231e1db39532b0fc6ae8a29f9dbea65 Reviewed-on: http://git-master/r/39740 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Re9f0b2b50f5bd2afc25564ad97396453e68f9e55
2011-11-30video: tegra: dc: Update the tegra_dc_setup_clk() for HDMI and DSI.Kevin Huang
Fix the conflict of clock sources for HDMI & DSI. Original-Change-Id: I730a39fbfd5fe56eea10c0f2147ceee7c3f03921 Reviewed-on: http://git-master/r/39081 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rb7201a0b141f699841f2eeb73faddea3f7983759
2011-11-30video: tegra: Use new Tegra platform typesYudong Tan
This change is needed to support three platforms, silicon, fpga and simulation. Change-Id: I70c6edbab85712b037b1ddf15ce72cf1a2affeba Reviewed-on: http://git-master/r/36354 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rdd2875e5494a504dc4d2df0393bc798765a9b865
2011-11-30video: tegra: dc: fix DSI pclk calculationXin Xie
BUG 844499 Original-Change-Id: Ib99a921456f4a6e8e3e2d40907a91d492daf4bc0 Reviewed-on: http://git-master/r/38773 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R6dccc88053c055d9e4828d6f4d4e18932f0502f2
generated by cgit v1.2.3 (git 2.0.4) at 2024-04-25 08:59:31 +0000