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path: root/drivers/video/tegra/dc/dc.c
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2012-05-01Revert "video: tegra: dc: Clear window option before window update."Kevin Huang
This reverts commit 90b79e5712300baab889772a5af348559ac95836. Bug 955393 Change-Id: I0e2a15b7d0898dbbb62f09d8bd3502ec93366664 Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/99261 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jon Mayo <jmayo@nvidia.com> Reviewed-by: Nirav Patel <nipatel@nvidia.com> Reviewed-by: Adam Cheney <acheney@nvidia.com> Tested-by: Adam Cheney <acheney@nvidia.com>
2012-04-24ARM: tegra: dc: support YUV422 formatJon Mayo
Change-Id: I8aa25b03fe6801882b65209cb1a6e125ef27ac2c Signed-off-by: Michael I. Gold <gold@nvidia.com> Reviewed-on: http://git-master/r/98319 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-04-24video: tegra: dc: add tracing informationJon Mayo
add trace_printk to log useful debug information. Bug 870685 Change-Id: I29c0b1600f234ebb06d19c8b6c713b16f6e7643c Signed-off-by: Jon Mayo <jmayo@nvidia.com> Reviewed-on: http://git-master/r/89204 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Prashant Malani <pmalani@nvidia.com>
2012-04-20video: tegra: dc: update windows after set lutAdam Cheney
TEGRA_DC_EXT_SET_LUT programmed the proper shadow registers but did not copy the shadow registers to the active set. Signed-off-by: Adam Cheney <acheney@nvidia.com> bug 947281 Change-Id: Id734e128bb708f1a75c0cad22b0c51b083d8df3b Reviewed-on: http://git-master/r/91368 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-04-17Revert "video: tegra: dc: load video mode during vblank"Jon Mayo
Change-Id: Ib1b0fc6015a9dd45982a97231972dadba6b5a92e Reviewed-on: http://git-master/r/96966 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-04-11video: tegra: dc: load video mode during vblankJon Mayo
Handle mode set for FBIOPUT_VSCREENINFO at the end of a frame (during vblank). This elimiates the work around that requires disabling then enabling display to change modes. Adds a spinlock to protect irq code from updates to tegra_dc_mode structure. Bug 560152 Change-Id: I5d2175f01a177a32d685b46e5af4f78efeec0786 Signed-off-by: Jon Mayo <jmayo@nvidia.com> Reviewed-on: http://git-master/r/90688 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-04-06video: tegra: dc: avoid overflow in bw calculationJon Mayo
Change to using kbytes/sec to avoid overflowing 32-bit integer in bandwidth calculation. Changing efficiency adjustment to ~35%. Bug 958016 Change-Id: Ia8bdf79e4b3e4bc65517db18d9f351a5f840805e Signed-off-by: Jon Mayo <jmayo@nvidia.com> Reviewed-on: http://git-master/r/92658 Reviewed-by: Automatic_Commit_Validation_User
2012-04-04dc: enabled recovery from resettingAdam Jiang
Enabled recovery of DC from resetting. When underflow triggered serveral times(current > 4 for tegra2), DC driver will reset itself to prevent data corruption. Reopend nvhost connection when resetting finished. That helps system to show frames instead of a blank screen again. Fixed Bug 936613 Change-Id: I314c37258a4a446dc07167ac60d0420e79a5fb2d Signed-off-by: Adam Jiang <chaoj@nvidia.com> Reviewed-on: http://git-master/r/89406 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-03-30video: tegra: dc: remove obsolete overlay interfaceJon Mayo
Remove old overlay interface, it is replaced with TEGRA_DC_EXTENSIONS External functions made static now that overlay.c no longer needs them. Change-Id: I5d080ceb19ad90d3b5cc4bf20494c967687293a5 Signed-off-by: Jon Mayo <jmayo@nvidia.com> Reviewed-on: http://git-master/r/92661 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Chao Xu <cxu@nvidia.com> Reviewed-by: Robert Morell <rmorell@nvidia.com> Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com> Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com> Reviewed-by: Michael I Gold <gold@nvidia.com> Reviewed-by: Markus Holtmanns <mholtmanns@nvidia.com>
2012-03-23video: tegra3: dc: remove hard coded HDMI ratesShashank Sharma
Set dc clock rate dynamically to requested pixel rate. Using modes specified in monitor's EDID data. Return mode set errors on unsupported clock tolerances. Bug 931908 Change-Id: I60990ecbc2fbeab542987036b8ccc30b8dababe8 Signed-off-by: Shashank Sharma <shashanks@nvidia.com> Reviewed-on: http://git-master/r/86073 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-03-21video: tegra: dc: disable disp.emc clock when 0 new rate is requestedNitin Kumbhar
Not disabling emc clock when it's being set to zero results in incorrect reference count when a call is made to clear bandwidth. This happens when two worker threads try to handle dc emc rate. A deep-sleep/wake-up cycle easily shows this scenario. With this fix, disp.emc's ref count is properly managed even after multiple deep-sleep/wake-up cycles. Bug 947228 Change-Id: I045fafbd483af1e3d492b8d0395275e45642d059 Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: http://git-master/r/90100 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-03-14video: tegra: dc: Fix the EMC bandwidth clear.Kevin Huang
Bug 951626 Change-Id: Ia7c7474aa0f066cba8bd1519a98e302c4b3992e0 Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/89076 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2012-03-08video: tegra: dc: Remove unnecessary delay in dc postsuspendMin-wuk Lee
Remove unnecessary 100ms delay for primary panel since this is needed for HDMI type only. Bug 940012 Change-Id: Id27966fb28faa73ade3a868a9f89cadbde76e227 Signed-off-by: Min-wuk Lee <mlee@nvidia.com> Reviewed-on: http://git-master/r/87613 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-03-08video: tegra: dc: Fix the race condition of one-shot work.Kevin Huang
Add lock to prevent race condition between cancellation of old delayed work and schedule of new delayed work. Bug 936337 Change-Id: I52df82e92279163841546127c72be9879ef810d0 Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/86730 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-02-28video: tegra: dc: Clear window option before window update.Kevin Huang
There exits an issue that if window number is less than DC_N_WINDOWS, window option of some windows won't be cleared. So although it should be disabled, it might not be disabled properly. This will lead to the failure of scan-out on screen. Bug 943846 Change-Id: I604399abaa590b27ab4ea41ed9eb2706be16a75a Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/86230 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-02-23video: tegra: dc: fix pixel clock latency issueKen Chang
GENERAL_ACT_REQ causes double-buffered registers to become active. This register needs to be programed to reduce the latency of pixel clock after dc enabled by tegra_dc_enable(). bug 926189 Signed-off-by: Ken Chang <kenc@nvidia.com> Reviewed-on: http://git-master/r/83346 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com> (cherry picked from commit f39c5ddd1867c508900c9aa2d4eead7eb3082343) Change-Id: I741c9be9074709c1ab571aa631cb462599d5fb78 Reviewed-on: http://git-master/r/84561 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-02-23video: tegra: dc: in continuous mode mask VBLANK after first frameNitin Kumbhar
A V_BLANK interrupt for each frame does not allow long lp2 idle intervals. If all windows are clean, mask V_BLANK interrupt after processing it for updating smart dimmer. It's unmasked again when a new window update is performed. This will schedule a work for updating smart dimmer for the new frame. Bug 920110 Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: http://git-master/r/85137 (cherry picked from commit 68398090aee22cf02069e5767c3e9a062b0fc2f6) Change-Id: I588328bfd0d6036febed236dc07f441878aa81d1 Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: http://git-master/r/85166 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com>
2012-02-21video: tegra: dc: use side-by-side stereo HDMI modeAndrija Bosnjakovic
Add a config option to limit HDMI stereo 3D output to 74.25MHz pixel clock. When this option is set, substitute the frame pack stereo modes for side-by-side (half) left-right stereo modes to meet this pixel clock restriction. By default, do not use it (use frame packed HDMI mode as usual). Bug 938807 Change-Id: I2ce2ca72cbb15ac1939af0f3386dd23650262435 Reviewed-on: http://git-master/r/84252 Reviewed-by: Andrija Bosnjakovic <abosnjakovic@nvidia.com> Tested-by: Andrija Bosnjakovic <abosnjakovic@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com>
2012-02-15video: tegra: dc: protect dc extension disabling with a lockNitin Kumbhar
When dc gets many underflows, instances of reset worker can race to perform reset. dc ext was getting disabled outside critical region affecting display path. disable dc ext after getting the lock. Bug 936545 Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: http://git-master/r/83108 (cherry picked from commit f9dcf7eee8ca8db28cee6fa9550044d1f746e843) Change-Id: Ie29dc66eb52c9be472c2d0db8c0014bfe1837ad4 Reviewed-on: http://git-master/r/83406 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-02-15video: tegra: dc: Schedule delayed work to clear emc bandwidth.Kevin Huang
Bug 932840 Change-Id: I12d8d2d2cd42d0dafea38463ad77b44f7e64d7c1 Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/83645 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-02-13video: tegra: dc: Activate dc registers properly for one-shot mode.Kevin Huang
Enable GENERAL_ACT_REQ and HOST_TRIG_ENABLE at the same time. Bug 930840 Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/78638 (cherry picked from commit 2f78c8e3c243b4c866ad54a550167abd94c200c1) Change-Id: If0ef97c4a2b1a0621152c02728edbbed064a5e34 Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Reviewed-on: http://git-master/r/82715 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Tested-by: Varun Wadekar <vwadekar@nvidia.com>
2012-02-13video: tegra: dc: enable dc ext from underflow reset workerNitin Kumbhar
DC ext is enabled only from _tegra_dc_controller_enable() which is not used from reset worker. Enable dc ext from _tegra_dc_controller_reset_enable() as well. Bug 933391 Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: http://git-master/r/78753 (cherry picked from commit a099c612f91cc12a99325e39609b1f9001525be0) Change-Id: Ia95df85ea602174c2fd66888b21f7a6d264c176e Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Reviewed-on: http://git-master/r/82714 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Tested-by: Varun Wadekar <vwadekar@nvidia.com>
2012-02-03video: tegra: dc: Call display client disable before dc irq disableAnimesh Kishore
dc irqs are required in display client disable to flag stopping of dc stream. Bug 930453 Reviewed-on: http://git-master/r/77808 Change-Id: I0e057ca14078d9e608cb32380123fade813c4041 Signed-off-by: Animesh Kishore <ankishore@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/78898 Reviewed-by: Automatic_Commit_Validation_User
2012-01-30video: tegra: dsi: Refine the DSI clock calculation.Kevin Huang
Reviewed-on: http://git-master/r/76406 Change-Id: I6e5b37a88d6be4ba2cc81417fe3eadfd129bc899 Signed-off-by: Kevin Huang <kevinh@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/77306 Reviewed-by: Automatic_Commit_Validation_User
2012-01-24video: tegra: dc: Add dc backup clock source supportAlex Frid
Add backup clock source option in dc platform configuration. Use backup source if fixed frequency pllp is specified as main source, but its rate can not be divided into pixel clock within required tolerance. 928260 Change-Id: I19bd9173276c6ea087f86361956809787875e979 Reviewed-on: http://git-master/r/76033 Signed-off-by: Alex Frid <afrid@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/76818 Reviewed-by: Automatic_Commit_Validation_User
2012-01-24video: tegra: host: Access nvhost_master via drvdataTerje Bergstrom
Use standard drvdata interface for storing and accessing nvhost_master. Reviewed-on: http://git-master/r/72846 Change-Id: I191987c8f6d313a6ede9b59f723269cb6a197e8a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/76815 Reviewed-by: Automatic_Commit_Validation_User
2012-01-24video: tegra: dc: enable emc clock on probeNitin Kumbhar
When dc->emc_clk_rate goes from 0 to non-zero the dispX.emc clock is enabled. This works with the sequence for probe and hotplug to have emc clock in the correct enable/disable state. Bug 927785 Bug 917769 Reviewed-on: http://git-master/r/76208 Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Signed-off-by: Jon Mayo <jmayo@nvidia.com> Change-Id: I53cc8c5091967ce021dd3ec1e2bc75405dc8c45c Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/76813 Reviewed-by: Automatic_Commit_Validation_User
2012-01-19video: tegra: dc: 1-shot bandwidth calculationJon Mayo
In one-shot mode(DSI) report emc rate as disabled to reduce bandwidth in this idle state. Use this same tegra_dc_clear_bandwidth() function to handle display disable for all types of displays. Bug 914917 Change-Id: I84ca1341d71999b3558f9dadb103b258a1a6ab6f Signed-off-by: Jon Mayo <jmayo@nvidia.com> Reviewed-on: http://git-master/r/74652 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com> Tested-by: Xin Xie <xxie@nvidia.com> Reviewed-on: http://git-master/r/75536 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-01-16Revert "video: tegra: dc: fix DSI pclk calculation"Jon Mayo
This reverts commit 20f43dfc590d22ad1e80b7b948f108b17038b084. Conflicts: drivers/video/tegra/dc/dc.c This fix is no longer needed to boot. Change-Id: Ie8d877207b6a1d70c63834f234d7a7cc68a372bf Signed-off-by: Jon Mayo <jmayo@nvidia.com> Reviewed-on: http://git-master/r/74884 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com> Reviewed-on: http://git-master/r/75151 Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Tested-by: Varun Wadekar <vwadekar@nvidia.com>
2012-01-16video: tegra: dc: consolidate underflow codeJon Mayo
Move underflow handling out of the irq handler and into a workqueue. Change-Id: I289d0a4c4e632a229e46d8e7f82e637409813807 Signed-off-by: Jon Mayo <jmayo@nvidia.com> Reviewed-on: http://git-master/r/74427 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Reviewed-on: http://git-master/r/75143 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2012-01-12video: tegra: host: Move device data to nvhost_deviceTerje Bergstrom
Move all device data from nvhost_channeldesc, nvhost_moduledesc and nvhost_module to nvhost_device. nvhost_devices are also assigned into a hierarchy to prepare for implementation of runtime power management. Change-Id: I1e18daae8fe538086cd1f453d316e0f73e9d7d92 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/72844 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Reviewed-on: http://git-master/r/74560 Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Tested-by: Varun Wadekar <vwadekar@nvidia.com>
2012-01-12Revert "video: tegra: dc: use highest bandwidth setting"Jon Mayo
This reverts commit af9a6eb54c031a8cca1477134d07e1ef2b807be3. Test reports were inconclusive on the effectiveness of this change. Change-Id: I859a14d2e2dcd9eed3a1c64f35e4f1c077660311 Reviewed-on: http://git-master/r/74021 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Reviewed-on: http://git-master/r/74550 Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Tested-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jon Mayo <jmayo@nvidia.com>
2012-01-10video: tegra: dc: Fix support for YUV422RFrancis Hart
The tegra display controller supports the YUV422R planar surface format, but this was not handled by the dc driver. This change also fixes the YUV422RA planar format variation. Bug 914375 Change-Id: I73ffd2f7434c71d8353c7e16ada5ac6b13fee86b Reviewed-on: http://git-master/r/69446 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> (cherry picked from commit a085ef1eeb332116f102d82af25f7a6451eb6329) Reviewed-on: http://git-master/r/73950 Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Tested-by: Varun Wadekar <vwadekar@nvidia.com>
2012-01-04video: tegra: dc: use highest bandwidth settingJon Mayo
Apply the highest bandwidth setting before windows are programmed rather than waiting for vblank. Bug 914917 Change-Id: Iaaede9966191fdfc896bbbb19fbbadf9c4598bff Signed-off-by: Jon Mayo <jmayo@nvidia.com> Reviewed-on: http://git-master/r/72301 Reviewed-by: Michael I Gold <gold@nvidia.com> Tested-by: Michael I Gold <gold@nvidia.com>
2011-12-30video: tegra: dc: Fix dc stream random failure to stopAnimesh Kishore
Fix dc stream randomly failing to stop. Add stablization delay during dsi interface reset. Bug 913019 Change-Id: I1cf3013659de75d15cb1ff41b27c63abd953d614 Signed-off-by: Animesh Kishore <ankishore@nvidia.com> Reviewed-on: http://git-master/r/71952 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-by: Krishna Yarlagadda <kyarlagadda@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2011-12-21video: tegra: dc: direct dc out pins polarity settingMin-wuk Lee
dc vsync, hsync, DE and pclk polarity in kernel can be different with bootloader setting for a short time when default polarity value is written. This can generate momentary panel flicker in kernel boot. Set the first polarity based on board dc out pin polarity information directly if needed. Bug 891444 Signed-off-by: Min-wuk Lee <mlee@nvidia.com> Reviewed-on: http://git-master/r/59895 (cherry picked from commit 8e5bfd5702067309171b62a6be5471bfab68a31e) Change-Id: I80c703792ea5a9596d4cf42ef19115cbf4d556f6 Reviewed-on: http://git-master/r/69711 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Min-wuk Lee <mlee@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com> Tested-by: Min-wuk Lee <mlee@nvidia.com>
2011-12-15video: tegra: dc: Move DSI clock configuration to DC.Kevin Huang
We'd better place clock set-up in dc as HDMI. It makes code cleaner. Also eliminate a false warning. Bug 902786 Bug 850852 Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/65024 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com> (cherry picked from commit e570e8dd45a66f11f0fc432f5919c5a036e34ba0) Change-Id: I90d73602048e2b3c706550128ba04665c307da22 Reviewed-on: http://git-master/r/68863 Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com> Tested-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com>
2011-11-30driver: video: terga: dc: fix switch class dependenciesMursalin Akon
Mark the dependencies of dc driver on switch class explicit, using proper pre-processors. Bug 877239 Change-Id: Ie5931aaf4f279e6379b85a00a30bd3cb910614d0 Signed-off-by: Mursalin Akon <makon@nvidia.com> Reviewed-on: http://git-master/r/55774 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R229bab237a55cacd22f5071eaca1a60503fdbb0d
2011-11-30HACK: handle DC IRQ when off gracefullyDan Willemsen
Change-Id: I613ad237bda9845c928b27b96db227e484b95f7d Reviewed-on: http://git-master/r/41077 Tested-by: Daniel Willemsen <dwillemsen@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rbc20d94729500157b45207bac4ab0d4340297af2
2011-11-30video: tegra: add modeset switch to trigger ueventsDan Willemsen
Original-Change-Id: I3b060b622a593d48319a442072a21d0c4f9527ae Reviewed-on: http://git-master/r/19049 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Ra9c6d91a0cb402b3b660e417a87480b36933a92f
2011-11-30video: tegra: dc: ignore unused overlays for bandwidthJoel Kenny
If an overlay is not being used, do not program the latency allowance. This is to avoid underflows that occur at a resolution of 19x12. When the unused overlays are reenabled, they underflow if the latency allowance has previously been increased to a very high value. Change-Id: Id381a74f5cc602d47199cb42d17f77b1086de70e Reviewed-on: http://git-master/r/58195 Reviewed-by: Jon Mayo <jmayo@nvidia.com> Reviewed-by: Joel Kenny <jkenny@nvidia.com> Tested-by: Joel Kenny <jkenny@nvidia.com> Tested-by: Gerrit_Virtual_Submit (cherry picked from commit cbc4e10451137a972ef694d7698c7dab26017377) Signed-off-by: Jon Mayo <jmayo@nvidia.com> Change-Id: Id7101997db77e54861ef1045df5eccdfa4ee09eb Reviewed-on: http://git-master/r/64065 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com> Rebase-Id: R8338a8bee51d297d66d8e0708f91627d202269ec
2011-11-30video: tegra: dc: use mask to control interruptsJon Mayo
Use the enable irq register during init, and mask irq register to control the interrupts to avoid a race in clearing interrupt status. Clear mask and enable during DC disable. Bug 888207 Bug 870801 Reviewed-on: http://git-master/r/57603 (cherry picked from commit 4640498bd8d46b6c5c1898d8ca8c9760416d1eae) Change-Id: I8d93746533da5021919cc4152a467adc6889c4c6 Signed-off-by: Jon Mayo <jmayo@nvidia.com> Reviewed-on: http://git-master/r/63370 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com> Rebase-Id: Ra3d62939458871c4c1cc09fe6010922cc95e4a1c
2011-11-30video: tegra: dc: Use FRAME_END_INT to mark completion of frame end.Kevin Huang
V_BLANK_INT was used to mark frame end for other tasks. However, it occurs at frame start. Switch to FRAME_END_INT to mark the end of frame. Bug 875448 Reviewed-on: http://git-master/r/52694 (cherry picked from commit 078a2688c67c46cf840f191405cd4324cb9c4574) Signed-off-by: Jon Mayo <jmayo@nvidia.com> [jmayo@nvidia.com: wrapped commit message, fixed bug in S_TO_MS()] Change-Id: I507148772c2f3037befd30289e5b3a56fe417ee9 Reviewed-on: http://git-master/r/63369 Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com> Tested-by: Jon Mayo <jmayo@nvidia.com> Rebase-Id: R5dbcf2d7ff3fd627194ae1a6163a300e6e48ff7c
2011-11-30video: tegra: dc: remove extra call to tegra_periph_reset_assertTom Cherry
During the K39 merge an additional call to tegra_periph_reset_assert was added. The call in this place was moved by the following two commits and needs to be removed from where it currently is. e9f069bc video: tegra: dc: Fix introduced regression. 884cc8a9 tegra: dc: fix dc hang during dc reset Bug 895713 Change-Id: Ibfe1445f23dbc92498696a6d0743f4b5f92e049e Reviewed-on: http://git-master/r/62510 Tested-by: Thomas Cherry <tcherry@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com> Rebase-Id: Re923f258ce13fa9c3fc4f9643762784729df63ae
2011-11-30video: tegra: dc: support global fbdev gamma tableDavid Schalig
Add support to set a global gamma correction table via fbdev cmap API. The 3 Tegra DC windows have their own local gamma tables, which can either override or alter the global table. Bug 868060 Change-Id: I0be1c5e4afa8fd8c010b772c7808c883c0848ab4 Reviewed-on: http://git-master/r/60201 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R7e613b1c8ac469242172bd81db9dfba25176e0c3
2011-11-30video: tegra: support display board PM313Hyungwoo Yang
This change supports PM313 with 19X12 panel. The change uses PM313 in "Single input to Dual output" mode Bug ID : 822980 Reviewed-on: http://git-master/r/50215 (cherry picked from commit b83e795747fa860b5b7fb66b2067ebe4f15bcfd0) Change-Id: Iabf707ded2976e9877481c215d0b1f1940781f14 Reviewed-on: http://git-master/r/60085 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Re8eadc35c75fa21b0a5f3cb3bee0e8cb77dc3238
2011-11-30video: tegra: dc: preserve gamma/csc over suspendDavid Schalig
Preserve YUV-to-RGB and gamma correction tables over suspend-resume Bug 868060 Change-Id: I5ea2224f7ab0dfbe24d741b89d727034be3ebf68 Reviewed-on: http://git-master/r/58016 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R84115584b766900004b5c6cdc3cc8d693fb0db5a
2011-11-30video: tegra: Phase in DIDIMMatt Wagner
Settings in DIDIM driver are now phased in over a defined number of steps in order to minimize the perception of changes to the settings during runtime Bug 840155 Reviewed-on: http://git-master/r/52495 (cherry picked from commit a33d4f5c677b657751fd017f8419df88016122a5) Change-Id: I0af84609d0f2ebadf23463473ebf0211dfa594a3 Reviewed-on: http://git-master/r/55789 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R759433a3cfd9b4c07216da4b2c9de6e515a8530d
2011-11-30video: tegra: dc: ioctl for setting gamma lutDavid Schalig
- enable gamma look-up hardware only when needed to save power - add flags field to ioctl TEGRA_DC_EXT_SET_LUT for forward compatibility Bug 868060 Change-Id: I690f8b8856e0b1acd6215907ca8bd78ecaf30b17 Reviewed-on: http://git-master/r/57736 Reviewed-by: David Schalig <dschalig@nvidia.com> Tested-by: David Schalig <dschalig@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com> Reviewed-by: Robert Morell <rmorell@nvidia.com> Rebase-Id: Rf6081a9372ba7d6e53a66b9b58a50a62ad409d9a
2011-11-30video: tegra: dc: revert d3408e77 for WIN_IS_ENABLEDSachin Nikam
Revert d3408e77 partailly which was causing NULL pointer derefence on HDMI hotplug in WIN_IS_ENABLED. Bug 881945 Change-Id: I2aa5757a9c4d4d7d010544941e4a05a7ba4db5f7 Signed-off-by: Sachin Nikam <snikam@nvidia.com> Reviewed-on: http://git-master/r/56218 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R8a1ee743deca53371073b9d622d4cc171d739443
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-13 15:29:40 +0000