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path: root/drivers/video/tegra/dc/dc_priv.h
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2012-11-16android: dc: tegra: video: conditionally revert timestamp supportMarcel Ziswiler
Android R14 userspace seems to have issues with timestamp support: [ 14.764337] host1x host1x: SurfaceFlinger: syncpoint id 8 (disp0_a) stuck waiting 3, timeout=2147483447 [ 14.773845] host1x host1x: id 8 (disp0_a) min 2 max 4 [ 14.779163] host1x host1x: id 9 (disp1_a) min 2 max 4 [ 14.784316] host1x host1x: id 18 (2d_0) min 21 max 25 [ 14.789586] host1x host1x: id 20 (disp0_b) min 2 max 4 [ 14.794889] host1x host1x: id 21 (disp1_b) min 2 max 4 [ 14.800241] host1x host1x: id 22 (3d) min 77 max 95 [ 14.805217] host1x host1x: id 24 (disp0_c) min 2 max 4 [ 14.810573] host1x host1x: id 25 (disp1_c) min 2 max 4 [ 14.815873] host1x host1x: id 26 (vblank0) min 800 max 0 [ 14.821264] host1x host1x: id 27 (vblank1) min 684 max 0 [ 14.826810] host1x host1x: waitbase id 3 val 77 Therefore conditionally revert it in that case for now. See e4e2e776a3d4bf1adf37fc061cfdfb92281f3ace.
2012-08-21video: tegra: dc: Add timestamp supportRaghavendra VK
bug 1021221 Change-Id: Ifbe007de5bdeafaa15a0b3f2a138086045eba160 Signed-off-by: Raghavendra VK <rvk@nvidia.com> Reviewed-on: http://git-master/r/118179 (cherry picked from commit 74be8d4e7210d7bcea0d55565a7cbb06d6cc960e) Reviewed-on: http://git-master/r/121087 Reviewed-by: Jon Mayo <jmayo@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Robert Morell <rmorell@nvidia.com>
2012-07-30misc: tegra-throughput: adding throughput dev nodeIlan Aelion
Creates a miscdev at /dev/tegra-throughput which gl will use to set a target frame rate. In addition it receives notifications from dc on flip events. On each notification the percentage ratio of the actual frame time to the target frame time is calculated. In subsequent changes this ratio will be reported to other modules as a throughput hint. Bug 991589 Change-Id: Ieaa2b2755b63d2d071de31e3ef819d4c3b51a956 Signed-off-by: Ilan Aelion <iaelion@nvidia.com> Reviewed-on: http://git-master/r/116865 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com>
2012-07-25video: tegra: dc: synchronize dsi clock-gatingRakesh Iyer
The one shot thread will clock gate the modules periodically. This will ensure relevant paths in dc driver have an active dc clock and dsi host. Bug 1013172 Change-Id: Ibb505e35044f31405c06cb9fa0d6fdf78aafd4a6 Signed-off-by: Rakesh Iyer <riyer@nvidia.com> Reviewed-on: http://git-master/r/117137 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jon Mayo <jmayo@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Animesh Kishore <ankishore@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-07-02video: tegra: dc: split dc.c into smaller filesJon Mayo
Moved mode setting code into mode.c Move window code info window.c Moved clock related code into clock.c Moved LUT and gamma related code into lut.c Moved csc(color space conversion) into csc.c Removed unnecessary static function prototypes from header. Moved many short inline functions to dc_priv.h Cleaned up copyright headings. Cleaned up formatting and indent in all files. Fixed build warnings. Bug 870907 Change-Id: I6ccc37150191765394f0b5629423eafd4e5e5792 Signed-off-by: Jon Mayo <jmayo@nvidia.com> Reviewed-on: http://git-master/r/111371 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-06-26video: tegra: use public APIs exposed by host1x driverMayuresh Kulkarni
Bug 961009 Change-Id: Ifdcc7bc8a40d270e70a63329f46caff541bf01e2 Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-on: http://git-master/r/109461 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-06-22video: tegra: dc: force the use of new bandwidthJon Mayo
During programming of a frame or at frame end, force the use of the new EMC bandwidth instead of the previous frame's bandwidth. Moved copy of new_bandwidth out of tegra_dc_set_latency_allowance() to match the semantics of the rest of tegra_dc_program_bandwidth(). bug 949015 Change-Id: I881f3a2c75f3438e3bbb3208b518f15a4574bc91 Signed-off-by: Jon Mayo <jmayo@nvidia.com> Reviewed-on: http://git-master/r/110149 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Daniel Solomon <daniels@nvidia.com> Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
2012-06-14video: tegra: dc: Move #includes from dc_priv.hTerje Bergstrom
Move #include directives for nvhost headers from dc_priv.h to the source files that need the #includes. This allows #including dc_priv.h without access to all nvhost headers. Also adds nvhost to the #include path of dc to allow making dev.h a stub in a later commit. Bug 982965 Change-Id: Icfe7084d295f57926195b178174f81047eb01187 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/108225 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-06-13video: tegra: dc: Use ref-count to mask vblank interrupt.Kevin Huang
Bug 990586 Change-Id: I63da2bd0aaae86070718e0d769b8c9555db18547 Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/107714 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jon Mayo <jmayo@nvidia.com>
2012-06-11video: tegra: dc: Clock-gate display modules dynamically.Kevin Huang
Bug 936337 Bug 899053 Change-Id: I2b3d8cfc8a00881338c1e17d03f2844d15ba7d3e Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/106313 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-06-06video: tegra: dc: new file for bandwidth calcJon Mayo
Move bandwidth calculation logic into its own file. Change-Id: I57f58a6399805eede8783fea922c6f07dcbd54cb Signed-off-by: Jon Mayo <jmayo@nvidia.com> Reviewed-on: http://git-master/r/106291 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
2012-05-16video: tegra: dc: fix build warningsJon Mayo
Makes function pointer type for mode_filter match the function in hdmi.c Change-Id: Id61f319a4ddef003b79782391e9e7f2f8cb32dda Signed-off-by: Jon Mayo <jmayo@nvidia.com> Reviewed-on: http://git-master/r/102630 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Shashank Sharma <shashanks@nvidia.com>
2012-05-11video: tegra: dc: Add display feature table support.Kevin Huang
Add display feature table so that user and kernel could set and update window attributes properly. Bug 962353 Change-Id: I08490a225892660126f3eefe4d5b7a4bb61d9bf7 Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/101078 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-08video: tegra: fb: Call mode filter from check varShashank Sharma
Call dc_hdmi_mode_filter to validate a videomode. X prepares its own modedb of supported HDMI modes, but all of them may not be supported from the HDMI driver. This call makes sure a X-mode is listed only if supported in DC driver. Bug: 959676 Change-Id: I8aff65f4e08fcc4471af096150e3972b5913a95a Signed-off-by: Shashank Sharma <shashanks@nvidia.com> Reviewed-on: http://git-master/r/99650 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-05-04video: tegra: host: Clean up includesTerje Bergstrom
Clean up #includes. Replace #includes with forward declarations where possible, and remove extraneous #includes. Bug 871237 Change-Id: I6942e0c632b42ad7009589ebdd78def88ae4baa4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/99046 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
2012-04-24video: tegra: dc: add tracing informationJon Mayo
add trace_printk to log useful debug information. Bug 870685 Change-Id: I29c0b1600f234ebb06d19c8b6c713b16f6e7643c Signed-off-by: Jon Mayo <jmayo@nvidia.com> Reviewed-on: http://git-master/r/89204 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Prashant Malani <pmalani@nvidia.com>
2012-04-17Revert "video: tegra: dc: load video mode during vblank"Jon Mayo
Change-Id: Ib1b0fc6015a9dd45982a97231972dadba6b5a92e Reviewed-on: http://git-master/r/96966 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-04-11video: tegra: dc: load video mode during vblankJon Mayo
Handle mode set for FBIOPUT_VSCREENINFO at the end of a frame (during vblank). This elimiates the work around that requires disabling then enabling display to change modes. Adds a spinlock to protect irq code from updates to tegra_dc_mode structure. Bug 560152 Change-Id: I5d2175f01a177a32d685b46e5af4f78efeec0786 Signed-off-by: Jon Mayo <jmayo@nvidia.com> Reviewed-on: http://git-master/r/90688 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-03-30video: tegra: dc: remove obsolete overlay interfaceJon Mayo
Remove old overlay interface, it is replaced with TEGRA_DC_EXTENSIONS External functions made static now that overlay.c no longer needs them. Change-Id: I5d080ceb19ad90d3b5cc4bf20494c967687293a5 Signed-off-by: Jon Mayo <jmayo@nvidia.com> Reviewed-on: http://git-master/r/92661 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Chao Xu <cxu@nvidia.com> Reviewed-by: Robert Morell <rmorell@nvidia.com> Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com> Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com> Reviewed-by: Michael I Gold <gold@nvidia.com> Reviewed-by: Markus Holtmanns <mholtmanns@nvidia.com>
2012-03-08video: tegra: dc: Fix the race condition of one-shot work.Kevin Huang
Add lock to prevent race condition between cancellation of old delayed work and schedule of new delayed work. Bug 936337 Change-Id: I52df82e92279163841546127c72be9879ef810d0 Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/86730 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-02-15video: tegra: dc: Schedule delayed work to clear emc bandwidth.Kevin Huang
Bug 932840 Change-Id: I12d8d2d2cd42d0dafea38463ad77b44f7e64d7c1 Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/83645 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-01-30video: tegra: dsi: Refine the DSI clock calculation.Kevin Huang
Reviewed-on: http://git-master/r/76406 Change-Id: I6e5b37a88d6be4ba2cc81417fe3eadfd129bc899 Signed-off-by: Kevin Huang <kevinh@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/77306 Reviewed-by: Automatic_Commit_Validation_User
2012-01-24video: tegra: host: Access nvhost_master via drvdataTerje Bergstrom
Use standard drvdata interface for storing and accessing nvhost_master. Reviewed-on: http://git-master/r/72846 Change-Id: I191987c8f6d313a6ede9b59f723269cb6a197e8a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/76815 Reviewed-by: Automatic_Commit_Validation_User
2012-01-19video: tegra: dc: 1-shot bandwidth calculationJon Mayo
In one-shot mode(DSI) report emc rate as disabled to reduce bandwidth in this idle state. Use this same tegra_dc_clear_bandwidth() function to handle display disable for all types of displays. Bug 914917 Change-Id: I84ca1341d71999b3558f9dadb103b258a1a6ab6f Signed-off-by: Jon Mayo <jmayo@nvidia.com> Reviewed-on: http://git-master/r/74652 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com> Tested-by: Xin Xie <xxie@nvidia.com> Reviewed-on: http://git-master/r/75536 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-01-16Revert "video: tegra: dc: fix DSI pclk calculation"Jon Mayo
This reverts commit 20f43dfc590d22ad1e80b7b948f108b17038b084. Conflicts: drivers/video/tegra/dc/dc.c This fix is no longer needed to boot. Change-Id: Ie8d877207b6a1d70c63834f234d7a7cc68a372bf Signed-off-by: Jon Mayo <jmayo@nvidia.com> Reviewed-on: http://git-master/r/74884 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com> Reviewed-on: http://git-master/r/75151 Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Tested-by: Varun Wadekar <vwadekar@nvidia.com>
2012-01-16video: tegra: dc: consolidate underflow codeJon Mayo
Move underflow handling out of the irq handler and into a workqueue. Change-Id: I289d0a4c4e632a229e46d8e7f82e637409813807 Signed-off-by: Jon Mayo <jmayo@nvidia.com> Reviewed-on: http://git-master/r/74427 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Reviewed-on: http://git-master/r/75143 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2012-01-12video: tegra: host: Move device data to nvhost_deviceTerje Bergstrom
Move all device data from nvhost_channeldesc, nvhost_moduledesc and nvhost_module to nvhost_device. nvhost_devices are also assigned into a hierarchy to prepare for implementation of runtime power management. Change-Id: I1e18daae8fe538086cd1f453d316e0f73e9d7d92 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/72844 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Reviewed-on: http://git-master/r/74560 Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Tested-by: Varun Wadekar <vwadekar@nvidia.com>
2012-01-04video: tegra: host: Move host1x code into own directoryTerje Bergstrom
Move source files related to host1x into an own directory. Bug 871237 Change-Id: I6fa3ef057f8b788c37dd2ab698271cf7508711c6 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/71783 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com>
2011-12-21video: tegra: dc: direct dc out pins polarity settingMin-wuk Lee
dc vsync, hsync, DE and pclk polarity in kernel can be different with bootloader setting for a short time when default polarity value is written. This can generate momentary panel flicker in kernel boot. Set the first polarity based on board dc out pin polarity information directly if needed. Bug 891444 Signed-off-by: Min-wuk Lee <mlee@nvidia.com> Reviewed-on: http://git-master/r/59895 (cherry picked from commit 8e5bfd5702067309171b62a6be5471bfab68a31e) Change-Id: I80c703792ea5a9596d4cf42ef19115cbf4d556f6 Reviewed-on: http://git-master/r/69711 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Min-wuk Lee <mlee@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com> Tested-by: Min-wuk Lee <mlee@nvidia.com>
2011-11-30driver: video: terga: dc: fix switch class dependenciesMursalin Akon
Mark the dependencies of dc driver on switch class explicit, using proper pre-processors. Bug 877239 Change-Id: Ie5931aaf4f279e6379b85a00a30bd3cb910614d0 Signed-off-by: Mursalin Akon <makon@nvidia.com> Reviewed-on: http://git-master/r/55774 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R229bab237a55cacd22f5071eaca1a60503fdbb0d
2011-11-30video: tegra: add modeset switch to trigger ueventsDan Willemsen
Original-Change-Id: I3b060b622a593d48319a442072a21d0c4f9527ae Reviewed-on: http://git-master/r/19049 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Ra9c6d91a0cb402b3b660e417a87480b36933a92f
2011-11-30video: tegra: dc: Use FRAME_END_INT to mark completion of frame end.Kevin Huang
V_BLANK_INT was used to mark frame end for other tasks. However, it occurs at frame start. Switch to FRAME_END_INT to mark the end of frame. Bug 875448 Reviewed-on: http://git-master/r/52694 (cherry picked from commit 078a2688c67c46cf840f191405cd4324cb9c4574) Signed-off-by: Jon Mayo <jmayo@nvidia.com> [jmayo@nvidia.com: wrapped commit message, fixed bug in S_TO_MS()] Change-Id: I507148772c2f3037befd30289e5b3a56fe417ee9 Reviewed-on: http://git-master/r/63369 Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com> Tested-by: Jon Mayo <jmayo@nvidia.com> Rebase-Id: R5dbcf2d7ff3fd627194ae1a6163a300e6e48ff7c
2011-11-30video: tegra: dc: support global fbdev gamma tableDavid Schalig
Add support to set a global gamma correction table via fbdev cmap API. The 3 Tegra DC windows have their own local gamma tables, which can either override or alter the global table. Bug 868060 Change-Id: I0be1c5e4afa8fd8c010b772c7808c883c0848ab4 Reviewed-on: http://git-master/r/60201 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R7e613b1c8ac469242172bd81db9dfba25176e0c3
2011-11-30video: tegra: dc: improve underflow statisticsJon Mayo
Collect individual underflow counts for underflow statistics to provide a more accurate number of underflows. Changed stats to use 64-bit numbers due to the larger numbers involved, about 100x from previously. Reviewed-on: http://git-master/r/52940 (cherry picked from commit 1d39d430ad90a027be43323f65eef85a3a30faab) Change-Id: I4d253346dfcb01185a93a7602b7a1c971ea1ebb4 Reviewed-on: http://git-master/r/56301 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rf931d627fedc7ce8d9a37c1c54bb76aa2caf9ff1
2011-11-30video: tegra: Expose vblank syncpointRobert Morell
This change adds support for userspace to query the syncpoint that display autoincrements every vblank. This can be useful for applications to time buffer submissions to throttle rendering and prevent excessive host stalls. bug 818525 Original-Change-Id: I050e4dcd08609da802f10eeec5b70da181b21717 Signed-off-by: Robert Morell <rmorell@nvidia.com> Reviewed-on: http://git-master/r/40529 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rac929d8ba6b14e469fef4c2753b040e02fae0b8e
2011-11-30video: tegra: Only attempt filtering when supportedRobert Morell
The Tegra display windows are not entirely symmetric; only some of them support filtering in either direction. This change makes the kernel only enable filtering when it's supported by the hardware. bug 818525 Original-Change-Id: I0f85f52fcc5c6785c75003c54c8aee12fcd0a220 Signed-off-by: Robert Morell <rmorell@nvidia.com> Reviewed-on: http://git-master/r/40524 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R7306a484983f91d501bcb122d5fc3cf25c5006d7
2011-11-30video: tegra: Wire up output connectednessRobert Morell
This makes the core dc driver keep track of whether a particular input in enabled. It is up to the output ops to maintain the connected status if a detect op is plugged in, otherwise it is assumed that the output is always connected. bug 818525 Original-Change-Id: I794d7e2db347f63bbb1a7d80bca1a53d9d10c210 Signed-off-by: Robert Morell <rmorell@nvidia.com> Reviewed-on: http://git-master/r/40522 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rfeeae486b6a39b95d9f1d95b697132b476735f50
2011-11-30video: tegra: nvhost: Use a syncpoint per windowRobert Morell
Reserve one syncpoint per window per display controller instead of one for the entire display controller. This is necessary to allow multiple windows on a single display controller to flip asynchronously. bug 818525 Original-Change-Id: Ide1de2bf2ed0bfea7f6abe9aa93815efd0824db1 Signed-off-by: Robert Morell <rmorell@nvidia.com> Reviewed-on: http://git-master/r/40516 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R49886938a74e71db0c8f53edc8ac45e5015ffe84
2011-11-30video: tegra: Add skeleton support for extensionsRobert Morell
This adds the infrasturcture for an enhanced driver interface to program extended capabilities of the Tegra display controller. It exposes a new set of device nodes for userspace clients distinct from the traditional fbdev device nodes. This is necessary due to limitations in the fbdev infrastructure that don't allow drivers to store file-private data. bug 818525 Original-Change-Id: I06cecf894792b9904c73f9ebcdeb746ff7455f6e Signed-off-by: Robert Morell <rmorell@nvidia.com> Reviewed-on: http://git-master/r/40512 Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Rebase-Id: Rfa3969804d7f52c841be1ff96305c9463077e1c5
2011-11-30video: tegra: dc: window bandwidth calculationsMichael Frydrych
Determine which windows are overlapping, and apply bandwidth calculations for emc clock scaling and latency allowance appropriately. Bug 856234 Bug 850602 Original-Change-Id: If587c46e8929b3885b25125f054f5cc2d22b2b58 Reviewed-on: http://git-master/r/44772 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R841ce1734a7afab1311d3367a72ba9755d6d539c
2011-11-30video: dsi: tegra: Export dsi functionsAnimesh Kishore
Export following functions: - panel read - panel write - register write - register read Bug 830296 Original-Change-Id: Ie0854e0b8eb213ac2c7fd54f8883ec28e523e1a3 Reviewed-on: http://git-master/r/45529 Reviewed-by: Animesh Kishore <ankishore@nvidia.com> Tested-by: Animesh Kishore <ankishore@nvidia.com> Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com> Rebase-Id: R69d9bed3b6c66384316a849bd646726cd321b1b2
2011-11-30video: tegra: dc: fix tiled memory efficiencyXin Xie
Tegra3 also supports LPDDR2 which has no tiled memory inefficiency as in DDR3. This patch adds one memory controller API to retrive tiled memory efficiency. BUG 847731 Original-Change-Id: I407914c6035389b696040947e7aebc6ecdb92bb1 Reviewed-on: http://git-master/r/40074 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R5675398d3066d01d3d46f26267eddbba1accc815
2011-11-30tegra: video: dc: disp1 and overlay at 204MHzVinayak Pane
Overlay was requesting emc 400MHz always during video playback. Playback happens in overlay which was calculated incorrectly. Reducing it to match accurate requirement. Calculate overlay EMC bandwidth requirement same as DC. Original-Change-Id: I5816d9ca1b42cd04048ca16b3e23e6d6ea312137 Reviewed-on: http://git-master/r/42507 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rc82d603742d5f9b5769b3f18a84ef8e718782b3b
2011-11-30video: tegra: dc: remove emc clock workerJon Mayo
remove the support to delay changing emc clock. Bug 850852 Original-Change-Id: Ibc125e7789ad96059c53c82eb51091afd7b880fc Reviewed-on: http://git-master/r/40133 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rc136721574d4337ce8538abcf852d4d64857cdbf
2011-11-30video: tegra: dc: only set supported filtersJon Mayo
Not all windows are created equal, only set vertical or horizontal filters when the window supports them. Bug 850852 Original-Change-Id: I69b40ff47fd8ed8499857408c249ddd35299ae95 Reviewed-on: http://git-master/r/40132 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R339412d8ca44cd3bbe69f4af8c9bdde32a6d56c7
2011-11-30tegra: video: dc: Add sys interface to read display CRC.Kevin Huang
- Add attribute in sys to read TEGRA_DC_CRC_CHECKSUM_LATCHED - Fix some minor formatting issue of dc_sysfs.c Bug 834332 Original-Change-Id: I48f75fcb1d5403ab40d0da438200a5552ba4e6ff Reviewed-on: http://git-master/r/37912 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rde819259112b14ed1ae67b41d66b1785d68a2b7f
2011-11-30video: tegra: remove unused list.h from dc_priv.hRobert Morell
Original-Change-Id: I7a2d2e3016a0289b9df6e73e5d0234f6ace07904 Signed-off-by: Robert Morell <rmorell@nvidia.com> Reviewed-on: http://git-master/r/39306 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Ra44aa094ba19c367576af4e2cfa5e571e1e05ef9
2011-11-30video: tegra: refactor for multiple chip supportKen Adams
Original-Change-Id: Ia203886a3b013612b4159393ff43a25a313d1ece Reviewed-on: http://git-master/r/35911 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R01b763362c13e09111f60700c3d3a7d2a9a3fc1c
2011-11-30video: tegra: dc: fix DSI pclk calculationXin Xie
BUG 844499 Original-Change-Id: Ib99a921456f4a6e8e3e2d40907a91d492daf4bc0 Reviewed-on: http://git-master/r/38773 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R6dccc88053c055d9e4828d6f4d4e18932f0502f2
2011-11-30tegra: dc: set EMC clock dynamicallyXin Xie
If the screen is idle (no POST for some time), reduce the DC EMC clock according the windows size. If external display connected, the EMC clock will not be reduced. BUG 828306 Original-Change-Id: I6fb62ce6baf3380737c76b71f16e38ad6465a667 Reviewed-on: http://git-master/r/37106 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: Re2b2c8b1a57c2a04b61c338b0b50e41d8c11ad65
generated by cgit v1.2.3 (git 2.0.4) at 2024-04-26 05:12:25 +0000