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path: root/drivers/video/tegra/dc
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2012-04-11video: tegra: fb: Add interface to nvdps.Kevin Huang
Provide /sys/class/graphics/fb0/device/nvdps to change video mode on-the-fly without resetting window layout like fb_set_var(). This allows flicker free changes in refresh rate. nvdps sysfs file takes an integer, and selects the closest matching mode with the same or higher refresh rate. Reading the file displays the current refresh rate. Bug 560152 Change-Id: Id5c1eafaf338b99fa9742202b38ccbfc238b77d5 Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/95473 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jon Mayo <jmayo@nvidia.com>
2012-04-11video: tegra: dc: load video mode during vblankJon Mayo
Handle mode set for FBIOPUT_VSCREENINFO at the end of a frame (during vblank). This elimiates the work around that requires disabling then enabling display to change modes. Adds a spinlock to protect irq code from updates to tegra_dc_mode structure. Bug 560152 Change-Id: I5d2175f01a177a32d685b46e5af4f78efeec0786 Signed-off-by: Jon Mayo <jmayo@nvidia.com> Reviewed-on: http://git-master/r/90688 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-04-10video: tegra: resolve compilation time warningsSanjay Singh Rawat
bug 949219 Change-Id: I1ed8d08de4bdba4643b2ae4e8320db6f9c97a18f Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com> Reviewed-on: http://git-master/r/92310 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-04-08Revert "video: tegra: dc: Disable 1080p stereo support"Andrija Bosnjakovic
This reverts commit 75009bc2b1a0a2d2efbe1d166647e789b8a1b9f1. In order to work around bug 869099, this mode has been temporarily disabled. Since the bug is not so visible, enable again. Change-Id: Ie71dac4ecf620cd96796e2fde361b45dc7141497 Reviewed-on: http://git-master/r/92157 Reviewed-by: Alok Ahuja <alahuja@nvidia.com> Reviewed-by: Aleksandar Odorovic <aodorovic@nvidia.com> Reviewed-by: Dhiren Bhatia <dbhatia@nvidia.com> Reviewed-by: Andrija Bosnjakovic <abosnjakovic@nvidia.com> Tested-by: Andrija Bosnjakovic <abosnjakovic@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com>
2012-04-06video: tegra: dc: avoid overflow in bw calculationJon Mayo
Change to using kbytes/sec to avoid overflowing 32-bit integer in bandwidth calculation. Changing efficiency adjustment to ~35%. Bug 958016 Change-Id: Ia8bdf79e4b3e4bc65517db18d9f351a5f840805e Signed-off-by: Jon Mayo <jmayo@nvidia.com> Reviewed-on: http://git-master/r/92658 Reviewed-by: Automatic_Commit_Validation_User
2012-04-04dc: enabled recovery from resettingAdam Jiang
Enabled recovery of DC from resetting. When underflow triggered serveral times(current > 4 for tegra2), DC driver will reset itself to prevent data corruption. Reopend nvhost connection when resetting finished. That helps system to show frames instead of a blank screen again. Fixed Bug 936613 Change-Id: I314c37258a4a446dc07167ac60d0420e79a5fb2d Signed-off-by: Adam Jiang <chaoj@nvidia.com> Reviewed-on: http://git-master/r/89406 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-04-03tegra: hdmi: Add 1080p timing tableHao Tang
Bug 949759 Add new 1080p timing support, or 1080p playback is not available on some monitors like Acer H243HX Change-Id: I8a8a3a5b2de71d5a56dad233f953e09176f85b76 Signed-off-by: Hao Tang <htang@nvidia.com> Reviewed-on: http://git-master/r/91732 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-03-30video: tegra: dc: remove obsolete overlay interfaceJon Mayo
Remove old overlay interface, it is replaced with TEGRA_DC_EXTENSIONS External functions made static now that overlay.c no longer needs them. Change-Id: I5d080ceb19ad90d3b5cc4bf20494c967687293a5 Signed-off-by: Jon Mayo <jmayo@nvidia.com> Reviewed-on: http://git-master/r/92661 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Chao Xu <cxu@nvidia.com> Reviewed-by: Robert Morell <rmorell@nvidia.com> Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com> Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com> Reviewed-by: Michael I Gold <gold@nvidia.com> Reviewed-by: Markus Holtmanns <mholtmanns@nvidia.com>
2012-03-29video: tegra: add cursor mode flippingAdam Cheney
This change adds a flag to flip windows in cursor mode. Cursor mode will cause flips to be skipped over if there are newer flip requests waiting in the workqueue. Add CURSOR_MODE to caps bitfield. bug 942762 Change-Id: Ib52a0a5565f961cdd9650e4204cd65b86f96fee1 Signed-off-by: Adam Cheney <acheney@nvidia.com> Reviewed-on: http://git-master/r/90418 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Robert Morell <rmorell@nvidia.com>
2012-03-23video: tegra3: dc: remove hard coded HDMI ratesShashank Sharma
Set dc clock rate dynamically to requested pixel rate. Using modes specified in monitor's EDID data. Return mode set errors on unsupported clock tolerances. Bug 931908 Change-Id: I60990ecbc2fbeab542987036b8ccc30b8dababe8 Signed-off-by: Shashank Sharma <shashanks@nvidia.com> Reviewed-on: http://git-master/r/86073 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-03-22video: tegra: dc: VGA modes in supported mode listShashank Sharma
Add following VGA video modes in tegra_dc_hdmi_supported_modes list: Resolution Refresh rate(Hz) ----------- ---------------- 640x480 75 720x400 59 800x600 60 800x600 75 1024x768 75 1024x768 60 1152x864 75 1280x800 60 1280x960 60 1280x1024 60 1368x768 60 1440x900 60 1600x1200 75 1680x1050 60 Add CVT representation of all above modes to make sure they pass all the HDMI constraints. Add a new function tegra_dc_reload_mode to pick up CVT representation of matching mode. Bug 883911 Signed-off-by: Shashank Sharma <shashanks@nvidia.com> Change-Id: I5227644207d38ca83a0452d3c078ef202e40a508 Reviewed-on: http://git-master/r/89126 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Kiran Adduri <kadduri@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com>
2012-03-21video: tegra: dc: disable disp.emc clock when 0 new rate is requestedNitin Kumbhar
Not disabling emc clock when it's being set to zero results in incorrect reference count when a call is made to clear bandwidth. This happens when two worker threads try to handle dc emc rate. A deep-sleep/wake-up cycle easily shows this scenario. With this fix, disp.emc's ref count is properly managed even after multiple deep-sleep/wake-up cycles. Bug 947228 Change-Id: I045fafbd483af1e3d492b8d0395275e45642d059 Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: http://git-master/r/90100 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-03-20video: tegra: dsi: Clear host trigger bit explicitly on fifo emptyAnimesh Kishore
dsi HW does not clear host trigger bit automatically on dsi interface disable if host fifo is empty. This leads to hang. Clearing the bit explicitly. Bug 930453 Change-Id: Id24359dc274f187f8ac634ad838ef4a6a29a6a5e Signed-off-by: Animesh Kishore <ankishore@nvidia.com> Reviewed-on: http://git-master/r/90043 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
2012-03-19video: tegra: clean-up warnings and code styleJon Mayo
fix some build warnings and bad code style. Change-Id: I907296ce0e5437dfd6acd0b2b3c119b6dbde7b1c Signed-off-by: Jon Mayo <jmayo@nvidia.com> Reviewed-on: http://git-master/r/89634 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-03-15video: tegra: dsi: Add checks to dsi for HOST1X powerTerje Bergstrom
Add checks to ensure host1x is powered when DSI is used. Change-Id: I2e61abdd5c0741571fb18262fd2efa16ffee71d9 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/86361 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-03-15video: tegra: hdmi: validate clocks per frame of HDMI modeYoungjin Kim
There are HDMI modes which have different margin/sync values although resolution and pixel clock are the same. One example is 1080p/24Hz and 1080p/30Hz case. Those modes are not distinguished when we check if given two modes are equal. So clocks per frame also should be validated to decide sameness of the modes. Bug 950935 Signed-off-by: Youngjin Kim <nkim@nvidia.com> Reviewed-on: http://git-master/r/89026 (cherry picked from commit b9e6316850a47445be7545aaec85c6a247c44cb9) Change-Id: I06d3c0f41e63d65f1908614d09df4d16028895f0 Reviewed-on: http://git-master/r/90030 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-03-15video: tegra: dc: Add rated refresh rate for one-shot mode.Kevin Huang
We add this variable for two purposes. First, it would remind developer to make sure actual refresh rate is larger than rated refresh rate. Second, gralloc would read rated refresh rate for one-shot mode since actual refresh rates of most devices are expected running at rated refresh rate. Bug 946370 Bug 934977 Change-Id: Ib4121337df1a388b40440b22687c39f373f08890 Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/89871 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-03-15video: tegra: dsi: Add phy timing check for hblankAnimesh Kishore
Horizontal blank must be greater than phy timing for HS transmission. Bug 938043 Change-Id: I5afe68ec04341f7b83c2897c586d4618bd518222 Signed-off-by: Animesh Kishore <ankishore@nvidia.com> Reviewed-on: http://git-master/r/89789 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jon Mayo <jmayo@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-03-15video: tegra: dsi: Fix phy timing HW incrementAnimesh Kishore
Adding support to accomodate hw increment to phy timing reg values. Bug 938043 Change-Id: I8de14648c0994b03c37a2ee455a656ff11c3cc34 Signed-off-by: Animesh Kishore <ankishore@nvidia.com> Reviewed-on: http://git-master/r/89741 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jon Mayo <jmayo@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-03-14video: tegra: dc: Fix the EMC bandwidth clear.Kevin Huang
Bug 951626 Change-Id: Ia7c7474aa0f066cba8bd1519a98e302c4b3992e0 Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/89076 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2012-03-08video: tegra: dc: Remove unnecessary delay in dc postsuspendMin-wuk Lee
Remove unnecessary 100ms delay for primary panel since this is needed for HDMI type only. Bug 940012 Change-Id: Id27966fb28faa73ade3a868a9f89cadbde76e227 Signed-off-by: Min-wuk Lee <mlee@nvidia.com> Reviewed-on: http://git-master/r/87613 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-03-08video: tegra: implement DC capabilities ioctlAdam Cheney
The returned capabilities bitfield is initially 0 (no caps). bug 942631 Change-Id: Ia7496981e525526147ecebe67b09dc877d3e0c17 Reviewed-on: http://git-master/r/87088 Tested-by: Adam Cheney <acheney@nvidia.com> Reviewed-by: Robert Morell <rmorell@nvidia.com>
2012-03-08video: tegra: dc: Fix the race condition of one-shot work.Kevin Huang
Add lock to prevent race condition between cancellation of old delayed work and schedule of new delayed work. Bug 936337 Change-Id: I52df82e92279163841546127c72be9879ef810d0 Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/86730 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-03-06video: tegra: dsi: fix DSI_PAD_CONTROL reg wr value on resumeBoris Suvorov
In panel resume path DSI_PAD_CONTROL value gets calibrated, however later on values are overwritten with bit settings for ulpm mode. refactor value for reg write to only change ulpm related bits. Change-Id: I9f9713bdf376c06b0e1b9f43b3e6c9f719bbd855 Signed-off-by: Boris Suvorov <bsuvorov@nvidia.com> Reviewed-on: http://git-master/r/85873 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-03-05video: tegra: dsi: Fix syncpt hang during early suspend cycleAnimesh Kishore
Fixing dsi syncpt hang issue after multiple cycles of early suspend-late resume. Bug 943096 Change-Id: Iefc0530a6e514b7733819dd1df35cde8f5c3dd47 Signed-off-by: Animesh Kishore <ankishore@nvidia.com> Reviewed-on: http://git-master/r/86946 Reviewed-by: Sang-Hun Lee <sanlee@nvidia.com> Tested-by: Sang-Hun Lee <sanlee@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
2012-02-28video: tegra: dc: Clear window option before window update.Kevin Huang
There exits an issue that if window number is less than DC_N_WINDOWS, window option of some windows won't be cleared. So although it should be disabled, it might not be disabled properly. This will lead to the failure of scan-out on screen. Bug 943846 Change-Id: I604399abaa590b27ab4ea41ed9eb2706be16a75a Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/86230 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-02-23video: tegra: dsi: Fix dsi phy timingAnimesh Kishore
Corrected the formulas to calculate phy timing. Added mipi d-phy constraints. Bug 938043 Change-Id: Ie1f2dd45e7e39f83735fe28e21a62dc0415c7c00 Signed-off-by: Animesh Kishore <ankishore@nvidia.com> Reviewed-on: http://git-master/r/85217 Reviewed-by: Jon Mayo <jmayo@nvidia.com> Reviewed-by: Krishna Yarlagadda <kyarlagadda@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-02-23video: tegra: dc: fix pixel clock latency issueKen Chang
GENERAL_ACT_REQ causes double-buffered registers to become active. This register needs to be programed to reduce the latency of pixel clock after dc enabled by tegra_dc_enable(). bug 926189 Signed-off-by: Ken Chang <kenc@nvidia.com> Reviewed-on: http://git-master/r/83346 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com> (cherry picked from commit f39c5ddd1867c508900c9aa2d4eead7eb3082343) Change-Id: I741c9be9074709c1ab571aa631cb462599d5fb78 Reviewed-on: http://git-master/r/84561 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-02-23video: tegra: dc: in continuous mode mask VBLANK after first frameNitin Kumbhar
A V_BLANK interrupt for each frame does not allow long lp2 idle intervals. If all windows are clean, mask V_BLANK interrupt after processing it for updating smart dimmer. It's unmasked again when a new window update is performed. This will schedule a work for updating smart dimmer for the new frame. Bug 920110 Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: http://git-master/r/85137 (cherry picked from commit 68398090aee22cf02069e5767c3e9a062b0fc2f6) Change-Id: I588328bfd0d6036febed236dc07f441878aa81d1 Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: http://git-master/r/85166 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com>
2012-02-21video: tegra: dc: use side-by-side stereo HDMI modeAndrija Bosnjakovic
Add a config option to limit HDMI stereo 3D output to 74.25MHz pixel clock. When this option is set, substitute the frame pack stereo modes for side-by-side (half) left-right stereo modes to meet this pixel clock restriction. By default, do not use it (use frame packed HDMI mode as usual). Bug 938807 Change-Id: I2ce2ca72cbb15ac1939af0f3386dd23650262435 Reviewed-on: http://git-master/r/84252 Reviewed-by: Andrija Bosnjakovic <abosnjakovic@nvidia.com> Tested-by: Andrija Bosnjakovic <abosnjakovic@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com>
2012-02-17video: tegra: dc: prevent nvmap_unpin crashMin-wuk Lee
This is a workaround to make sure serialization of flip worker, for Android specific. Android doesn't need mutiple workqueues per each window since it gets composited one from user layer. If the last windows' argument index is not 0, provided change will make the last index to 0 with swap operation so work will be queued into one workqueue all the time. Bug 929993 Bug 932592 Bug 933831 Bug 935623 Bug 934569 Change-Id: Ic467bb4f593c72ae98ea1fb324cf1a6d343faa62 Signed-off-by: Min-wuk Lee <mlee@nvidia.com> Reviewed-on: http://git-master/r/82971 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-02-16video: tegra: dsi: Config dsi and csi shared padAnimesh Kishore
Configure voltage regulator. Bug 914749 Change-Id: I6cf1924a928839249d4e62029dd14fca84b05792 Signed-off-by: Animesh Kishore <ankishore@nvidia.com> Reviewed-on: http://git-master/r/83361 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-02-16video: tegra: dsi: Soft reset if dsi host busyAnimesh Kishore
If dsi host is unexpectedly busy, soft resetting will restore controller state. Bug 930453 Change-Id: I1bbce55d0b27a2be80a66218978e73c616e9d894 Signed-off-by: Animesh Kishore <ankishore@nvidia.com> Reviewed-on: http://git-master/r/83986 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-02-15video: tegra: dc: protect dc extension disabling with a lockNitin Kumbhar
When dc gets many underflows, instances of reset worker can race to perform reset. dc ext was getting disabled outside critical region affecting display path. disable dc ext after getting the lock. Bug 936545 Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: http://git-master/r/83108 (cherry picked from commit f9dcf7eee8ca8db28cee6fa9550044d1f746e843) Change-Id: Ie29dc66eb52c9be472c2d0db8c0014bfe1837ad4 Reviewed-on: http://git-master/r/83406 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-02-15video: tegra: dc: Schedule delayed work to clear emc bandwidth.Kevin Huang
Bug 932840 Change-Id: I12d8d2d2cd42d0dafea38463ad77b44f7e64d7c1 Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/83645 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-02-14video: tegra: dc: acquire window locks in an order to avoid a deadlockNitin Kumbhar
All window locks are grabbed while performing dc window updates. Currently, no particular locking order is followed for these locks. If user provided windows are not in order, this leads to deadlock due to race between flip ioctl and dc underflow reset worker. Now on all window locks are acquired in an order as below 1. window A i.e. index 0 2. window B i.e. index 1 3. window C i.e. index 2 And unlocked in the reverse order 1. window C i.e. index 2 2. window B i.e. index 1 3. window A i.e. index 0 Bug 936545 Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: http://git-master/r/83107 (cherry picked from commit 68815fa87e879d0c783e8fd38f473f414806c0be) Change-Id: I3b3e00eaf91384c39ff74047f06af8199848ad92 Reviewed-on: http://git-master/r/83405 Tested-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com> Reviewed-by: Robert Morell <rmorell@nvidia.com>
2012-02-13video: tegra: dc: Activate dc registers properly for one-shot mode.Kevin Huang
Enable GENERAL_ACT_REQ and HOST_TRIG_ENABLE at the same time. Bug 930840 Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/78638 (cherry picked from commit 2f78c8e3c243b4c866ad54a550167abd94c200c1) Change-Id: If0ef97c4a2b1a0621152c02728edbbed064a5e34 Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Reviewed-on: http://git-master/r/82715 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Tested-by: Varun Wadekar <vwadekar@nvidia.com>
2012-02-13video: tegra: dc: enable dc ext from underflow reset workerNitin Kumbhar
DC ext is enabled only from _tegra_dc_controller_enable() which is not used from reset worker. Enable dc ext from _tegra_dc_controller_reset_enable() as well. Bug 933391 Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: http://git-master/r/78753 (cherry picked from commit a099c612f91cc12a99325e39609b1f9001525be0) Change-Id: Ia95df85ea602174c2fd66888b21f7a6d264c176e Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Reviewed-on: http://git-master/r/82714 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Tested-by: Varun Wadekar <vwadekar@nvidia.com>
2012-02-13video: tegra: dc: Ignore suspend if DSI is disabledTerje Bergstrom
DSI enables during suspend time host1x, and then checks if DSI is really enabled. Now DSI first checks if it's enabled. If yes, it'll turn on host1x and disable it. Bug 887332 Change-Id: I206f908a62d0a56f0737c31634fa46613ca07d7e Reviewed-on: http://git-master/r/82755 Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Animesh Kishore <ankishore@nvidia.com> Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2012-02-10video: tegra: hdmi: Enable HDA NULL sample inject supportSumit Bhattacharya
When HDMI NULL sample injection is enabled codec inserts null samples into the audio FIFO for each Azalia frame in which it did not receive any samples. This support is needed to prevent audio loss for HDMI devices from some vendor(e.g. sony). Bug 924926 Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com> Reviewed-on: http://git-master/r/79227 (cherry picked from commit 898fd83d94506de3bd604f75d25084d9bcb6dd9e) Change-Id: I81f55cab52c92377b49ab94635c8e8aa394b6739 Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Reviewed-on: http://git-master/r/82724 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Sumit Bhattacharya <sumitb@nvidia.com> Reviewed-by: Sumit Bhattacharya <sumitb@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Tested-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-by: Scott Peterson <speterson@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com>
2012-02-03video: tegra: dc: Call display client disable before dc irq disableAnimesh Kishore
dc irqs are required in display client disable to flag stopping of dc stream. Bug 930453 Reviewed-on: http://git-master/r/77808 Change-Id: I0e057ca14078d9e608cb32380123fade813c4041 Signed-off-by: Animesh Kishore <ankishore@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/78898 Reviewed-by: Automatic_Commit_Validation_User
2012-02-03video:tegra:hdmi: skip useless checkColin Patrick McCabe
Don't check if dc is NULL after we've already dereferenced it. Reviewed-on: http://git-master/r/63647 Change-Id: I0af6c829b6143b21a1f7de47a1ccfeac4bda99e0 Signed-off-by: Colin Patrick McCabe <cmccabe@nvidia.com> Signed-off-by: Jon Mayo <jmayo@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/78434 Reviewed-by: Automatic_Commit_Validation_User
2012-01-30video: tegra: host: CPU reg read to use power managementTerje Bergstrom
CPU register read did not have access to nvhost power management. Due to this only modules that were powered on previously are actually accessible via the API. This patch refactors CPU access to: * Move mutexes to sync point, as they're sync point operations * Move register address spaces to nvhost_device * Call register read with access to the respective nvhost_device * Initialize module completely at boot-up so that register reads can be done without an initialized channel. Reviewed-on: http://git-master/r/75275 Change-Id: I0db38cef7b2cd92dc64e7f55d227bdd2fdb8f752 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/77764 Reviewed-by: Automatic_Commit_Validation_User
2012-01-30video: tegra: dsi: Refine the DSI clock calculation.Kevin Huang
Reviewed-on: http://git-master/r/76406 Change-Id: I6e5b37a88d6be4ba2cc81417fe3eadfd129bc899 Signed-off-by: Kevin Huang <kevinh@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/77306 Reviewed-by: Automatic_Commit_Validation_User
2012-01-24video: tegra: dc: Add dc backup clock source supportAlex Frid
Add backup clock source option in dc platform configuration. Use backup source if fixed frequency pllp is specified as main source, but its rate can not be divided into pixel clock within required tolerance. 928260 Change-Id: I19bd9173276c6ea087f86361956809787875e979 Reviewed-on: http://git-master/r/76033 Signed-off-by: Alex Frid <afrid@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/76818 Reviewed-by: Automatic_Commit_Validation_User
2012-01-24video: tegra: host: Access nvhost_master via drvdataTerje Bergstrom
Use standard drvdata interface for storing and accessing nvhost_master. Reviewed-on: http://git-master/r/72846 Change-Id: I191987c8f6d313a6ede9b59f723269cb6a197e8a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/76815 Reviewed-by: Automatic_Commit_Validation_User
2012-01-24video: tegra: dc: enable emc clock on probeNitin Kumbhar
When dc->emc_clk_rate goes from 0 to non-zero the dispX.emc clock is enabled. This works with the sequence for probe and hotplug to have emc clock in the correct enable/disable state. Bug 927785 Bug 917769 Reviewed-on: http://git-master/r/76208 Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Signed-off-by: Jon Mayo <jmayo@nvidia.com> Change-Id: I53cc8c5091967ce021dd3ec1e2bc75405dc8c45c Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/76813 Reviewed-by: Automatic_Commit_Validation_User
2012-01-19video: tegra: dc: 1-shot bandwidth calculationJon Mayo
In one-shot mode(DSI) report emc rate as disabled to reduce bandwidth in this idle state. Use this same tegra_dc_clear_bandwidth() function to handle display disable for all types of displays. Bug 914917 Change-Id: I84ca1341d71999b3558f9dadb103b258a1a6ab6f Signed-off-by: Jon Mayo <jmayo@nvidia.com> Reviewed-on: http://git-master/r/74652 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com> Tested-by: Xin Xie <xxie@nvidia.com> Reviewed-on: http://git-master/r/75536 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-01-16Revert "video: tegra: dc: fix DSI pclk calculation"Jon Mayo
This reverts commit 20f43dfc590d22ad1e80b7b948f108b17038b084. Conflicts: drivers/video/tegra/dc/dc.c This fix is no longer needed to boot. Change-Id: Ie8d877207b6a1d70c63834f234d7a7cc68a372bf Signed-off-by: Jon Mayo <jmayo@nvidia.com> Reviewed-on: http://git-master/r/74884 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com> Reviewed-on: http://git-master/r/75151 Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Tested-by: Varun Wadekar <vwadekar@nvidia.com>
2012-01-16video: tegra: dc: consolidate underflow codeJon Mayo
Move underflow handling out of the irq handler and into a workqueue. Change-Id: I289d0a4c4e632a229e46d8e7f82e637409813807 Signed-off-by: Jon Mayo <jmayo@nvidia.com> Reviewed-on: http://git-master/r/74427 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Reviewed-on: http://git-master/r/75143 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-14 20:01:32 +0000