| Age | Commit message (Collapse) | Author |
|---|
|
Use nvmap.h include file from kernel/include instead of mach-tegra/include.
Bug 854182
Change-Id: I9a44471dc77d1ed7aa3b6e61a5eca4833fe6dc25
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/102721
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
|
|
Currently nvhost hard codes usage of context handler and sync point
id. Split the context handler and context structures into generic and
host1x specific parts, and move the allocation to happen via a
function pointer in nvhost_device.
Also updates gr3d and mpe to use sync point id and waitbase from
nvhost_device.
Bug 926690
Change-Id: I7f00b450cac99f3816baa27b37ee4e4cf68cfe24
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/84901
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
|
|
Replace license information in nvhost with GPLv2. Also adds
copyright year 2012 in files which have been changed in 2012.
Change-Id: I86e8ed27095df13d99e0250e57e244d531fdacec
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/89735
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
|
|
Timeout struct contains fields which are accessed even after client has
quit. Move the fields to hwctx and nvhost_job so that they can be
accessed when submits complete.
Bug 917340
Change-Id: I322c38d32bc801aa9b061355a17be7f605692e18
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/71004
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
|
|
Separate Tegra2 and Tegra3 code paths for 3D context switching.
Bug 839973
Original-Change-Id: I5cfece1c9835a3de329f390aed55c47ad00f87e8
Reviewed-on: http://git-master/r/46887
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Rebase-Id: R715b9728fe01cb391f258e374f83d098c14ea874
|
|
In this change, nvhost_cdma starts a timer (if a timeout is specified
in the userctx), for the buffer at the head of the sync_queue that has
not reached its syncpt threshold.
If the timeout fires, nvhost_cdma initiates a channel / module reset.
It then detects up to where in the sync_queue it stopped execution
(based on the current HW syncpt value).
For any remaining uncompleted buffers in the context, nvhost_cdma NOPs
the entry and CPU incrs the syncpt to where it should be had it completed.
If one of the sync_queue entries belongs to another context, it still
does the syncpt incrs for this context, but via the PB as a GATHER opcode,
At the end, CDMA is restarted, so buffers are refetched (either with
NOP slots, or GATHERs to incr syncpts). This appears as though the
buffer has completed (and the associated resources released).
For testing, debugfs entries have been added under /d/tegra_nvhost
force_timeout_val - set the timeout value, in ms
force_timeout_channel - channel ID, were timeouts checks occur
force_timeout_pid - process ID to set the userctx
The idea is to set the timeout_val, then the timeout_channel (e.g. for
3D, the channel ID is 1) and then the process ID, gotten from running
adb shell ps.
Bug 625545
Original-Change-Id: I659e9255f1105f3439ce23e9169a19739b83ea52
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/42655
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R89759c129e2db8f7dbf83a6066fc29947f95cc27
|
|
To prepare for kernel modularization, nvhost include files need to be
moved from mach-tegra/include to kernel/include. At the same time
user space specific part is split into nvhost_ioctl.h.
Bug 854182
Original-Change-Id: I3694a40d786028733310ecf5b59341282af571be
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/43211
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Rc4fadf65d59ddfb5bb924e7adfccd39e86a0b2c7
|
|
Original-Change-Id: Ia203886a3b013612b4159393ff43a25a313d1ece
Reviewed-on: http://git-master/r/35911
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R01b763362c13e09111f60700c3d3a7d2a9a3fc1c
|
|
Original-Change-Id: I158d2be97c795313e7e74ce9fb4ec0bdc7d95496
Reviewed-on: http://git-master/r/27559
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Hiro Sugawara <hsugawara@nvidia.com>
Reviewed-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I0ff198daa548ed2837f7fb1794013bf0adf7e5a1
Rebase-Id: R83df5f3b5104183bfe774d8eed8ce94427c9b7fc
|
|
Adding support for Tegra3:
* auto context save (without FIFO reading in interrupt)
* new registers
* SLI
Note: currently hardcoded to Tegra3, SLIx2. Need query function.
Original-Change-Id: I7daff768540ac0f0af12a655a664428a3ae55665
Reviewed-on: http://git-master/r/12564
Tested-by: Andrew Howe <ahowe@nvidia.com>
Tested-by: Jussi Rasanen <jrasanen@nvidia.com>
Reviewed-by: Andrew Howe <ahowe@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I42bfa94856676bfd82b4c11cc8cf523ca2c0dbe6
Rebase-Id: R9b1f81b7a0323f87a4c13804e483383595971550
|
|
the graphics and display hardware on tegra SoCs is accessed
through a command DMA front-end called host1x
host driver clients place commands into memory objects called
streams, and submit a stream on one of 8 channels: the assignment
of streams-to-channels depends on the hardware module(s) programmed
by the stream: for example, all streams which program the 3D
hardware are submitted on channel 1.
the host1x hardware includes two synchronization primitives to
allow command streams to synchronize access to memory or to
hardware engines shared across channels (e.g. the 2D blitter):
sync points and module mutexes. both primitives can also be
used to synchronize with the CPU.
the host1x driver performs power management for all modules
behind the host block: once a module is idle (i.e., the
last stream which accesses it has completed, indicated by
a syncpoint) and has remained idle for an extended period
of time, the module's clock (and power gate island, if the
module is uniquely power-gated) is disabled, and will be
automatically re-enabled when a new stream is submitted for
that module.
includes channel debugging support originally implemented
by Erik Gilling <konkers@google.com>
Original Author: Antti Hatala <ahatala@nvidia.com>
Signed-off-by: Gary King <gking@nvidia.com>
Change-Id: Idf0ecc8e7710f3839903a9fbfbe5650990a96b2c
|
