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path: root/drivers/video/tegra/host/t30
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2012-06-19video: tegra: host: Support per Soc hardware headersTerje Bergstrom
Make all chip specific functions static. Include the chip specific functions in SoC files after including the hardware headers. This makes the chip specific functions to be compiled per SoC, and with the correct hardware definitions. Bug 982965 Change-Id: I4774d4dc351951cb886d9d4da66cf021f3f0121e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/107581 Reviewed-by: Automatic_Commit_Validation_User
2012-06-14video: tegra: host: Remove version from dev nameTerje Bergstrom
Remove version from nvhost_device name, and use a new field, version, to distinguish between IP versions. This restores the sysfs API for 3D clock scaling back to its original path. Change-Id: I444ef728b7cab9e5ea3a08f3c7be0f1661209686 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/108501 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-06-14video: tegra: host: Parametrize host1xTerje Bergstrom
Add parameters in host1x nvhost_device on * number of sync points * number of wait bases * number of channels * number of mlocks * client managed bitmask * naming of sync points Add automatically generated headers and use symbols from them to access hardware. Move host1x device definition from generic host1x to SoC specific source files t20.c and t30.c. Bug 982965 Change-Id: Ibec84be22d75b363900d10bcbd59d4d8321d54a1 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/104974 Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
2012-06-14video: tegra: host: Register devices in SoC filesTerje Bergstrom
Move the device structures to the driver source code files. Register all nvhost_device's in one loop which is called from board file. host1x driver code is moved to live under host1x, too. This causes a need to add host to include path of tegradc and nvavp. Bug 982965 Change-Id: If99cf9d1ef6bc24663ee8294c19370429ed04ca7 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/104076 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-06-11video: tegra: host: Abstract nvmap supportTerje Bergstrom
Abstract nvmap support to one file, and use it via function pointers from other parts of nvhost. Bug 965206 Change-Id: I4e5e7de4271e0797d117ac8210af4732b6018973 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/105665 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
2012-05-25Revert "video: tegra: host: t30: use max 2d clock"Wen Yi
This reverts commit 5bdd03b21f625d0a07c66e4894b79e557287a3a1. The reverted commit kept vcore at 1.2 volts whenever 2D engine is on and increased power consumption for use cases that utilize 2D but doesn't require its full speed. Bug 979545 Change-Id: I4297ab1fb83558501ff620952284c8590dc5f1dd Signed-off-by: Wen Yi <wyi@nvidia.com> Reviewed-on: http://git-master/r/104293 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Donghan Ryu <dryu@nvidia.com> Tested-by: Donghan Ryu <dryu@nvidia.com> GVS: Gerrit_Virtual_Submit
2012-05-23video: tegra: host: move function pointers to nvhost_driverMayuresh Kulkarni
- currently, function pointers are inside nvhost_device - these functions abstract the device specific implementation of a functionality per SoC - move them to nvhost_driver so that nvhost_device can be instantiated from arch code using board files/device trees - add support to use single driver for multiple devices using concept of id_table. this will be useful in supporting multiple SoC devices binding single driver - also add some notes about how device name is expected Bug 871237 Change-Id: I4c75d7121d26c3bdc50f058e0d144d89ca0edbd9 Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-on: http://git-master/r/100985 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-05-17video: tegra: host: remove nvhost_channel from nvhost_masterMayuresh Kulkarni
- nvhost_master holds a reference to all the channels for a chip architecture - however, nvhost_master is a private data of host1x hardware device. so it should contain only members needed by host1x hardware device - add chip specific apis to allocate and free channels - this will also help to remove the static binding between nvhost_device and a channel per SoC in future Bug 871237 Change-Id: I2148db57b995b4cb60954ebb6e670f588552eca4 Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-on: http://git-master/r/91687 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2012-05-11video: tegra: host: move chip_support out of nvhost_masterMayuresh Kulkarni
- currently, nvhost_master holds the reference to struct chip_support - the struct chip_support hides the chip specific implementation for channel submit, cdma, push buffer operations etc. so it exposed all the internal structures through nvhost_master - move chip_support to be a part of nvhost_bus since it only has function pointers to chip specific api implementations - nvhost_master is host1x device specific private data so ideally it should not hold reference to chip specifics Bug 871237 Change-Id: I4f3f48ee5fc47a90288d110ea8eef905150275a0 Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-on: http://git-master/r/94421 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
2012-05-08video: tegra: host: Iterate devices without nb_channelsTerje Bergstrom
Do not use nb_channels to find out the number of client devices. Instead, allocate devno regions when they are needed and find a device by module id by iterating over nvhost bus. Bug 871237 Change-Id: I53fd0d8e5874422ef9877430c0a170db2660118a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/99067 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
2012-05-04video: tegra: host: Clean up includesTerje Bergstrom
Clean up #includes. Replace #includes with forward declarations where possible, and remove extraneous #includes. Bug 871237 Change-Id: I6942e0c632b42ad7009589ebdd78def88ae4baa4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/99046 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
2012-05-01video: tegra: host: t30: use max 2d clockDonghan Ryu
setting max 2d clock can make noticeable performance difference in 2d limited usecase such as buffer clearing Change-Id: I40ef999e7eeebff45b657f00293608561cae831d Signed-off-by: Donghan Ryu <dryu@nvidia.com> Reviewed-on: http://git-master/r/98644 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-04-26video: tegra: host: Reset 3D after power onTerje Bergstrom
Sometimes 3D unit comes up with incorrect scissor configuration. Earlier patch added the scissor registers to the context save list, but that did not solve the problem. Remove the extra registers, and reset 3D after powering it up. Bug 939307 Change-Id: Id795f2d99ec3c6b907da2785b1816ce753af7a3f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/87654 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Graziano Misuraca <gmisuraca@nvidia.com> Tested-by: Graziano Misuraca <gmisuraca@nvidia.com> Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com> Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
2012-03-21video: tegra: host: refactor for upstreamingMayuresh Kulkarni
- split the nvhost clients into their own directories - each client is a nvhost_device and nvhost_driver - all the code related to host1x control node is centralized at single place in dev.c - all the code related to host1x modules nodes is centralized at single place in bus_client.c - update the copyright notice & year for new files Bug 871237 Change-Id: Ief85064699e35ad02b48a7e54496928d7f085af4 Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-on: http://git-master/r/83491 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-03-18video: tegra: host: disable 3d powergatingDonghan Ryu
this is a workaround for the SLI scissor bug which can happen intermittently. Bug 914785 Change-Id: I5b7071df5bbfdd03bfe8b6f6b12ac7279221bd4e Signed-off-by: Donghan Ryu <dryu@nvidia.com> Reviewed-on: http://git-master/r/87968 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
2012-03-15video: tegra: host: Refactor context handling logicTerje Bergstrom
Currently nvhost hard codes usage of context handler and sync point id. Split the context handler and context structures into generic and host1x specific parts, and move the allocation to happen via a function pointer in nvhost_device. Also updates gr3d and mpe to use sync point id and waitbase from nvhost_device. Bug 926690 Change-Id: I7f00b450cac99f3816baa27b37ee4e4cf68cfe24 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/84901 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-03-15video: tegra: host: Replace license informationTerje Bergstrom
Replace license information in nvhost with GPLv2. Also adds copyright year 2012 in files which have been changed in 2012. Change-Id: I86e8ed27095df13d99e0250e57e244d531fdacec Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/89735 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-03-07video: tegra: host: Set 3D pg timeout to 250msTerje Bergstrom
Power gating timeout for 3D is too short, and causes oscillation in non-idle use cases. Increase timeout to 250ms to get more benefits from power gating. Bug 914785 Change-Id: I4e37fda260ceecc2fe3e21989789105b7c8fcf36 Reviewed-on: http://git-master/r/87659 Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-by: Ilan Aelion <iaelion@nvidia.com> Reviewed-by: Graziano Misuraca <gmisuraca@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2012-01-30video: tegra: host: CPU reg read to use power managementTerje Bergstrom
CPU register read did not have access to nvhost power management. Due to this only modules that were powered on previously are actually accessible via the API. This patch refactors CPU access to: * Move mutexes to sync point, as they're sync point operations * Move register address spaces to nvhost_device * Call register read with access to the respective nvhost_device * Initialize module completely at boot-up so that register reads can be done without an initialized channel. Reviewed-on: http://git-master/r/75275 Change-Id: I0db38cef7b2cd92dc64e7f55d227bdd2fdb8f752 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/77764 Reviewed-by: Automatic_Commit_Validation_User
2012-01-19video: tegra: host: Fix includesJuha Tukkinen
Remove one duplicate include and relative paths in includes. Replace one include with forward declaration. Make dependencies to t20 and t30 explicit. Change-Id: I195020bedbb46277dbd6a92b65be2cde5f6276b8 Reviewed-on: http://git-master/r/72903 Signed-off-by: Juha Tukkinen <jtukkinen@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/75885 Reviewed-by: Automatic_Commit_Validation_User
2012-01-12video: tegra: host: Move device data to nvhost_deviceTerje Bergstrom
Move all device data from nvhost_channeldesc, nvhost_moduledesc and nvhost_module to nvhost_device. nvhost_devices are also assigned into a hierarchy to prepare for implementation of runtime power management. Change-Id: I1e18daae8fe538086cd1f453d316e0f73e9d7d92 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/72844 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Reviewed-on: http://git-master/r/74560 Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Tested-by: Varun Wadekar <vwadekar@nvidia.com>
2012-01-04video: tegra: host: Move host1x code into own directoryTerje Bergstrom
Move source files related to host1x into an own directory. Bug 871237 Change-Id: I6fa3ef057f8b788c37dd2ab698271cf7508711c6 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/71783 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com>
2011-12-30video: tegra: host: Move 3D code into own directoryTerje Bergstrom
Move source files related to gr3d into own directory. Bug 871237 Change-Id: I5118ad792d6ec136d2ec2575eff931e112d5f3b2 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/71782 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
2011-12-30video: tegra: host: Move MPE files into own directoryTerje Bergstrom
Separate source code related to mpe into an own directory. Bug 871237 Change-Id: I59251752119660bb1e57e1763626fa289a2b9f5b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/70531 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
2011-12-30video: tegra: host: Replace magic numbers with constantsTerje Bergstrom
Replace magic numbers with constants throughout the code base. Change-Id: If6071f3ee95078d7b631a300b241ebf6522ef68a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/66795 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
2011-12-21video: tegra: host: Remove T30 A01 workaroundJuha Tukkinen
As T30 A01 is no longer supported, remove T30 A01 workaround. Bug 915655 Signed-off-by: Juha Tukkinen <jtukkinen@nvidia.com> Change-Id: I17ebb252bad2c8a67fcb2b7ef1a40a1b3738a026 Reviewed-on: http://git-master/r/70014 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com> Tested-by: Juha Tukkinen <jtukkinen@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2011-12-21video: tegra: host: Register all clients as devicesTerje Bergstrom
Register all host1x client modules as devices to kernel, and a matching driver for each of them. Change-Id: Id3ab2adc860fabfcc1595e0a5dbaeb07575e19e8 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/69996 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Ken Adams <kadams@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2011-12-15video: tegra: host: scale 3d.emc with 3d.busIlan Aelion
3d.emc clock will be scaled proportionately to the rate chosen for 3d.cbus clock. Bug 911223 Change-Id: I903ad7e3f6c33c3d3119e8b9810839edb1084596 Signed-off-by: Ilan Aelion <iaelion@nvidia.com> Reviewed-on: http://git-master/r/69021 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-12-15video: tegra: host: max emc rate when 3d is onDonghan Ryu
Currently, EMC rate is mostly controlled by CPU frequency assuming that higher CPU freqeuncy requires more mem B/W. However, some of the 3d apps makes GPU very busy while CPU is mostly idle. This patch changes HOST_EMC_FLOOR to UINT_MAX allowing GPU to utilize full mem B/W when it is active. This may be re-visited when 3d scaling is enabled since we might be able to scale EMC rate dynamically based on 3d rate. Bug 911223 Change-Id: I8eb7b3991abe3bd664441bfc1f43075984dafcaa Signed-off-by: Donghan Ryu <dryu@nvidia.com> Reviewed-on: http://git-master/r/68650 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-12-15video: tegra: host: Enable multiple MPE contextsTerje Bergstrom
Enable multiple contexts for MPE. Bug 827192 Change-Id: I112ddbdc099efdce3f214161ae454bce34158dc7 Reviewed-on: http://git-master/r/69690 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com>
2011-12-15video: tegra: host: Implement MPE context switchTerje Bergstrom
Implement context switching for MPE. This allows doing multiple video encodings at the same time. Context switching relies on wait base being in sync with sync point. As MPE user land does not use wait bases, the patch also enables automatic wait base syncing. This patch does not enable the context save/restore. Bug 827192 Change-Id: I510c02fb6d02ffbc1b9537d33474d46022b6cf59 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/66881 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2011-12-08video: tegra: host: allow user to enable scalingIlan Aelion
change file permissions to allow a user application such as the control panel to enable or disable scaling. Cherry-picked from: http://git-master/r/#change,56479 Change-Id: I99d7dc76b82fcdf78ab0e9c387108b648adf488d Signed-off-by: Daniel Solomon <daniels@nvidia.com> Reviewed-on: http://git-master/r/64288 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2011-12-08video: tegra: host: adjusted 3d frequency scalingIlan Aelion
count scale up / down hints to adjust scaling parameters. Reviewed-on: http://git-master/r/#change,60338 (cherry picked from commit 093d16d905e7bd299c6fb1d627b6e8317ed8c714) Change-Id: Ie4716570a2bfcb82fd595932eef94102364fb18a Reviewed-on: http://git-master/r/63719 Tested-by: Ilan Aelion <iaelion@nvidia.com> Reviewed-by: Luke Huang <lhuang@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
2011-11-30video: tegra: host: Enhance FIFO/GATHER debug_dumpTerje Bergstrom
Enhance nvhost_debug_dump() output, as follows: - Swap FIFO and GATHER dump so that even if GATHER dump blows out seq_printf 1k buffer, we still have FIFO information; - Write FIFO signature pattern (0xd???d???) to indirect save input data to help pinpoint FIFO position within debug dumps; - Prevent long data sequences from blowing out the seq_printf 1k buffer, by limiting such sequences to 64 words. Change-Id: I83f6118f8af14a6c46fd1080c03b718a7a3bc66c Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/62424 (cherry picked from commit cb37e4212b78546411b33b32044f30feb0579b86) Reviewed-on: http://git-master/r/63788 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: R39329ae8eb252ced3da604e4f33c272e26921d27
2011-11-30gcov-kernel: Add GCOV_KERNEL := y to MakefilesJuha Tukkinen
These changes have no effect if CONFIG_GCOV_KERNEL is not set in defconfig. It is easier to trigger GCOV for kernel if this patch is in by only setting the before mentioned flag. Change-Id: I8aade309da2da62c4b3889bd84e4123ba8f182da Signed-off-by: Juha Tukkinen <jtukkinen@nvidia.com> Reviewed-on: http://git-master/r/62999 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Rebase-Id: R4c238f707f1db600f188ae83426336753992b7be
2011-11-30video: tegra: host: Enable powergating for MPE and 3DTerje Bergstrom
Enable power gating for MPE and 3D in T30. Bug 857044 Reviewed-on: http://git-master/r/62101 (cherry picked from commit 4fd4d2a948450f04181179f5f1e4da7b6c9e3060) Change-Id: I031324f6d45afc11cb056fa0f26932f7f7767417 Reviewed-on: http://git-master/r/63225 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R96f7986af5b534d8db0ff2a1f119f5f783d6ed44
2011-11-30video: tegra: host: fixes to 3d clock scalingIlan Aelion
fixed bug in scale up timing, improved idle time reporting and scaling parameters. Reviewed-on: http://git-master/r/55849 Reviewed-by: Karan Jhavar <kjhavar@nvidia.com> Tested-by: Karan Jhavar <kjhavar@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> (cherry picked from commit b73fc6951192a2c80ed8d22f7ca4739b6e1e46de) Change-Id: I6a04eb9ce789c475a461e9cc7306d679f209ed97 Reviewed-on: http://git-master/r/60443 Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Tested-by: Ilan Aelion <iaelion@nvidia.com> Rebase-Id: Rf34f9567d9b39ebd2e18742c8e3543d144b2de6f
2011-11-30video: tegra: host: Separate clk and power gatingTerje Bergstrom
Separate clock and power gating from each other. There are now two timeout values related to power management: * clockgate_delay: how long to wait before clock gating * powergate_delay: when to save context and power gate If the module does not support power gating, that state is not used. System suspend also explicitly power gates all channels before suspending host1x. Bug 875675 Change-Id: Id27f0fca7914ca2a135b27f623cb67af8a94a0ef Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> (cherry picked from commit eda8a5ccc474bc60d76e241f292573a8b6f30ab6) Reviewed-on: http://git-master/r/59077 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Ra935e74f68b3d56479be1105e9858f2248ef6cd6
2011-11-30nvhost: Add host module clock functionality for T20/T30Vandana Salve
This includes Get/Set clock rate functionality. Removed the abstraction and added functionality for T20 and T30 into nvhost_acm file Bug 887263 Change-Id: I2e8ad3d96fcc3711f99f9aa42150e7d4588910fa Reviewed-on: http://git-master/r/58654 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Vandana Salve <vsalve@nvidia.com> Tested-by: Vandana Salve <vsalve@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: R5aebeda335d753d23b0e8704dea949ccf0f7303e
2011-11-30video: tegra: host: Check for allocation failuresTerje Bergstrom
Adds checks for memory allocation failures, and proper propagation of error conditions. Adds clearing of pointers after free or unpin has been called to catch use after free. Bug 877551 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/54027 Reviewed-by: Antti Miettinen <amiettinen@nvidia.com> Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Tested-by: Gerrit_Virtual_Submit (cherry picked from commit bfbf2766d11a5f85781532ddce3a87b7ae762ba3) Change-Id: I04171ee5db6a42bb1689221d4f80d5f3d35e7399 Reviewed-on: http://git-master/r/57462 Rebase-Id: Rc9f43312c8b818869d746f4b73700d8b56e4569d
2011-11-30nvhost: Modularize ACM codeTerje Bergstrom
Refactor nvhost_acm.c so that module specific code can be separated from generic code: * Module clock and power op descriptions added to channelmap table * New module busy/idle interface added * 3D clock scaling for Tegra3 moved behind the module busy/idle API * 3D power off code moved to 3dctx where it belongs * Module power on API removed as there were no users * Get/Set rate moved to Tegra3 specific file Bug 870791 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/51275 Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> (cherry-picked from ebea06768d9c9d351a7d1c8dc6499c97f2f5002d) Change-Id: I5857c7db4bbf936a694239a4a3493f2cb95426a1 Reviewed-on: http://git-master/r/56268 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Reaccd277c8f4fe12a4f7453cc4e787334122a3b8
2011-11-30tegra: nvhost: Retrieve phys address from nvmapTerje Bergstrom
Debug code used to rely on being able to calculate the base address of a pinned page by masking it. Now we always retrieve the physical address from nvmap and find the correct command buffer using that. Bug 840976 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/48105 Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> (cherry picked from commit 0ef5f2d4d94464b8d5562327c9cf5b56fe93fff5) Change-Id: I1a17665cf19d8758f154d4fd05f6a5ec6c07caff Reviewed-on: http://git-master/r/56266 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R12cdbf7b335ca46cd063cdf9dd7783b18255a3f1
2011-11-30tegra: host: Separate Tegra2/3 code paths for 3DTerje Bergstrom
Separate Tegra2 and Tegra3 code paths for 3D context switching. Bug 839973 Original-Change-Id: I5cfece1c9835a3de329f390aed55c47ad00f87e8 Reviewed-on: http://git-master/r/46887 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: R715b9728fe01cb391f258e374f83d098c14ea874
2011-11-30tegra: nvhost: Runtime retrieval of chip typeTerje Bergstrom
Use tegra_get_chipid() to the chip type at run-time instead of own code based on build-time flags. Bug 839973 Original-Change-Id: Iecb20be2bdc909627d4dd096a735518ba9cb2976 Reviewed-on: http://git-master/r/46886 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: Rade4bdd18721b7db9085358f1e5792b2d5747247
2011-11-30video: tegra: refactor for multiple chip supportKen Adams
Original-Change-Id: Ia203886a3b013612b4159393ff43a25a313d1ece Reviewed-on: http://git-master/r/35911 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R01b763362c13e09111f60700c3d3a7d2a9a3fc1c
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-18 01:22:26 +0000