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Sometimes 3D unit comes up with incorrect scissor configuration.
Earlier patch added the scissor registers to the context save list,
but that did not solve the problem. Remove the extra registers, and
reset 3D after powering it up.
Bug 939307
Change-Id: Id795f2d99ec3c6b907da2785b1816ce753af7a3f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/87654
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Graziano Misuraca <gmisuraca@nvidia.com>
Tested-by: Graziano Misuraca <gmisuraca@nvidia.com>
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
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Bug 951349
Change-Id: I79fb2e49fa38b83af78323b5f5cf6dbca8fd83c2
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/98512
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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Bug 953210
Change-Id: Id40b3fe90174a2a8c9a6faf3f35f61d9f7eeb642
Signed-off-by: Sayak Ghosh Choudhury <sayakc@nvidia.com>
Reviewed-on: http://git-master/r/98477
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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Inform DC register updated after we programmed. This eliminates
the display corruption while device enters and resumes from LP0.
Signed-off-by: Mark Zhang <markz@nvidia.com>
bug 964626
Change-Id: I4c655d4800474c675d4cdb6204d6fe66e8c6c4b5
Reviewed-on: http://git-master/r/98336
Tested-by: Mark Zhang <markz@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Peer Chen <pchen@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
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This change adds check for out of memory conditions
after memory allocations
Bug 967504
Change-Id: Icafc16528880ea376dd69a023570b85c25e3d057
Signed-off-by: Anton Kondratenko <akondratenko@nvidia.com>
Reviewed-on: http://git-master/r/97113
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Change-Id: I8aa25b03fe6801882b65209cb1a6e125ef27ac2c
Signed-off-by: Michael I. Gold <gold@nvidia.com>
Reviewed-on: http://git-master/r/98319
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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add trace_printk to log useful debug information.
Bug 870685
Change-Id: I29c0b1600f234ebb06d19c8b6c713b16f6e7643c
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/89204
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Prashant Malani <pmalani@nvidia.com>
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TEGRA_DC_EXT_SET_LUT programmed the proper shadow registers
but did not copy the shadow registers to the active set.
Signed-off-by: Adam Cheney <acheney@nvidia.com>
bug 947281
Change-Id: Id734e128bb708f1a75c0cad22b0c51b083d8df3b
Reviewed-on: http://git-master/r/91368
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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Change-Id: Ib1b0fc6015a9dd45982a97231972dadba6b5a92e
Reviewed-on: http://git-master/r/96966
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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This is necessary to introduce DMA iommu mapping API in nvmap.
Change-Id: I9c043460ca08cc25c4688811a2021820aed5c9f7
Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/96378
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
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Provide /sys/class/graphics/fb0/device/nvdps to change video mode
on-the-fly without resetting window layout like fb_set_var(). This
allows flicker free changes in refresh rate.
nvdps sysfs file takes an integer, and selects the closest matching mode
with the same or higher refresh rate. Reading the file displays the
current refresh rate.
Bug 560152
Change-Id: Id5c1eafaf338b99fa9742202b38ccbfc238b77d5
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/95473
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
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Handle mode set for FBIOPUT_VSCREENINFO at the end of a frame (during
vblank). This elimiates the work around that requires disabling then
enabling display to change modes.
Adds a spinlock to protect irq code from updates to tegra_dc_mode structure.
Bug 560152
Change-Id: I5d2175f01a177a32d685b46e5af4f78efeec0786
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/90688
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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bug 949219
Change-Id: I1ed8d08de4bdba4643b2ae4e8320db6f9c97a18f
Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com>
Reviewed-on: http://git-master/r/92310
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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- as of now the resources needed by all the host1x
modules are part of resource list of host1x device
- now that each module is a nvhost_device of its own,
so it should hold the resources it needs instead of
host1x device holding it for them
- each device that needs its resources gets it in its
_probe() using a helper API in bus_client.c
Bug 871237
Change-Id: Ia7c63fcf40cbc5db76d4d8339294a0e9ce75e352
Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-on: http://git-master/r/94166
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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This reverts commit 75009bc2b1a0a2d2efbe1d166647e789b8a1b9f1.
In order to work around bug 869099,
this mode has been temporarily disabled.
Since the bug is not so visible, enable again.
Change-Id: Ie71dac4ecf620cd96796e2fde361b45dc7141497
Reviewed-on: http://git-master/r/92157
Reviewed-by: Alok Ahuja <alahuja@nvidia.com>
Reviewed-by: Aleksandar Odorovic <aodorovic@nvidia.com>
Reviewed-by: Dhiren Bhatia <dbhatia@nvidia.com>
Reviewed-by: Andrija Bosnjakovic <abosnjakovic@nvidia.com>
Tested-by: Andrija Bosnjakovic <abosnjakovic@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
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Change to using kbytes/sec to avoid overflowing 32-bit integer in
bandwidth calculation.
Changing efficiency adjustment to ~35%.
Bug 958016
Change-Id: Ia8bdf79e4b3e4bc65517db18d9f351a5f840805e
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/92658
Reviewed-by: Automatic_Commit_Validation_User
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Context handler init functions are referred to from non-init section.
The functions should not have __init attribute, even though they're
only used in init time.
Change-Id: I1b6bca48504fd7989edaa037c4b022a76244b0f6
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/93216
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-by: Ken Adams <kadams@nvidia.com>
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
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Add inline wrappers for device_prep_slave_sg() and device_prep_dma_cyclic()
interfaces to hide new parameter from current users of affected interfaces.
Convert current users to use new wrappers instead of direct calls.
Suggested by Russell King [https://lkml.org/lkml/2012/2/3/269].
Signed-off-by: Alexandre Bounine <alexandre.bounine@idt.com>
Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
cherry-picked from mainline commit
16052827d98fbc13c31ebad560af4bd53e2b4dd5
Change-Id: I929a49556539621a0546829e88b3caa498c94be2
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/94463
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Initialize scale3d worker even though scale3d would be disabled.
Bug 954879
Change-Id: Iaf3a12740d1d377d949cdfbf7e11fa00568e72fe
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/93488
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
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Expose sync point current and max values through sysfs.
Bug 957639
Change-Id: I2a3b914d404bb8d7bbed86d383c859bd8237a278
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/92778
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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Enabled recovery of DC from resetting. When underflow triggered serveral
times(current > 4 for tegra2), DC driver will reset itself to prevent
data corruption. Reopend nvhost connection when resetting finished. That
helps system to show frames instead of a blank screen again.
Fixed Bug 936613
Change-Id: I314c37258a4a446dc07167ac60d0420e79a5fb2d
Signed-off-by: Adam Jiang <chaoj@nvidia.com>
Reviewed-on: http://git-master/r/89406
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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- remove redundant 2nd argument to nvhost_module_suspend()
- also remove the debug_not_idle() as it redundant after
refactor of host1x code
- debug_not_idle() iterates through host1x's private instance
of channels to find out which client module is active (along
with host1x itself). we are going to remove these instances of
channels from host1x's device private data
- reduce the prints during suspend
Bug 871237
Change-Id: I66c7c4d8f35c157b1626784a6a27166442a50557
Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-on: http://git-master/r/92550
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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nvmap_ioctl.h intended to be included by both kernel and
userspace code.
Change-Id: I8cccef5e3bc02f3271f471155b2e36126c68017a
Signed-off-by: Yogish Kulkarni <yogishk@nvidia.com>
Reviewed-on: http://git-master/r/93329
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
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Bug 949759
Add new 1080p timing support, or 1080p playback is not available on
some monitors like Acer H243HX
Change-Id: I8a8a3a5b2de71d5a56dad233f953e09176f85b76
Signed-off-by: Hao Tang <htang@nvidia.com>
Reviewed-on: http://git-master/r/91732
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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Remove old overlay interface, it is replaced with TEGRA_DC_EXTENSIONS
External functions made static now that overlay.c no longer needs them.
Change-Id: I5d080ceb19ad90d3b5cc4bf20494c967687293a5
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/92661
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>
Reviewed-by: Robert Morell <rmorell@nvidia.com>
Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
Reviewed-by: Michael I Gold <gold@nvidia.com>
Reviewed-by: Markus Holtmanns <mholtmanns@nvidia.com>
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Remove the check and debug dump for cases where we compare against
an old syncpt value. Also removes an extra check that is already done
by wait_event_interruptible_timeout();
Bug 941327
Change-Id: Icbaf70b04a8bd070c3fdd3467b981de11219d2b9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/92283
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
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Refactor page pool code.
Add page pool support for all memory types.
Add support to enable/disable page pools.
Add support to allow configuring page pool size.
Change-Id: I07c79004542efdd5909547928b3aa5d470e38909
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/91914
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
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- if user space does not open 3d channel, 3d scaling
algorithm is not initialized. so return safely when
3d scaling is disabled
- also do not call nvhost_module_suspend() explicitly
for host1x client modules. nvhost_channel_suspend()
takes care to suspend the module if ref count = 0
- call nvhost_module_suspend() only for host1x device
as it does not use actual hardware channel
Bug 953451
Change-Id: Iba2b771b71d9b41c8ed978112566181872c56259
Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-on: http://git-master/r/92506
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Peer Chen <pchen@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Emily Jiang <ejiang@nvidia.com>
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This change adds a flag to flip windows in cursor mode. Cursor mode
will cause flips to be skipped over if there are newer flip requests
waiting in the workqueue.
Add CURSOR_MODE to caps bitfield.
bug 942762
Change-Id: Ib52a0a5565f961cdd9650e4204cd65b86f96fee1
Signed-off-by: Adam Cheney <acheney@nvidia.com>
Reviewed-on: http://git-master/r/90418
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Robert Morell <rmorell@nvidia.com>
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- this patch uses the iterrator bus API to print the channel
status on debug-fs output
- it is the first step for removal nvhost_master holding
pointers to all the channels
Bug 871237
Change-Id: I2eaf8f0124512f1bc1ea9bbbe71d2c112b1947d2
Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-on: http://git-master/r/91676
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Split host1x_channel_submit() into subfunctions.
Bug 926690
Change-Id: I8be55cbc9d25ee76c758a918de4a9bb27e2ea846
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/90626
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
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Set dc clock rate dynamically to requested pixel rate.
Using modes specified in monitor's EDID data.
Return mode set errors on unsupported clock tolerances.
Bug 931908
Change-Id: I60990ecbc2fbeab542987036b8ccc30b8dababe8
Signed-off-by: Shashank Sharma <shashanks@nvidia.com>
Reviewed-on: http://git-master/r/86073
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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Add following VGA video modes in tegra_dc_hdmi_supported_modes list:
Resolution Refresh rate(Hz)
----------- ----------------
640x480 75
720x400 59
800x600 60
800x600 75
1024x768 75
1024x768 60
1152x864 75
1280x800 60
1280x960 60
1280x1024 60
1368x768 60
1440x900 60
1600x1200 75
1680x1050 60
Add CVT representation of all above modes to make sure they pass all the
HDMI constraints.
Add a new function tegra_dc_reload_mode to pick up CVT representation of
matching mode.
Bug 883911
Signed-off-by: Shashank Sharma <shashanks@nvidia.com>
Change-Id: I5227644207d38ca83a0452d3c078ef202e40a508
Reviewed-on: http://git-master/r/89126
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Kiran Adduri <kadduri@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
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Not disabling emc clock when it's being set to zero results in incorrect
reference count when a call is made to clear bandwidth. This happens when
two worker threads try to handle dc emc rate. A deep-sleep/wake-up cycle
easily shows this scenario.
With this fix, disp.emc's ref count is properly managed even after multiple
deep-sleep/wake-up cycles.
Bug 947228
Change-Id: I045fafbd483af1e3d492b8d0395275e45642d059
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: http://git-master/r/90100
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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Change waitchk comparison logic to use the new
nvhost_syncpt_is_expired().
Bug 941327
Change-Id: Ib7de04ad7663990bb416e39f8d79a46a9f5955fa
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/89769
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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- split the nvhost clients into their own directories
- each client is a nvhost_device and nvhost_driver
- all the code related to host1x control node is centralized
at single place in dev.c
- all the code related to host1x modules nodes is centralized
at single place in bus_client.c
- update the copyright notice & year for new files
Bug 871237
Change-Id: Ief85064699e35ad02b48a7e54496928d7f085af4
Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-on: http://git-master/r/83491
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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dsi HW does not clear host trigger bit automatically
on dsi interface disable if host fifo is empty.
This leads to hang. Clearing the bit explicitly.
Bug 930453
Change-Id: Id24359dc274f187f8ac634ad838ef4a6a29a6a5e
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/90043
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
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Update nvmap_alloc api to take heap_mask as arg.
This is to let clients specify the specific heap needed.
Change-Id: I9950b3e60e6dac0301b6dc66be3e9d0bab8e0fee
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/90471
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
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Fix sync point comparison to take into account old expired values, and
do proper comparison taking into account wrapping.
Bug 941327
Change-Id: I70724637ba870b2e29bac695abc0ea2b968394d7
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/84808
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ilan Aelion <iaelion@nvidia.com>
Reviewed-by: Acorn Pooley <apooley@nvidia.com>
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Bug 925987
Change-Id: Ifab4e515c7dd06b92d798e7eb93094c35e02b878
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/89414
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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fix some build warnings and bad code style.
Change-Id: I907296ce0e5437dfd6acd0b2b3c119b6dbde7b1c
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/89634
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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this is a workaround for the SLI scissor bug which can happen
intermittently.
Bug 914785
Change-Id: I5b7071df5bbfdd03bfe8b6f6b12ac7279221bd4e
Signed-off-by: Donghan Ryu <dryu@nvidia.com>
Reviewed-on: http://git-master/r/87968
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
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Add checks to ensure host1x is powered when DSI is used.
Change-Id: I2e61abdd5c0741571fb18262fd2efa16ffee71d9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/86361
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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Currently nvhost hard codes usage of context handler and sync point
id. Split the context handler and context structures into generic and
host1x specific parts, and move the allocation to happen via a
function pointer in nvhost_device.
Also updates gr3d and mpe to use sync point id and waitbase from
nvhost_device.
Bug 926690
Change-Id: I7f00b450cac99f3816baa27b37ee4e4cf68cfe24
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/84901
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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Fix race condition in handle_page_alloc. Page allocations
should not try allocate from pool, once it fails for a
request. If it tries and allocation passes during subsequent
attempts, the page_index is not valid for CPA and cache won't be
flushed for all the necessary pages.
Change-Id: I5548e11b713f271cc8473a3f2ae193a69e832f99
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/89611
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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There are HDMI modes which have different margin/sync values
although resolution and pixel clock are the same. One example
is 1080p/24Hz and 1080p/30Hz case.
Those modes are not distinguished when we check if given two
modes are equal. So clocks per frame also should be validated
to decide sameness of the modes.
Bug 950935
Signed-off-by: Youngjin Kim <nkim@nvidia.com>
Reviewed-on: http://git-master/r/89026
(cherry picked from commit b9e6316850a47445be7545aaec85c6a247c44cb9)
Change-Id: I06d3c0f41e63d65f1908614d09df4d16028895f0
Reviewed-on: http://git-master/r/90030
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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We add this variable for two purposes. First, it would remind developer
to make sure actual refresh rate is larger than rated refresh rate.
Second, gralloc would read rated refresh rate for one-shot mode since
actual refresh rates of most devices are expected running at rated
refresh rate.
Bug 946370
Bug 934977
Change-Id: Ib4121337df1a388b40440b22687c39f373f08890
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/89871
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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Horizontal blank must be greater than phy timing for
HS transmission.
Bug 938043
Change-Id: I5afe68ec04341f7b83c2897c586d4618bd518222
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/89789
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
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Adding support to accomodate hw increment to
phy timing reg values.
Bug 938043
Change-Id: I8de14648c0994b03c37a2ee455a656ff11c3cc34
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/89741
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
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Replace license information in nvhost with GPLv2. Also adds
copyright year 2012 in files which have been changed in 2012.
Change-Id: I86e8ed27095df13d99e0250e57e244d531fdacec
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/89735
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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