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2015-06-24MLK-11151 usb: chipidea: otg: drive vbus off if fsm.drv_vbus is truerel_imx_3.14.38_6qp_betaPeter Chen
The current condition may not true even we have driven vbus on already. The vbus drive operation may be async, eg through i2c gpio expendor, so the vbus may not be valid when we unload usb module. We meet this issue when we do fast load/unload usb module test. Signed-off-by: Peter Chen <peter.chen@freescale.com>
2015-06-24MLK-11137 usb: chipidea: host: add own hc_driver for each hcdPeter Chen
There are several benefits for doing like this: - hc_driver can be customized for each hcd - Other hcd hc_driver's initialization will not affect current one. We run out NULL pointer dereference problem when one hcd is started by module_init, and the other is started by otg thread at SMP platform. The reason for this problem is ehci_init_driver will do memory copy for current uniform hc_driver, and this memory copy will do memset (as 0) first, so when the first hcd is running usb_add_hcd, and the second hcd may clear the uniform hc_driver's space (at ehci_init_driver), then the first hcd will meet NULL pointer at the same time. See below two logs: LOG_1: ci_hdrc ci_hdrc.0: EHCI Host Controller ci_hdrc ci_hdrc.0: new USB bus registered, assigned bus number 1 ci_hdrc ci_hdrc.1: doesn't support gadget Unable to handle kernel NULL pointer dereference at virtual address 00000014 pgd = 80004000 [00000014] *pgd=00000000 Internal error: Oops: 805 [#1] PREEMPT SMP ARM Modules linked in: CPU: 0 PID: 108 Comm: kworker/u8:2 Not tainted 3.14.38-222193-g24b2734-dirty #25 Workqueue: ci_otg ci_otg_work task: d839ec00 ti: d8400000 task.ti: d8400000 PC is at ehci_run+0x4c/0x284 LR is at _raw_spin_unlock_irqrestore+0x28/0x54 pc : [<8041f9a0>] lr : [<8070ea84>] psr: 60000113 sp : d8401e30 ip : 00000000 fp : d8004400 r10: 00000001 r9 : 00000001 r8 : 00000000 r7 : 00000000 r6 : d8419940 r5 : 80dd24c0 r4 : d8419800 r3 : 8001d060 r2 : 00000000 r1 : 00000001 r0 : 00000000 Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel Control: 10c53c7d Table: 1000404a DAC: 00000015 Process kworker/u8:2 (pid: 108, stack limit = 0xd8400238) Stack: (0xd8401e30 to 0xd8402000) 1e20: d87523c0 d8401e48 66667562 d8419800 1e40: 00000000 00000000 d8419800 00000000 00000000 00000000 d84198b0 8040fcdc 1e60: 00000000 80dd320c d8477610 d8419c00 d803d010 d8419800 00000000 00000000 1e80: d8004400 00000000 d8400008 80431494 80431374 d803d100 d803d010 d803d1ac 1ea0: 00000000 80432428 804323d4 d803d100 00000001 80435eb8 80e0d0bc d803d100 1ec0: 00000006 80436458 00000000 d803d100 80e92ec8 80436f44 d803d010 d803d100 1ee0: d83fde00 8043292c d8752710 d803d1f4 d803d010 8042ddfc 8042ddb8 d83f3b00 1f00: d803d1f4 80042b60 00000000 00000003 00000001 00000001 80054598 d83f3b00 1f20: d8004400 d83f3b18 d8004414 d8400000 80e3957b 00000089 d8004400 80043814 1f40: d839ec00 00000000 d83fcd80 d83f3b00 800436e4 00000000 00000000 00000000 1f60: 00000000 80048f34 00000000 00000000 00000000 d83f3b00 00000000 00000000 1f80: d8401f80 d8401f80 00000000 00000000 d8401f90 d8401f90 d8401fac d83fcd80 1fa0: 80048e68 00000000 00000000 8000e538 00000000 00000000 00000000 00000000 1fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 1fe0: 00000000 00000000 00000000 00000000 00000013 00000000 00000000 00000000 [<8041f9a0>] (ehci_run) from [<8040fcdc>] (usb_add_hcd+0x248/0x6e8) [<8040fcdc>] (usb_add_hcd) from [<80431494>] (host_start+0x120/0x2e4) [<80431494>] (host_start) from [<80432428>] (ci_otg_start_host+0x54/0xbc) [<80432428>] (ci_otg_start_host) from [<80435eb8>] (otg_set_protocol+0xa4/0xd0) [<80435eb8>] (otg_set_protocol) from [<80436458>] (otg_set_state+0x574/0xc58) [<80436458>] (otg_set_state) from [<80436f44>] (otg_statemachine+0x408/0x46c) [<80436f44>] (otg_statemachine) from [<8043292c>] (ci_otg_fsm_work+0x3c/0x190) [<8043292c>] (ci_otg_fsm_work) from [<8042ddfc>] (ci_otg_work+0x44/0x1c4) [<8042ddfc>] (ci_otg_work) from [<80042b60>] (process_one_work+0xf4/0x35c) [<80042b60>] (process_one_work) from [<80043814>] (worker_thread+0x130/0x3bc) [<80043814>] (worker_thread) from [<80048f34>] (kthread+0xcc/0xe4) [<80048f34>] (kthread) from [<8000e538>] (ret_from_fork+0x14/0x3c) Code: e5953018 e3530000 0a000000 e12fff33 (e5878014) LOG_2: ci_hdrc ci_hdrc.0: EHCI Host Controller ci_hdrc ci_hdrc.0: new USB bus registered, assigned bus number 1 ci_hdrc ci_hdrc.1: doesn't support gadget Unable to handle kernel NULL pointer dereference at virtual address 00000000 pgd = 80004000 [00000000] *pgd=00000000 In Online 00:00ternal e Offline rror: Oops: 80000005 [#1] PREEMPT SMP ARM Modules linked in: CPU: 0 PID: 108 Comm: kworker/u8:2 Not tainted 3.14.38-02007-g24b2734-dirty #127 Workque Online 00:00ue: ci_o Offline tg ci_otg_work Online 00:00task: d8 Offline 39ec00 ti: d83ea000 task.ti: d83ea000 PC is at 0x0 LR is at usb_add_hcd+0x248/0x6e8 pc : [<00000000>] lr : [<8040f644>] psr: 60000113 sp : d83ebe60 ip : 00000000 fp : d8004400 r10: 00000001 r9 : 00000001 r8 : d85fd4b0 r7 : 00000000 r6 : 00000000 r5 : 00000000 r4 : d85fd400 r3 : 00000000 r2 : d85fd4f4 r1 : 80410178 r0 : d85fd400 Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel Control: 10c53c7d Table: 1000404a DAC: 00000015 Process kworker/u8:2 (pid: 108, stack limit = 0xd83ea238) Stack: (0xd83ebe60 to 0xd83ec000) be60: 00000000 80dd920c d8654e10 d85fd800 d803e010 d85fd400 00000000 00000000 be80: d8004400 00000000 d83ea008 80430e34 80430d14 d803e100 d803e010 d803e1ac bea0: 00000000 80431dc8 80431d74 d803e100 00000001 80435858 80e130bc d803e100 bec0: 00000006 80435df8 00000000 d803e100 80e98ec8 804368e4 d803e010 d803e100 bee0: d86e8100 804322cc d86cf050 d803e1f4 d803e010 8042d79c 8042d758 d83cf900 bf00: d803e1f4 80042b78 00000000 00000003 00000001 00000001 800545e8 d83cf900 bf20: d8004400 d83cf918 d8004414 d83ea000 80e3f57b 00000089 d8004400 8004382c bf40: d839ec00 00000000 d8393780 d83cf900 800436fc 00000000 00000000 00000000 bf60: 00000000 80048f50 80e019f4 00000000 0000264c d83cf900 00000000 00000000 bf80: d83ebf80 d83ebf80 00000000 00000000 d83ebf90 d83ebf90 d83ebfac d8393780 bfa0: 80048e84 00000000 00000000 8000e538 00000000 00000000 00000000 00000000 bfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 bfe0: 00000000 00000000 00000000 00000000 00000013 00000000 ee66e85d 133ebd03 [<804 Online 00:000f644>] Offline (usb_add_hcd) from [<80430e34>] (host_start+0x120/0x2e4) [<80430e34>] (host_start) from [<80431dc8>] (ci_otg_start_host+0x54/0xbc) [<80431dc8>] (ci_otg_start_host) from [<80435858>] (otg_set_protocol+0xa4/0xd0) [<80435858>] (otg_set_protocol) from [<80435df8>] (otg_set_state+0x574/0xc58) [<80435df8>] (otg_set_state) from [<804368e4>] (otg_statemachine+0x408/0x46c) [<804368e4>] (otg_statemachine) from [<804322cc>] (ci_otg_fsm_work+0x3c/0x190) [<804322cc>] (ci_otg_fsm_work) from [<8042d79c>] (ci_otg_work+0x44/0x1c4) [<8042d79c>] (ci_otg_work) from [<80042b78>] (process_one_work+0xf4/0x35c) [<80042b78>] (process_one_work) from [<8004382c>] (worker_thread+0x130/0x3bc) [<8004382c>] (worker_thread) from [<80048f50>] (kthread+0xcc/0xe4) [<80048f50>] (kthread) from [<8000e538>] (ret_from_fork+0x14/0x3c) Code: bad PC value Signed-off-by: Peter Chen <peter.chen@freescale.com>
2015-06-24MLK-11160 pci: imx: enlarge the delay time after resumeRichard Zhu
some pcie pe devices maybe still failed resime back, after pcie rc is resumed, when the pcie ep devices have a heavy loading task. Enlarge the delay time after imx6qp pcie rc resume back. Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com> (cherry picked from commit e0f3836149889b1db7cce76218c76efbf0347e0e)
2015-06-24MLK-11132 usb: chipidea: otg: delay suspend for a_wait_vfallLi Jun
While A device as peripheral ends session by a_bus_drop, it will go back to host role by transition to a_wait_vfall state, then ehci host driver may access portsc status after controller enters suspend , this will result in system hang since its clock is gated off. This patch use existing autosuspend to delay the controller suspend if it comes to a_wait_vfall state. Signed-off-by: Li Jun <jun.li@freescale.com> (cherry picked from commit b140fa6803ef6ececec17e435212a960a3169cc2)
2015-06-23MLK-9897-2 usb: otg-fsm: check B-device state before sending polling requestLi Jun
While system resume, the connected udev as B-device may not has been resumed, if HNP polling request is sent to it, HNP polling may fail, this patch adds check of the udev state to make sure it finished resume and to be configured state before sending host request message, otherwise try next HNP polling request. Acked-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Li Jun <jun.li@freescale.com> (cherry picked from commit 2cff5eb7bd4feb70cd28ac4655e7433e57a17938)
2015-06-23mmc: sdhci-esdhc-imx: avoid DMA to kernel stackRussell King
sdhci-esdhc-imx tries to DMA to the kernel stack when tuning the interface, which causes dma-debug to complain. Fix this by kmallocing a buffer to hold the received tuning pattern. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-by: Markus Pargmann <mpa@pengutronix.de> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Chris Ball <chris@printf.net>
2015-06-15MGS-755 [#1779] fix vg context buffer memory leakXianzhong
gcoVGHARDWARE_FreeVideoMemory user space implementation has some problem, the asynchronous unlock/free is required by kernel memory managment, by not available in this function. because user command buffer & struct cannot be freed through committing new vg command to hardware, the new workaround is to double unlock the video memory for gcvHAL_RELEASE_VIDEO_MEMORY, also removed the database as the asynchronous unlock is not available in vg user space driver. Date: Jun 15, 2015 Signed-off-by: Xianzhong <b07117@freescale.com> (cherry picked from commit af30773d184e4b370ae577fd624f3ea8aec97a50)
2015-06-12MLK-10828 thermal: imx: update the temperature calibration data for i.mx6Bai Ping
According to the design team: After a thorough accuracy study of the Temp sense circuit,we found that with our current equation, an average part can read 7 degrees lower than a known forced temperature. We also found out that the standard variance was around 2C; which is the tightest distribution that we could create. We need to change the temp sense equation to center the average part around the target temperature. Old Equation: Temp = Troom,cal - slope*(Count measured - Count room fuse) Where Troom,cal = 25C and Slope = 0.4297157 - (0.0015974 * Count room fuse) New Equation: Temp = Troom,cal - slope*(Count measured - Count room fuse) +offset Where Troom,cal = 25C and Slope = 0.4148468 - (0.0015423 * Count room fuse) Offset = 3.580661 Signed-off-by: Bai Ping <b51503@freescale.com>
2015-06-11MLK-11082 mxc IPUv3: common: Explicitly set IDMAC0/1/2/3 AXI ID for various SoCsLiu Ying
The IDMAC0/1/2/3 channels are real time channels for video input capture via the SMFC0/1/2/3 channels respectively. These IDMAC channels should have high priority in IPUv3(controlled by the register IDMAC_CH_PRI_1) to make sure the capture channels may access memory whenever they want. Accordingly, the AXI ID of the IDMAC channels should reflect it's high priority nature in the fabric settings(controlled by IPUx_IDy_RD/WR_QoS fields) with a relatively good QoS value. This patch explicitly sets IDMAC0/1/2/3 AXI ID for various SoCs to match the fabric settings(programmed in machine layer or bootloader). Signed-off-by: Liu Ying <Ying.Liu@freescale.com> (cherry picked from commit 70dfca096aa1be07dc6eb83c0a11998a9c69804d)
2015-06-10MGS-797 [#1772] fix gpu hang with the loadable galcoreXianzhong
GPU hang with repeat insmod/rmmod galcore when run all 3D applications, The issue is identifed and related with the workaround of keeping PU always on to avoid PRE hang, It is confirmed that GPU hardware reset is not available on i.mx6qp due to PRE Errata, The SW wokaround is applied to remove soft reset during GPU hardware initialization. Date: Jun 10, 2015 Signed-off-by: Xianzhong <b07117@freescale.com> (cherry picked from commit a1072144162dfa281a78d9e2c2e657e464aa5ea9)
2015-06-10MLK-11078 video: mxc ipuv3 fb: reduce debug level for PRE allocation failureLiu Ying
Upon PRE allocation failure, the function ipu_pre_alloc() would return a dedicated value to reflect the reason of the failure. So, it should be ok to reduce debug level for the failure from dev_err to dev_dbg so that dmesg would be less noisy. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> (cherry picked from commit e37c94006b4b84670500c4113ad841e5fda68141)
2015-06-09MLK-11066 video: mxc ipuv3 fb: check tile block after blank check in pan displayLiu Ying
We may wrongly check tile block in pan display for a linear framebuffer in the following case: step 1) framebuffer works in linear RGB24 pixel format(unblanked) step 2) blank the framebuffer step 3) change framebuffer to be a GPU tile format step 4) change framebuffer back to linear RGB24 pixel format The cached variable mxc_fbi->cur_var will not change in all of the 4 steps because the framebuffer is blanked in step 2). In step 3), the format change is successful since step 2) to 3) would definitely changes the pixel format from linear RGB24 to a GPU tile format - mxc_fbi->cur_var is not the same to fbi->var, which leads to mxcfb_need_to_set_par() returns true. However, in step 4), the format change is not successful since mxc_fbi->cur_var and fbi->var is the same, which leads to mxcfb_need_to_set_par() returns false. Note that we set mxc_fbi->resolve to be true in step 3), so it keeps to be true in step 4) as we return at mxcfb_need_to_set_par() before we may change it to be false. Finally, in step 4), after doing ->fb_set_par() in fb_set_var(), we do fb_pan_display() and wrongly check tile block for the linear RGB24 pixel format as mxc_fbi->resolve is true - hit the BUG_ON() in fmt_to_tile_block(). To fix this issue, this patch moves the code for tile block check down below blank check in ->fb_pan_display(). Signed-off-by: Liu Ying <Ying.Liu@freescale.com> (cherry picked from commit f1889f599400d9cc766fba09e709434cbca33fd2)
2015-06-05MLK-11055 video: mxc ipuv3 fb: Fix wrong pixel component map when PRE is enabledLiu Ying
In the on-the-fly cases to enable PRE, to make sure the pixel may be correctly deciphered by IPU after the framebuffer configuration is done, we probably need to use PRE pixel component mapping feature since the original framebuffer pixel format is likely not the same as the one we use in the last run. However, in the non on-the-fly cases to enable PRE, we should have PRE generate an appropriate pixel format for IPU to consume which doesn't include PRE pxiel component mapping feature. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> (cherry picked from commit d87af060ae03a24cfa120ffe7047354cc0110d68)
2015-06-05MLK-10994-5 usb: chipidea: otg: fix NULL pointer dereference when unload modulePeter Chen
With commit "95b62fe MLK-10750 usb: chipidea: otg: remove otg fsm before destory gdaget and host", the otg fsm will be removed first, but when the host is removing, it will trigger pcd interrupt, and otg work is still queued to ci_otg workqueue(otg state is OTG_STATE_A_HOST), but at that time, ci_otg workqueue has been destroyed. In this commit, we make sure the otg work is not queued if ci->wq is NULL, and keep otg state is OTG_STATE_UNDEFINED after otg fsm has been removed. The NULL pointer deference error like belows: Unable to handle kernel NULL pointer dereference at virtual address 00000000 pgd = a873c000 [00000000] *pgd=a90f9831, *pte=00000000, *ppte=00000000 Internal error: Oops: 17 [#1] PREEMPT SMP ARM Modules linked in: usb_f_ecm u_ether libcomposite configfs ci_hdrc_imx(-) ci_hdrc udc_core ehci_hcd mxc_vadc mx6s_capture mxc_dcic ov5640_camera usbmisc_imx phy_mxs_usb evbug [last unloaded: usb_f_rndis] CPU: 0 PID: 162 Comm: udevd Not tainted 3.14.38-02187-g5639985-dirty #160 task: a863e880 ti: a872e000 task.ti: a872e000 PC is at __queue_work+0x68/0x268 LR is at __queue_work+0x68/0x268 pc : [<80045060>] lr : [<80045060>] psr: 600e0193 sp : a872fed0 ip : 00000000 fp : 00000000 r10: 00000004 r9 : a872e000 r8 : 0000004b r7 : 80e4c804 r6 : a9295000 r5 : a87f8294 r4 : 00000000 r3 : a80690e0 r2 : 00000000 r1 : a8069108 r0 : a8003400 Flags: nZCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment user Control: 10c53c7d Table: a873c04a DAC: 00000015 Process udevd (pid: 162, stack limit = 0xa872e238) Stack: (0xa872fed0 to 0xa8730000) fec0: 00ff3d34 80743750 00000000 600e0193 fee0: a87f8294 a9295000 00000004 0000004b a8008900 80eb51ff 00ff3d34 800452a8 ff00: 00000000 a87f8010 00000000 00000000 00000000 7f060ac0 a8dfced0 a87f8010 ff20: 00002e20 7f059730 a8e7e2c0 a800895c 00000000 8006c1b4 80e46080 80e40458 ff40: a8008900 a800895c a8e7e2c0 c0802100 00fc40e8 00000000 00000048 8006c320 ff60: a8008900 a800895c 00000000 8006f1c4 8006f140 0000004b 0000004b 8006b92c ff80: 80e40e54 8000f9cc c080210c 80e4c970 a872ffb0 8000856c 00fc4308 76d9c890 ffa0: 600e0010 ffffffff 7edef480 800130bc 00fc4308 00ff3d70 00000000 000000ff ffc0: 00000671 00000000 00ff3b90 7edef480 00fc40e8 00000000 00000048 00ff3d34 ffe0: 000321b8 7edef140 000240a0 76d9c890 600e0010 ffffffff abf5e821 abf5ec21 [<80045060>] (__queue_work) from [<800452a8>] (queue_work_on+0x48/0x54) [<800452a8>] (queue_work_on) from [<7f060ac0>] (ci_otg_fsm_irq+0x108/0x310 [ci_hdrc]) [<7f060ac0>] (ci_otg_fsm_irq [ci_hdrc]) from [<7f059730>] (ci_irq+0x94/0x158 [ci_hdrc]) [<7f059730>] (ci_irq [ci_hdrc]) from [<8006c1b4>] (handle_irq_event_percpu+0x50/0x180) [<8006c1b4>] (handle_irq_event_percpu) from [<8006c320>] (handle_irq_event+0x3c/0x5c) [<8006c320>] (handle_irq_event) from [<8006f1c4>] (handle_fasteoi_irq+0x84/0x14c) [<8006f1c4>] (handle_fasteoi_irq) from [<8006b92c>] (generic_handle_irq+0x2c/0x3c) [<8006b92c>] (generic_handle_irq) from [<8000f9cc>] (handle_IRQ+0x40/0x90) [<8000f9cc>] (handle_IRQ) from [<8000856c>] (gic_handle_irq+0x2c/0x5c) [<8000856c>] (gic_handle_irq) from [<800130bc>] (__irq_usr+0x3c/0x60) Exception stack(0xa872ffb0 to 0xa872fff8) ffa0: 00fc4308 00ff3d70 00000000 000000ff ffc0: 00000671 00000000 00ff3b90 7edef480 00fc40e8 00000000 00000048 00ff3d34 ffe0: 000321b8 7edef140 000240a0 76d9c890 600e0010 ffffffff Code: e5964084 e0844003 e1a00005 ebfffa14 (e5943000) ---[ end trace 53dc25e918ff7216 ]--- Kernel panic - not syncing: Fatal exception in interrupt Signed-off-by: Peter Chen <peter.chen@freescale.com> (cherry picked from commit c5b8111e4178387e1a6e9c700fdf887a944a5129)
2015-06-03MLK-10960 thermal: imx: add a mutex to make sure tempmon setting changed safelyBai Ping
The busfreq notifier and thermal_zone updating run asynchronously. In some critical situaiton, the notifier callback may be interrupted by thermal_zone kthread, it will lead to the TEMPMON setting uncompleted when the get_temp function reads the temp sensor value. Signed-off-by: Bai Ping <b51503@freescale.com>
2015-06-01MLK-11007 Revert "MLK-10998 video: mxc ipuv3 fb: Fix wrong pixel component ↵Robby Cai
map when PRE is enabled" This reverts commit 543b0799a446ecddedaa33847021bfc87d8262e1. Because this patch will introduce the following error: If only use /dev/video18 to display the video, it will print IPU warning and gst dqueue failed. imx-ipuv3 2400000.ipu: IPU Warning - IPU_INT_STAT_10 = 0x40000000 imx-ipuv3 2400000.ipu: IPU Warning - IPU_INT_STAT_10 = 0x00100000 imx-ipuv3 2400000.ipu: IPU Warning - IPU_INT_STAT_5 = 0x00800000 mxc_sdc_fb fb.24: timeout when waiting for flip irq .... Signed-off-by: Robby Cai <r63905@freescale.com> (cherry picked from commit 316c2a399871eaafff0a2f2b5a35e5398cebb41a)
2015-05-29MLK-10998 video: mxc ipuv3 fb: Fix wrong pixel component map when PRE is enabledLiu Ying
In the on-the-fly cases to enable PRE, the PRE input/output pixel formats are likely not the same, hence, we need to use PRE pixel component mapping feature to make sure the pixel may be correctly deciphered by IPU. However, in the non on-the-fly cases to enable PRE, we should have PRE generate the original fb pixel format for IPU to consume as long as the pixel format is one that IPU can process. The PRE specific input pixel formats(NV21, NV61 and GPU tile formats) are not one of them, thus, we have to use PRE to convert them into dedicated IPU formats. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> (cherry picked from commit 0c33038319b71464dae0d894902e6e6da4dd42a9)
2015-05-28MGS-622 [#1729] Suspend/resume test cause GPU hangShawn Xiao
Signal will cause some GPU kernel call return with error status gcvSTATUS_INTERRUPTED. If adding interruptcount first, the signal will cause the number not align with actual event, and the monitor funciton will make a fake GPU hang judgement based on this. Date May 21, 2015 Signed-off-by: Shawn Xiao <b49994@freescale.com> (cherry picked from commit 4ac2e19117d3c2349cab50e58a2b33606c3d5bdd)
2015-05-28MLK-9606-1 usb: otg: test: add otg test device into otg and EH TPLLi Jun
This patch add otg test device with VID(0x1a0a) and PID(0x0200) into otg and EH TPL. Acked-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Li Jun <b47624@freescale.com> (cherry picked from commit b88ee5e2cbf55aaed3b6c5dd0aff7f826f9e357d)
2015-05-28MLK-9617-19 usb: otg: test: show warning message for unsupported otg test devLi Jun
According to "USB On-The-Go and Embedded Host Automated Compliance Plan Version 1.2", chapter 6.7.23, unknown Device Not Supporting HNP:'Unsupported Device'; chapter 6.7.24 unknown Device Supporting HNP: 'Device No Response' Signed-off-by: Li Jun <b47624@freescale.com> (cherry picked from commit 32df700386fff1d1eef90007604055f1d013aaf3)
2015-05-28MLK-9829 usb: core: print suggested message if failed to get device descriptorLi Jun
This is required for USB OTG and EH compliance test 6.7.22(A-UUT “Device No Response” for connection timeout). When the connected usb device(PET) does not response to transactions, host will fail to get device descriptor. Signed-off-by: Li Jun <jun.li@freescale.com> (cherry picked from commit 86d0bd661ecbbdf97dd9a8ddbaf0d3811de7f39e)
2015-05-22MLK-10937 video: mxc ipuv3 fb: Correct cur_blank for set_par bailout if no ↵Liu Ying
PRE available We should set cur_blank to be FB_BLANK_POWERDOWN for set_par's bailout path if no PRE is available and we are not in the 'on_the_fly' cases, because the framebuffer is still in unblanked status even if we fail to allocate PRE in the 'on_the_fly' cases. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> (cherry picked from commit 79623a7509bf9c81c9b6722f120cde9a5e9a8a38)
2015-05-22MLK-10862-2 mxc IPUv3: cpmem: SMFC chan 12bit 3 planar burst size fixupLiu Ying
There are some little horizontal stripes on the I420 interlaced frames captured by i.MX6QP SMFC channels but not i.MX6Q Rev1. Changing the IDMAC burst size from 32pixel to 16pixel may workaround this issue which is recorded by TKT266260. The capture performance is expected to be dropped as the burst size is half. The exact performance drop data is not known since the video input device's output is not tough enough to push the capture to it's boundary. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> (cherry picked from commit dc7ba9d506e7a438cd342e02977f3455fbe05cd2)
2015-05-22MLK-10862-1 mxc IPUv3: common: Move the helper _ipu_is_smfc_chan() to ipu_prv.hLiu Ying
The helper _ipu_is_smfc_chan() needs to be used outside ipu_common.c so move it to ipu_prv.h. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> (cherry picked from commit fa12f70fb32e52982d17bdc69fbdad0c232046f9)
2015-05-20MLK-10929 media: mxc: vout: fix the vout->task_lock dead lock issueJason Liu
with the task_lock mutext to avoid the open/release race condition, which will have the deadlock issue when the release process try to destory the workqueue while the display work queued want to get the task_lock to finish the pending work, this lead to the AB-BA dead lock. To simplify the design, let's use the dedicated mutext for open/release. Signed-off-by: Jason Liu <r64343@freescale.com> (cherry picked from commit 86c9372395b3752a6395639d1ce584b8c79759f7)
2015-05-18MLK-10894 pci: imx: Error message and kernel dump happens after resumeRichard Zhu
phenomena: There is no such kind of phenomen when the "no_consol_suspend" is added into kernel cmd line. But there maybe kernel dump when the "no_consol_suspend" is removed from kernel cmd line. Root cause: After the RC resume back and link is up, delay for a while is required to let ep to resume from D3 mode Regarding to RM DOC, no status bit can be used to make a check on it, thus a while delay had been added. Test results: Over weekend stress tests are passed. Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
2015-05-14MLK-10893: i2c: imx: add irqf_no_suspendgaopan
The i2c irq is masked when pcie starts a i2c transfer process during noirq suspend stage. As a result, i2c transfer fails. To solve the problem, IRQF_NO_SUSPEND is added to i2c bus. Signed-off-by: Gao Pan <b54642@freescale.com>
2015-05-13MLK-10750 usb: chipidea: otg: remove otg fsm before destory gdaget and hostLi Jun
If unload ci_hdrc driver while otg fsm is running as A-device, we should firstly clean otg fsm and stop all otg fsm timers before destroy gadget and host. Signed-off-by: Li Jun <jun.li@freescale.com>
2015-05-13MLK-10803 media: mxc: vout: fix the race condition for multiple disaplayJason Liu
There will some race condition such as the followings: - multiple open concurrence will cause the vout refer to the stall vout-> v4l_wq or the vout-> v4l_wq is not initialized correctly. - multiple open concurrence will cause the global fb setting race-condition, thus, it will have the “set_crop error exceeds width/height” or “mxc_v4l2_output v4l2_out.30: can not find output” This patch fix the above issue by adding the protection for the critical section. Reviewed-by: Liu Ying <b17645@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> (cherry picked from commit 226bc39341bc2526f4d36b88c65ad27c5fac157c)
2015-05-08MLK-10786 mxc ipuv3 fb: Correct ->cur_blank in bailout of ->set_par due to ↵Liu Ying
no PRE We should set mxcfbi->cur_blank to be FB_BLANK_POWERDOWN in the bailout path of ops->set_par due to no PRE is available since the engine will be stopped scanning out frames in this case. Otherwise, the users may call the PAN_DISPLAY ioctrl to switch buffer right after the bailout path and accidently access the IPUv3 registers without the IPUv3 HSP clock being enabled - the system hangs up. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> (cherry picked from commit 9f6b5d5a2f56bd6eb8717bd5469d298fd729a65f)
2015-05-08MLK-10785 mxc ipuv3 fb: Correct ->resolve in bailout of ->set_par due to no PRELiu Ying
We should set mxcfbi->resolve to be false in the bailout path of ops->set_par due to no PRE is available. Otherwise, the users may call the PAN_DISPLAY ioctrl to switch buffer right after the bailout path and accidently runs the resolving logic for switching buffer. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> (cherry picked from commit 26e5c1d73e3bd17384130647bc55757ff10cb3a5)
2015-05-08MLK-10778 usb: chipidea: otg: remove mutex unlock and lock while stop and startLi Jun
Wrongly release mutex lock during otg_statemachine may result in re-enter otg_statemachine, which is not allowed, we should do next state transtition after previous one completed. Signed-off-by: Li Jun <jun.li@freescale.com>
2015-05-08MLK-10718 usb: chipidea: udc: disable BSV irq when otg from undefined to a_idleLi Jun
After device power up, insert usb OTG ID cable, otg fsm from undefined state to a_idle, the BSV cannot be disabled, this will result BSV irq generated but which is actually only for B device. Signed-off-by: Li Jun <jun.li@freescale.com>
2015-05-08MLK-10765 usb: chipidea: use hrtimer for otg fsm timersLi Jun
Current otg fsm timers are using controller 1ms irq and count it, this patch is to replace it with hrtimer solution, use one hrtimer for all otg timers. Signed-off-by: Li Jun <jun.li@freescale.com> Signed-off-by: Peter Chen <peter.chen@freescale.com> (cherry picked from commit 0433eb3101c967783d1231c0431587a49298bc1c)
2015-05-08MLK-10765 usb: otg-fsm: move 2 otg fsm timers definition to otg_fsm_timerLi Jun
B_DATA_PLS(data-line pulse time) and B_SSEND_SRP(session end to SRP init) are also from OTG&EH 2.0 Specification and they are not chipidea specific. Signed-off-by: Li Jun <jun.li@freescale.com> Signed-off-by: Peter Chen <peter.chen@freescale.com> (cherry picked from commit f64f023d3c4899c029a167345350651872271a2c)
2015-05-08MLK-10753 mxc IPUv3: common: Increase IPU priority for 2nd capture channelOliver Brown
Set the IPU channel priority to high for the second CSI capture channel. Signed-off-by: Oliver Brown <oliver.brown@freescale.com> (cherry picked from commit 51d628d057ddfd96321608ca3c639c46e43b996a)
2015-05-08MLK-10769 mxc IPUv3: PRE: Specify some prefetch input RGB pixel formatsLiu Ying
The mxc vout driver is likely to set framebuffer to a RGB pixel format via fbvar->nonstd field when PRE is enabled. This would cause the PRE driver report the prefetch input pixel format is invalid. This patch specifies some prefetch input RGB pixel formats in the PRE driver to address this issue. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> (cherry picked from commit d6fc5d853d05765638e3910be911d18c7c14eabe)
2015-05-08MLK-10723-5 mxc IPUv3: common: Set IDMAC_CONF used bufs via platform informationLiu Ying
We need to use IPUv3 platform information to set IDMAC_CONF used bufs stuffs for different IPUv3 variants. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
2015-05-08MLK-10723-4 mxc IPUv3: common: Set CH0/23/27/28 AXI ID via platform informationLiu Ying
We need to use IPUv3 platform information to set IDMAC0/23/27/28 AXI ID for different IPUv3 variants. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
2015-05-08MLK-10723-3 mxc IPUv3: common: Remove system sleep power management hooksLiu Ying
The system sleep power management hooks ipu_suspend/ipu_resume are actually doing nothing, so let's remove them. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
2015-05-08MLK-10723-2 mxc IPUv3: Remove the ugly global variable g_ipu_hw_revLiu Ying
Let's replace the ulgy global variable g_ipu_hw_rev with the ipu->devtype. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
2015-05-08MLK-10723-1 mxc IPUv3: Remove some unused IPU deblock register basesLiu Ying
The driver doesn't have functional support for IPU_DISP0/1_BASE, IPU_ISP_REG_BASE, IPU_DP_REG_BASE, IPU_IRT_REG_BASE, IPU_LUT_REG_BASE, and IPU_ISP_TBPR_REG_BASE. Let's remove them to save some lines. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
2015-05-08MLK-10736 epdc: update rotation configuration according to pxp driver changeRobby Cai
The commit c01cdab21b1e3cc045f40f29ca0d9292d238ffda introduced a different configuration for rotation case in PxP driver, that is, it requires the rotated width and height value. Thus EPDC driver, the user of PxP driver should also adjust accordingly. Signed-off-by: Robby Cai <r63905@freescale.com>
2015-05-08MLK-10714 mxc IPUv3: PRE: Fix deadlock possibility in PRE interrupt handlerLiu Ying
The PRE interrupt handler is protected by the spin lock pre->lock. The spin lock is also locked/unlocked in non-interrupt contexts. So, we need to use spin_lock_irqsave() and spin_unlock_irqrestore() primitives in the non-interrupt contexts to avoid deadlock in the interrupt handler. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
2015-05-08MLK-10712 mxc IPUv3: PRG: Fix PRE/PRG muxingLiu Ying
The i.MX6QP IOMUX_GPR5 PRE_PRG_SEL0/1 fields control the PRE/PRG muxing. The muxing could be described by the following table. ------------------------------------------------------------------ |\ | PRG0/IPU0 | PRG1/IPU1 | | mux |-----------------------------------------------------------| | \ |ch0/ch23 |ch1/ch27 |ch2/ch28 |ch0/ch23 |ch1/ch27 |ch2/ch28 | |------------------------------------------------------------------| | PRE0 | fixed | n/a | n/a | n/a | n/a | n/a | |------------------------------------------------------------------| | PRE1 | n/a | A(2b'00)| A(2b'01)| n/a | A(2b'10)| A(2b'11)| |------------------------------------------------------------------| | PRE2 | n/a | B(2b'00)| B(2b'01)| n/a | B(2b'10)| B(2b'11)| |------------------------------------------------------------------| | PRE3 | n/a | n/a | n/a | fixed | n/a | n/a | ------------------------------------------------------------------ (Note - A: GPR5 bit12-13, B: GPR5 bit14-15) We should bind PRG[x] channel[y] with IPU[x] channel[y+26] statically instead of dynamically, where x=0or1, y=1or2. Also, the values for A/B cannot be the same due to a SoC design requirement(even if one of the PRE1/PRE2 is disabled, the two values cannot be the same). This patch fixes the PRE/PRG muxing logic. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
2015-05-08MLK-10610-3 pci: imx: refine pcie pm operationsRichard Zhu
- add the perst for imx pcie because that this signal is mandatory required to be asserted/de-asserted during suspend/resume. Otherwise, pcie ep maybe failed to resume back. - for imx7 pcie - use the external osc, otherwise the internal pll - adjust the ltssm de-assert - change the init of pcie to late_initcall, because the expansion spi gpio is used as pcie_rst_b and pcie_dis_b on imx7d/imx6qp boards, and pcie driver has to be loaded after spi/i2c driver is probed. - cansleep set value function should be used to manipulate the expansion gpios. Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
2015-05-08MLK-10610-2 gpio: 74x164: add the runtime pmRichard Zhu
Since the spi expansion gpio maybe manipulated, during spi driver is suspend. Such as the PCIE_RST_B on imx7d sdb board. Add runtime pm into spi expansion gpio driver Signed-off-by: Gao Pan <b54642@freescale.com> Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
2015-05-08MLK-10663: arm: imx: pinctrl-imx: fix support for iomuxc-lpsrAdrian Alonso
* Fix pinctrl-imx suport for iomuxc-lpsr daisy chain configuration * Add SHARE_INPUT_SELECT_REG to indicate that iomuxc-lpsr shares input select config register from iomuxc controller to properly set up iomuxc-lpsr pads than need daisy chain setup. Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Robin Gong <b38343@freescale.com>
2015-05-08MLK-10660-3 video: mxc ipuv3 fb: Correct prefetch flag if no PRE is availableLiu Ying
For those SoCs which have no PRE engines embedded, users may try to call the ioctrl MXCFB_SET_PREFETCH to enable the PRE. The ioctrl sets the flag mxcfbi->prefetch to be true to go for PRE allocation. It is doomed to fail and the users will have no chance to set the flag back to false. As a result, the framebuffer will not be responsive to the users' set_par ioctls. Let's set the current prefetch flag back to the prefetch flag in that case to avoid the situation. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
2015-05-08MLK-10660-2 mxc IPUv3: common/disp: Balance pixel clock enable/disable countLiu Ying
The usual sequence[1] to enable/disable a display channel is 1) ipu_init_channel() 2) ipu_init_channel_buffer() 3) ipu_enable_channel() -> enable pixel clock 4) ipu_disable_channel() 5) ipu_uninit_channel() -> disable pixel clock We currently enable pixel clock in ipu_enable_channel() while disable it in ipu_uninit_channel() to meet some critical pipeline on/off sequence. This will make the bail-out path for [1] fail to balance pixel clock enable/disable count if there is no flag to reflect the clock's status. For example, if we bail out after 1) by calling 5), we has the risk to additionally disable pixel clock for one time. This patch adds the pixel_clk_en[2] flags to help balance the count. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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