Age | Commit message (Collapse) | Author |
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Set default videomode during the dc probe. This patch enables
HDMI during the probe only and fixes following issues:
1. Until Xinit there was no display on HDMI.
2. Framebuffer console on HDMI needs it to be enabled well before
Xinit.
To avoide un-necessary powering on HDMI,Check HPD and enable HDMI
only if it's present.
Bug: 930136
Bug: 977705
Change-Id: Ifb71328e5df0ccbb5751669db71fd24719fe3738
Signed-off-by: Shashank Sharma <shashanks@nvidia.com>
Reviewed-on: http://git-master/r/100656
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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Add gpio irq masking in irq_sync_unlock.
Change-Id: I008caf58ae82d9ed888f4720f54675e9106f027d
Signed-off-by: Jinyoung Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/98664
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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Some boards don't have a vddio regulator for few rails hence not getting
the regulator handle. And we assume that those rails are always powered.
Hence rephrased the error message and lowered the loglevel to KERN_INFO.
Bug 976177
Change-Id: I92b82f75934eaf7137584a625065e3389b6ae1b7
Signed-off-by: Ramalingam C <ramalingamc@nvidia.com>
Reviewed-on: http://git-master/r/100490
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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Fix fps update condition in max77663_regulator_set_fps().
Bug 930883
Change-Id: I2f57603320a91b2727932586fc3c66d9de347d64
signed-off-by: Jinyoung Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/92707
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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Unmasked EN0 rising interrupt to generate fast PMU_INT by
EN0(POWER_KEY).
Bug 930883
Change-Id: I9a3d8c4f564e83deea86fbd3d05f14933a0b0f65
Signed-off-by: Jinyoung Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/98665
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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Remove UART clock enable code, as UART clock gating is not
needed in tibluesleep driver.
Remove un-wanted tasklets, workqueues and wakelocks
Remove extra lines and spaces
Change-Id: I422e09ece2c736c4a98911a5bd84029ad654cb08
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-on: http://git-master/r/96944
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Add config option to enable/disable nvmap page pools.
Change-Id: I873e81a675fecd768534d4ce03c2f8fdd3c6a063
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/100424
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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Changed the suspend resume logic as per new
UDC driver. Also, added few debug prints.
Bug 887361
Change-Id: I36ec1f160e8b4db54b5bd2153bdbf1c4fae1cc2a
Signed-off-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-on: http://git-master/r/99450
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
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Add High-speed USB device controller driver for tegra chips.
This can work in OTG device mode with tegra OTG driver.
Driver currently supports only UMTIP PHY.
Bug 887361
Change-Id: I63774a44e3bb607c93007b170ba8b811f96e43f8
Signed-off-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-on: http://git-master/r/97918
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
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when update_cdma_locked() is invoked, CDMA is not running
implies that the queue is cleared and we can return immediately.
Bug 960487
Change-Id: I599027906dc405f4490590443d4f4d5a3202b5b0
Reviewed-on: http://git-master/r/96650
(cherry picked from commit f297b4812d15540f4b14c87178662a7ca6575ce9)
Reviewed-on: http://git-master/r/99994
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Clean up #includes. Replace #includes with forward declarations where
possible, and remove extraneous #includes.
Bug 871237
Change-Id: I6942e0c632b42ad7009589ebdd78def88ae4baa4
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/99046
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
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The sequence of read fuse id is:
1. write to OTP index register 0x3d00.
2. read out byte from ox3d04.
3. repeat step 1 to the next byte with its index respectively.
also fixed ov5650_read_reg always fail issue.
bug 957657
Change-Id: I649a7765320d0d4be8111a7f523d8487b872b620
Signed-off-by: Charlie Huang <chahuang@nvidia.com>
Reviewed-on: http://git-master/r/98330
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Wei Chen <wechen@nvidia.com>
Reviewed-by: Frank Chen <frankc@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
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We found missed irq could be happened if clear all INT_STS_x register in one time.
Shadow register pushes the irq status after the first byte of INT_STS_x was cleared
The proposed way to clear interrupt is to write only one INT_STS_x register.
It will also clear the other two ones.
Bug 952476
Reviewed-on: http://git-master/r/93453
Signed-off-by: Steve Kuo <stevek@nvidia.com>
(cherry picked from commit 0c92f32e9e03defaeac991518b26134e59ef4db6)
Change-Id: I76179be4847f59a1687926b9b0dde6ebd3f58aa4
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/100306
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This reverts commit 9349cedf17f9b3c10760c8d48f831473f87a3a15.
It is reviewed on http://git-master/r/99635
It will cause HDMI power ON and emc clock bump up to 667Mhz
after resume from LP0.
bug 930136
Change-Id: I130494fdb381b3d322ac0e3fc8be2e44f2c2d7a7
Signed-off-by: Hunk Lin <hulin@nvidia.com>
Reviewed-on: http://git-master/r/100202
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
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Recent pinctrl discussions concluded that gpiolib APIs
should in fact do whatever is required to mux a GPIO onto
pins.
This change is based on the work done by Stephen Warren in mainline
kernel.
-----
commit 3e215d0a19c2a0c389bd9117573b6dd8e46f96a8
gpio: tegra: Hide tegra_gpio_enable/disable()
Recent pinctrl discussions concluded that gpiolib APIs should in fact do
whatever is required to mux a GPIO onto pins, by calling pinctrl APIs if
required. This change implements this for the Tegra GPIO driver, and removes
calls to the Tegra-specific APIs from drivers and board files.
----
Change-Id: I482ea5c177cf2ee6fa06ddac48b556f1508efacb
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/98466
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
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Bug 933653
Change-Id: If7ce4dc5129782a7e3487028d2dba01c9380ba90
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/98256
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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Change wlan interface from mlan to wlan.
Bug 954218
Change-Id: I5b2b2840a4830eda908a47cc0fc59d0479a1df34
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: http://git-master/r/98997
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Rakesh Kumar <krakesh@nvidia.com>
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The CL disables SDIO card clock when idle for Tegra 3 only.
Bonus: conditional build for some tegra 3 functionalities.
Bug 975541
Change-Id: I097c4771f3565bf9137d7854ada10c1fe8535056
Signed-off-by: Mursalin Akon <makon@nvidia.com>
Reviewed-on: http://git-master/r/99707
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Allen Martin <amartin@nvidia.com>
Reviewed-by: Peer Chen <pchen@nvidia.com>
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Set window enabled flag in pan display. This fixes a blank
window display while switching console from dc_ext device to
framebuffer device, and allows dc_ext and fbdev to co-exist.
Removed previous work around to unblank fb from
tegra_dc_blank function.
Bug: 970263
Bug: 963480
Change-Id: I9853da211f78815246965d240d1717345c5ab391
Signed-off-by: Shashank Sharma <shashanks@nvidia.com>
Reviewed-on: http://git-master/r/99422
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-by: Kiran Adduri <kadduri@nvidia.com>
Reviewed-by: Allen Martin <amartin@nvidia.com>
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Set default videomode during the dc probe. This patch enables
HDMI during the probe only and fixes following issues:
1. Until Xinit there was no display on HDMI.
2. Framebuffer console on HDMI needs it to be enabled well before
Xinit.
Bug: 930136
Change-Id: Ieaf5c69eefa4a6584893425ad4fd772bcd91ea11
Signed-off-by: Shashank Sharma <shashanks@nvidia.com>
Reviewed-on: http://git-master/r/99635
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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This reverts commit 90b79e5712300baab889772a5af348559ac95836.
Bug 955393
Change-Id: I0e2a15b7d0898dbbb62f09d8bd3502ec93366664
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/99261
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-by: Nirav Patel <nipatel@nvidia.com>
Reviewed-by: Adam Cheney <acheney@nvidia.com>
Tested-by: Adam Cheney <acheney@nvidia.com>
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Added support for enable/disable rails from user space.
bug 966960
Change-Id: Iae660699c60f537296f90508a78bd40959c46535
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/99186
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Hunk Lin <hulin@nvidia.com>
Tested-by: Hunk Lin <hulin@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Update correct status to fuel-gauge driver
when charger cable is disconnected.
Bug 960318
Change-Id: I4c3ad2030ada7c06825e80a3eb4697b669fe7cb6
Signed-off-by: Syed Rafiuddin <srafiuddin@nvidia.com>
Reviewed-on: http://git-master/r/98719
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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If sd power rail is not configured to FORCED_PWM_MODE or
FSRADE_DISABLE, clear corresponding bits(FPWM and FSRADE)
when initialization.
Change-Id: I4e08329a430c6ccf7179b77cc7a283460ffaedd1
Signed-off-by: Jinyoung Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/98715
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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Configure i2c client structure in update charger structure
only when the charger driver is in use.
If charger driver is not used return -ENODEV
Change-Id: Ib1bc99145ee75bea819f69157920f9096e5d40ba
Signed-off-by: Syed Rafiuddin <srafiuddin@nvidia.com>
Reviewed-on: http://git-master/r/98712
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Vcell is calculated based on upper 12msb's of ADC result.
Signed-off-by: Syed Rafiuddin <srafiuddin@nvidia.com>
Reviewed-on: http://git-master/r/95830
(cherry picked from commit e550636d9b03207b9d4fecf078168175964d85fd)
Change-Id: Ic2834d8c8576b938e9d7d400c2beeb459ddeb5fc
Reviewed-on: http://git-master/r/98669
Reviewed-by: Syed Rafiuddin <srafiuddin@nvidia.com>
Tested-by: Syed Rafiuddin <srafiuddin@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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setting max 2d clock can make noticeable performance difference
in 2d limited usecase such as buffer clearing
Change-Id: I40ef999e7eeebff45b657f00293608561cae831d
Signed-off-by: Donghan Ryu <dryu@nvidia.com>
Reviewed-on: http://git-master/r/98644
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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- Abort initialization if an I2C error to avoid excessive load on the I2C bus
since it is heavily used during initialization.
- Updated to the latest NVC framework.
- Added feature that allows for the key focus points to be set at runtime
and the relative positions recalculated.
Bug 929133
Bug 938934
Change-Id: Ida4ab885bf35057ae6df131e3ec3587a891a7dc9
Signed-off-by: Erik Lilliebjerg <elilliebjerg@nvidia.com>
Reviewed-on: http://git-master/r/93944
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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add Konfig to marvel 8797 and some tailing
space corrections.
Bug 954218
Change-Id: I2885f2a74dea14ffeeb5dad65e03e217c77c5013
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: http://git-master/r/98436
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Initial commit for Marvell sd8797 Wi-Fi driver
Package Ver: T3T-14.69.11.p111-M2614303_A0B0-MGPL
Bug 954218
Change-Id: I76fcadb5cda054d1e489c4cff77a3c461bdac742
Signed-off-by: Mohan T <mohant@nvidia.com>
Reviewed-on: http://git-master/r/97305
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Change line_length for 1080p mode in order to change
frame rate from 31.30 to 29.50 fps.
The reason that new fps is not 30 is because flicker
detection requires fps not to be multiples of 60/50Hz.
This change helps save power and lower the chance of frame
drop.
Bug 928296
Change-Id: I4fda13d9334c725754b3f5eab034309a1dfef3dc
Signed-off-by: Jihoon Bang <jbang@nvidia.com>
Reviewed-on: http://git-master/r/83636
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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When there is PMU interrupt we need to enable controller
clock. For this currently, work is being schedule, removing
this as clock can be enabled directly without scheduling
any work.
bug 925958
bug 941899
Signed-off-by: Andy Carman <acarman@nvidia.com>
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-on: http://git-master/r/88777
(cherry picked from commit fc31c04b7124f30970e862dd1b21a97d18dca38e)
Change-Id: I8f6e7325771219488440226ddde97a32da228608
Reviewed-on: http://git-master/r/97882
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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enable MMC_PM_IGNORE_PM_NOTIFY for all sd instances
Bug 956238
Bug 932086
Change-Id: I4d455e480eabace403719f1813d97abfa4d01924
Signed-off-by: naveen kumar arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/96071
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Rakesh Kumar <krakesh@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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Sometimes 3D unit comes up with incorrect scissor configuration.
Earlier patch added the scissor registers to the context save list,
but that did not solve the problem. Remove the extra registers, and
reset 3D after powering it up.
Bug 939307
Change-Id: Id795f2d99ec3c6b907da2785b1816ce753af7a3f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/87654
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Graziano Misuraca <gmisuraca@nvidia.com>
Tested-by: Graziano Misuraca <gmisuraca@nvidia.com>
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
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Bug 951349
Change-Id: I79fb2e49fa38b83af78323b5f5cf6dbca8fd83c2
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/98512
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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Add system suspend count and avoid urb activity during
system suspend. Use async autopm to avoid deadlock with
system suspend. Do not allocate rx urb's constantly -
allocate once upon init, free rx urb upon exit.
Bug 929408, 952748, 957354
Change-Id: I4ea050fc881528cf44d2039d42891e21c9df8c4e
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
(cherry picked from commit 8bd7322127ccf6727d949f4bc1b2a4eac4b6814e)
Reviewed-on: http://git-master/r/95166
Reviewed-by: Vinayak Pane <vpane@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Bug 953210
Change-Id: Id40b3fe90174a2a8c9a6faf3f35f61d9f7eeb642
Signed-off-by: Sayak Ghosh Choudhury <sayakc@nvidia.com>
Reviewed-on: http://git-master/r/98477
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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Inform DC register updated after we programmed. This eliminates
the display corruption while device enters and resumes from LP0.
Signed-off-by: Mark Zhang <markz@nvidia.com>
bug 964626
Change-Id: I4c655d4800474c675d4cdb6204d6fe66e8c6c4b5
Reviewed-on: http://git-master/r/98336
Tested-by: Mark Zhang <markz@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Peer Chen <pchen@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
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configure fuel-gauge to enter and exit hibernate mode
Change-Id: Ifaa471a4b796fc1aa2b30f109091227eb19cf6ae
Signed-off-by: Syed Rafiuddin <srafiuddin@nvidia.com>
Reviewed-on: http://git-master/r/97900
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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This change adds check for out of memory conditions
after memory allocations
Bug 967504
Change-Id: Icafc16528880ea376dd69a023570b85c25e3d057
Signed-off-by: Anton Kondratenko <akondratenko@nvidia.com>
Reviewed-on: http://git-master/r/97113
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Change-Id: I8aa25b03fe6801882b65209cb1a6e125ef27ac2c
Signed-off-by: Michael I. Gold <gold@nvidia.com>
Reviewed-on: http://git-master/r/98319
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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add trace_printk to log useful debug information.
Bug 870685
Change-Id: I29c0b1600f234ebb06d19c8b6c713b16f6e7643c
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/89204
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Prashant Malani <pmalani@nvidia.com>
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There are a couple of issues found in tegra_camera.
1. clock enable/disable is controlled by user space.
-> If client process crashes, there is no way to disable clock.
2. power enable/disable is associated with clock enable.
-> There is no reason to relate power with clock.
-> There is only one regulator for this driver.
-> As same as #1, it may leave power up when client process crashes.
3. driver allows multiple clients to access.
-> This is not the case for this driver.
This changes addresses the problems described above.
Bug 948780
Change-Id: Ie534771327175f56cf0e138f1c07096ddba470a8
Signed-off-by: Jihoon Bang <jbang@nvidia.com>
Reviewed-on: http://git-master/r/92386
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: David Schalig <dschalig@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
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Add nvavp_force_clock_stay_on ioctl which provides way for user-mode driver
to stay on AVP clock state. This change is to fix LP0 resume fail during
Widevine playback. Since VDE/BSEV clocks are used by OTF driver in secure
world during closing sesssion, the change makes VDE/BSEV clocks running
while entering LP0.
Bug 960130
Bug 961015
Change-Id: I7eaaa9a33537a72b6ae0a016372bc513fef532e2
Reviewed-on: http://git-master/r/96302
Reviewed-by: Hyung Taek Ryoo <hryoo@nvidia.com>
Tested-by: Hyung Taek Ryoo <hryoo@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Karan Jhavar <kjhavar@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
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In resuming from LP1, USB HOST is wrongly detected in Tegra2.
In that time, adb connection doesn't work also.
So clear only interrupt enabling bits to fix this problem.
Bug 960254
Bug 970012
Change-Id: I2f8e891ab2abcf8552526ff305d6f3a148076edd
Signed-off-by: Joshua Cha <joshuac@nvidia.com>
Reviewed-on: http://git-master/r/96769
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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TEGRA_DC_EXT_SET_LUT programmed the proper shadow registers
but did not copy the shadow registers to the active set.
Signed-off-by: Adam Cheney <acheney@nvidia.com>
bug 947281
Change-Id: Id734e128bb708f1a75c0cad22b0c51b083d8df3b
Reviewed-on: http://git-master/r/91368
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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Addition of callback function to nofity the plug and
un-plug of OTG cable to charger driver.
Change-Id: I6b16d051cafe0799cffe8a05d1510da27e841f8b
Signed-off-by: Syed Rafiuddin <srafiuddin@nvidia.com>
Reviewed-on: http://git-master/r/97514
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chandler Zhang <chazhang@nvidia.com>
Tested-by: Chandler Zhang <chazhang@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Disable card clock before disabling internal clock to
ensure that there are no abnormal clock waveforms.
Bug 947058
Change-Id: I98a3f7f63b4380b62bead05f1018d3cddc0ac217
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/95396
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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Disable SDIO card clock when there are no commands/
data transfers on the SD bus.
Bug 958954
Bug 955742
Bug 952344
Change-Id: I7390be0406f7e46c0eb88ede2ae6f904b2181306
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/95390
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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There is a chance that we might read an TD request which
has just arrived after fence read in a interrupt handler.
Added fence read in unmap urb to avoid this issue.
Bug 964879
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-on: http://git-master/r/95916
(cherry picked from commit 8d8415820014710052eef088ed2d579d0531cd52)
Change-Id: Ia682654a25c685cf3dd2e76c8b9ea30427a06d89
Reviewed-on: http://git-master/r/97507
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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