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Providing the different clock source option through platform data
to select best clock source based on required interface frequency.
bug 851642
Original-Change-Id: I18bf817b63cf1afac7db3969f266cc5fcaeee81e
Reviewed-on: http://git-master/r/41226
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Rebase-Id: Ra4e4573414ef2c4e72cdcb4cd5625e242cfb4ec6
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Supporting the hw based CS to communicate to spi device. This
provides the constraints in hold and setup time of CS before
clock start and clock ends.
The hw based CS can be selected if spi client provide the option
through the device controler data and only one transfer per
message is requested.
Original-Change-Id: I56d5e466361cb8b3710646e01494ddac46791ae4
Reviewed-on: http://git-master/r/23988
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Amit Kamath <akamath@nvidia.com>
Reviewed-by: Ramachandrudu Kandhala <rkandhala@nvidia.com>
Original-Change-Id: I52b1dcdefa199cd11ae7f838c61411a6268a2d32
Rebase-Id: Rd9f2c70e8c8551ea5ca6ce698a172ef00c08ca67
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Following are the fixes;
- Supportng half duplex.
- Only using SW based CS.
- Write to readback with command register does not work. Fixing issue.
- Using cpu based transfer for smaller size and dma based for larger size.
- reading proper transfer status after every transaction.
bug 791149
bug 791780
Original-Change-Id: I293b3f1b571276f5d8fe4ad4da67f827926e4b73
Reviewed-on: http://git-master/r/20581
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Amit Kamath <akamath@nvidia.com>
Rebase-Id: R29f88f7509bdb182f05916ecf31e1090b1b9d017
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