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Check property of usb hardware to get otg version and if SRP, HNP and ADP
are disabled.
Signed-off-by: Li Jun <jun.li@freescale.com>
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Add usb_otg_caps pointer to usb_gadget structure to indicate its
otg capabilities.
Signed-off-by: Macpaul Lin <macpaul@gmail.com>
Signed-off-by: Li Jun <jun.li@freescale.com>
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This patch adds a structure usb_otg_caps to cover all otg related
capabilities of the device, including otg revision, and if hnp/srp/adp
is supported.
Signed-off-by: Li Jun <jun.li@freescale.com>
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Add USB_OTG_ADP definition for usb_otg_descriptor.bmAttributes.
Signed-off-by: Macpaul Lin <macpaul@gmail.com>
Signed-off-by: Li Jun <jun.li@freescale.com>
Acked-by: Peter Chen <peter.chen@freescale.com>
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OTG 2.0 introduces bcdOTG in otg descriptor to identify the OTG and EH
supplement release number with which the OTG device is compliant, this
patch adds structure usb_otg20_descriptor for OTG 2.0 and above. Then
the bcdOTG should be removed for usb_otg_descriptor in gadget drivers.
Signed-off-by: Macpaul Lin <macpaul@gmail.com>
Signed-off-by: Li Jun <jun.li@freescale.com>
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HNP polling uses a kernel stack variable when sending the HNP polling
control message, which causes dma-debug to complain, fix it by adding
host_req_flag to otg_fsm struct, so it's done by kmallocing.
Signed-off-by: Li Jun <jun.li@freescale.com>
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When temperature >= the 'critical_trip' temperature, the common
framework code will call 'orderly_poweroff' function to power off
the system. During the power off procedure the thermal framework
will go on polling the temp, this will lead to recall the
'orderly_poweroff' again. In the first poweroff flow, some system
resource has been freezed, then if the secondary 'orderly_poweroff'
frees the resource again, it will lead to kernel dump.
Signed-off-by: Bai Ping <b51503@freescale.com>
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* Add ADC root clock IMX7D_ADC_ROOT_CLK
* Update device tree adc node to use IMX7D_ADC_ROOT_CLK
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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correct the clock for CSI
Signed-off-by: Robby Cai <r63905@freescale.com>
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Add mipi csi bits define in gpr head file.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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ADP(Attach Detection Protocol) is part of USB OTG 2.0 release, which can be
used to find device attachment after session ends(vbus is off). This patch adds
OTG ADP feature for chipdea usb driver.
Signed-off-by: Li Jun <jun.li@freescale.com>
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When otg fsm leaves a_idle or b_idle, ADP probe and sense should be stopped,
therefore ADP timers should be removed.
Signed-off-by: Li Jun <jun.li@freescale.com>
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Check property of usb hardware to get if ADP is supported.
Signed-off-by: Li Jun <jun.li@freescale.com>
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- enable the rpmsg support for imx amp soc
- add the notify mechanism to notify imx_rpmsg in mu isr
when there is msg sent from remote m4.
- Make sure that the vring alignment is 4096 on both linux and mqx
- add double check on MU msg transfer, make sure that the MU MSG is
handled by the other side core.
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
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per_bch is used for fabric, need to be enabled when using
bch for RAWNAND operation.
Signed-off-by: Bai Ping <b51503@freescale.com>
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B-device detects that bus is idle for more than TB_AIDL_BDIS min and begins HNP
by turning off pullup on DP, this allows the bus to discharge to the SE0 state.
This timer was missed and failed with one PET test, this patch is to fix this
timing issue.
Signed-off-by: Li Jun <b47624@freescale.com>
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This patch adds a flag hnp_polling to indicate if HNP polling is supported.
Signed-off-by: Li Jun <b47624@freescale.com>
(cherry picked from commit b19d4b1110fe1fb2ec3141233781a1e016c9a9cf)
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After B device as host enumerates A peripheral and sets configuration,
B host should start to hand host role back to A device when this timer
expires.
Acked-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Li Jun <b47624@freescale.com>
(cherry picked from commit 3f4a8c8a20ef69721f9e7886b8d245036d41d91a)
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This patch adds flag otg_hnp_reqd in struct otg_fsm to indicate A device
as host wants to start HNP sequence.
Acked-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Li Jun <b47624@freescale.com>
(cherry picked from commit 92382e06c6902731b05dcbb0db4f0ebfa486969f)
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This patch adds otg_hnp_reqd wIndex high byte value for otg test mode.
Acked-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Li Jun <b47624@freescale.com>
(cherry picked from commit c334dc80bc2672aab012cad6926d819feaf4634d)
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This patch adds a timer for chipidea otg fsm driver to start data pulse
after A host ends the session.
Acked-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Li Jun <b47624@freescale.com>
(cherry picked from commit 35e92b59080b58925c3b96e36511056cb51d4a00)
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This patch adds flag otg_srp_reqd in struct otg_fsm to indicate A device
as host wants B-UUT to do SRP once it ends the session.
Acked-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Li Jun <b47624@freescale.com>
(cherry picked from commit 8e5f1b6b12ec77ec591909b09727049ffff37b9c)
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This patch adds otg_srp_reqd wIndex high byte value for otg test mode.
Acked-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Li Jun <b47624@freescale.com>
(cherry picked from commit 34660f7aa14972630622406b9dbfc7a106d8d15d)
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This patch adds 2 variables: tst_maint and otg_vbus_off, tst_maint is to check if
current session for test device; otg_vbus_off is to notify if A device need turn
off vbus immediately after B device disconnects.
The otg test device handling is added into ehset driver, for that device,
A-device should start a timer for maintain the session, and set otg_vbus_off
flag according to its bcdDevice value.
Acked-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Li Jun <b47624@freescale.com>
(cherry picked from commit 78a2c14bdea4b8e334c7e0afad074b61b71193cb)
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The initial source code for the new mipi dsi module which can
support the basic necessary functions(blank/unblank, set brightness
and etc). New functions can be added if required later.
Signed-off-by: Fancy Fang <chen.fang@freescale.com>
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Add IMX7D_OCOTP_CLK, sourcing from ipg_root_clk.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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During the read of NOR, the kernel actually calls the inline_map_copy_from()
to read the data out. And inline_map_copy_from() will use the memcpy_fromio()
to do the real job.
The memcpy_fromio macro maps _memcpy_fromio() in the current code.
But the _memcpy_fromio() will use readb() to do the copy work one byte
by one byte. This makes the read performance of NOR very slow(about 2~3MB/s).
A similiar discussion could be found in:
http://lists.infradead.org/pipermail/linux-arm-kernel/2009-November/003860.html
This patch replace the memcpy_fromio with memcpy which is optimized by the
kernel.
The following is the result from mtd_speedtest with M29W256GL7AN6E:
=================================================
mtd_speedtest: MTD device: 2
mtd_speedtest: not NAND flash, assume page size is 512 bytes.
mtd_speedtest: MTD device size 4194304, eraseblock size 131072, page size 512,
count of eraseblocks 32, pages per eraseblock 256, OOB size 0
mtd_speedtest: testing eraseblock write speed
mtd_speedtest: eraseblock write speed is 845 KiB/s
mtd_speedtest: testing eraseblock read speed
mtd_speedtest: eraseblock read speed is 19504 KiB/s
mtd_speedtest: testing page write speed
mtd_speedtest: page write speed is 845 KiB/s
mtd_speedtest: testing page read speed
mtd_speedtest: page read speed is 19140 KiB/s
mtd_speedtest: testing 2 page write speed
mtd_speedtest: 2 page write speed is 846 KiB/s
mtd_speedtest: testing 2 page read speed
mtd_speedtest: 2 page read speed is 19320 KiB/s
mtd_speedtest: Testing erase speed
mtd_speedtest: erase speed is 233 KiB/s
mtd_speedtest: Testing 2x multi-block erase speed
mtd_speedtest: 2x multi-block erase speed is 225 KiB/s
mtd_speedtest: Testing 4x multi-block erase speed
mtd_speedtest: 4x multi-block erase speed is 224 KiB/s
mtd_speedtest: Testing 8x multi-block erase speed
mtd_speedtest: 8x multi-block erase speed is 225 KiB/s
mtd_speedtest: Testing 16x multi-block erase speed
mtd_speedtest: 16x multi-block erase speed is 225 KiB/s
mtd_speedtest: Testing 32x multi-block erase speed
mtd_speedtest: 32x multi-block erase speed is 225 KiB/s
mtd_speedtest: Testing 64x multi-block erase speed
mtd_speedtest: 64x multi-block erase speed is 224 KiB/s
mtd_speedtest: finished
=================================================
(cherry-picked from: f1e5914ffd82d5326cbd30507d4f37d02a0da099)
Signed-off-by: Huang Shijie <b32955@freescale.com>
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CAAM only has a single clock in i.mx7d. Logic was added to initialize only the
single clock.
The Secure Memory registers moved in CAAM era included in i.mx7d. This required
changes to support access to two different versions of the register map. The
registers are access through a data structure that overlay the register region.
Two new Secure Memory register structures were created to support the different
versions. Logic was also added to determine which version is implemented based on
the CAAM era, and access functions were added to support register access to the
Secure Memory Command and Status registers.
Signed-off-by: Dan Douglass <dan.douglass@freescale.com>
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For some platforms, time delay is requried between putting PHY into low power
mode and gate PHY clock.
Signed-off-by: Li Jun <jun.li@freescale.com>
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Add ksz8081 resume function since the phy has some non-standard
register init process that has some fixup.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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Set the usb_otg_pll as the pareent of clks[IMX6UL_CLK_SIM_PRE_SEL].The RM is wrong
in description of 6~9 bit of CCM_CCGR6. These are used as clock gate of SIM1 and SIM2.
Update the clock tree code.
Signed-off-by: Luwei Zhou <b45643@freescale.com>
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On i.MX6UL, the 'CA7_SECONDARY_SEL' clk can be used by the ARM core
as clock source.
Signed-off-by: Bai Ping <b51503@freescale.com>
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As busfreq need to cover both i.MX6 and i.MX7
and maybe later SoCs, so better to change the
name to support common imx SoC.
Signed-off-by: Anson Huang <b20788@freescale.com>
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No need to add audio mclk for imx6ul, because codec mclk is routing from
sai2 mclk instead of audio mclk.
This reverts commit 18283848bcf6ee5a6e713517a5e35e21c5b7b657.
Signed-off-by: Zidan Wang <zidan.wang@freescale.com>
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add audio mclk for imx6ul
Signed-off-by: Zidan Wang <zidan.wang@freescale.com>
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B_DATA_PLS(data-line pulse time) and B_SSEND_SRP(session end to SRP init) are
also from OTG&EH 2.0 Specification and they are not chipidea specific.
Signed-off-by: Li Jun <jun.li@freescale.com>
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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1. add enet2 clock init
2. add micrel phy fixup for MII mode
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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i.MX6UL is a new SOC, add MSL support, including
timer, clk tree and cpu etc..
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Bai Ping <b51503@freescale.com>
Signed-off-by: Fugang Duan <B38611@freescale.com>
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Add new SOC i.MX6UL dtb file support, including ddr3
arm2 board support, clock file and pinfunc head file.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Bai Ping <b51503@freescale.com>
Signed-off-by: Fugang Duan <B38611@freescale.com>
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defined.
Kernel build fails when CPU_FREQ or CPU_IDLE is disabled in the kernel config.
This patch fixes the problem.
When CPU_FREQ is disabled the system will run at the frequency setup by
uboot.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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The driver doesn't have functional support for IPU_DISP0/1_BASE,
IPU_ISP_REG_BASE, IPU_DP_REG_BASE, IPU_IRT_REG_BASE, IPU_LUT_REG_BASE,
and IPU_ISP_TBPR_REG_BASE. Let's remove them to save some lines.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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The i.MX6QP IOMUX_GPR5 PRE_PRG_SEL0/1 fields control the PRE/PRG muxing.
The muxing could be described by the following table.
------------------------------------------------------------------
|\ | PRG0/IPU0 | PRG1/IPU1 |
| mux |-----------------------------------------------------------|
| \ |ch0/ch23 |ch1/ch27 |ch2/ch28 |ch0/ch23 |ch1/ch27 |ch2/ch28 |
|------------------------------------------------------------------|
| PRE0 | fixed | n/a | n/a | n/a | n/a | n/a |
|------------------------------------------------------------------|
| PRE1 | n/a | A(2b'00)| A(2b'01)| n/a | A(2b'10)| A(2b'11)|
|------------------------------------------------------------------|
| PRE2 | n/a | B(2b'00)| B(2b'01)| n/a | B(2b'10)| B(2b'11)|
|------------------------------------------------------------------|
| PRE3 | n/a | n/a | n/a | fixed | n/a | n/a |
------------------------------------------------------------------
(Note - A: GPR5 bit12-13, B: GPR5 bit14-15)
We should bind PRG[x] channel[y] with IPU[x] channel[y+26] statically
instead of dynamically, where x=0or1, y=1or2. Also, the values for A/B
cannot be the same due to a SoC design requirement(even if one of the
PRE1/PRE2 is disabled, the two values cannot be the same). This patch
fixes the PRE/PRG muxing logic.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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According the latest Reference Manual of i.MX6QP, the GPU3d_AXI_CLOCK_ROOT
and GPU2D_AXI_CLOCK_ROOT are derived from MMDC_CH0_AXI_CLOCK_ROOT. The origin
GPU2D_AXI_CLOCK_ROOT in CCM is not used anymore, the origin GPU3D_AXI_CLOCK_ROOT
in CCM is change to PRE_CLOCK_ROOT used by the PRE0/1/2/3.
Tested-by: Liu Ying <Ying.Liu@freescale.com>
Signed-off-by: Bai Ping <b51503@freescale.com>
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platform.
This driver is based on the current code which runs the the EMV test on the i.MX258 platform.
Since there are still many cases that can't pass on the i.MX258 and i.MX7d platform. The
driver will need to be improved after per-test work. Just check in as a base code. There
would be definitly some timing improvement work to do in the future.
Signed-off-by: Luwei Zhou <b45643@freescale.com>
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parent on
On Freescale i.MX7D platform, all clocks operations, including enable/disable,
rate change and re-parent, requires its parent clock on.
Current clock core can not support it well.
This patch introduce a new flag CLK_SET_PARENT_ON to handle this special case
in clock core that enable its parent clock firstly for each operation and disable
it later after operation complete.
The most special case is for set_parent() operation which requires both parent,
old one and new one, to be enabled at the same time during the operation.
Acked-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
Signed-off-by: Dong Aisheng <b29396@freescale.com>
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DRAM PLL is a audio/video type PLL, need to correct
it to get correct ops of PLL.
There is a test_div placed before DRAM PLL's gate, so
add this test div clk.
Signed-off-by: Anson Huang <b20788@freescale.com>
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- enable sema4 on imx7d, and verified on imx7d mcc
pingpong tests.
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
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- use dsb() to make sure the consistence of the share
memory , because that share memory is located in ddr memory,
it maybe buffer-able although it is remapped as nocache
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
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- add imx7d sema4 and mu root clocks
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
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Add clk divider for i.MX7D AUDIO/VIDEO PLL, there are two
diviers for audio pll, one is test_div and the other
is post div, per design team's saying, test_div is
placed before PLL gate and post div is placed after
PLL gate.
Signed-off-by: Anson Huang <b20788@freescale.com>
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