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Add alsa controls to specify which alsa device is used by AVP to render
audio. Also add support for disabling DMA interrupt when AVP renders
audio. Also add couple of alsa controls to query DMA channel ID and
DMA buffer physical address.
Bug 968814
Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com>
Change-Id: If593329db72bf00d97f7433f5c54e13500281253
Reviewed-on: http://git-master/r/97916
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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Change prototype of tegra_asoc_utils_init to pass snd_soc_card handle.
It is needed to move common tegra machine driver codes to
tegra_asoc_utils interface.
Bug 968814
Change-Id: I98490ffdda51cf7d0b89adadb23c31892183bc0e
Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-on: http://git-master/r/97914
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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Support I2S slave mode. Disable pll_p_out1 and
pll_a to reduce power when in slave mode.
Slave mode disabled by default.
Reviewed-on: http://git-master/r/76046
Change-Id: I873a11d54f1e037d99c86ff4cec06ee83064902a
Signed-off-by: ScottPeterson <speterson@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77765
Reviewed-by: Automatic_Commit_Validation_User
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Expose a new API to lock pll_a, pll_a_out0 and mclk rates. Any dai-link
which sets any of these clocks should call this API from hwparam() to
lock these rates and should release the lock once dai-link shutdown
is called. When lock is held by any dai-link request for change in any
of these clocks will not be granted.
Bug 872652
Change-Id: I583b4849acde7e588531e60c6c5cd5156badb4f2
Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-on: http://git-master/r/63828
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Rebase-Id: R044806997c82a11115a6a110196ac82402aceca5
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add code to enable/disable pll_a and cdev1 clocks
Bug: 862023
Change-Id: If5b6014f82651e2286802ba6d76f77b1b5419b41
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/61085
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Rddb3206531e76e7ea28df691f6aa86a50f7c66d0
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Tegra30 has some additional clocks that need to be manipulated, names
some clocks differently, runs PLLs at different base rates, etc. The
utility code needs to handle this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Rebase-Id: R295313c25d9eae15a7cc423953f50f9132790c9e
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Only the clock programming code needs to know whether the clocks changed,
and that is encapsulated within tegra_asoc_utils_set_rate(). The machine
driver's call to snd_soc_dai_set_sysclk(codec_dai, ...) is safe
irrespective of whether the clocks changed.
(Applying Mark's TrimSlice review comments to the existing driver)
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Liam Girdwood <lrg@ti.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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Instead, have the machine driver provide storage for the utility data
somehow.
For Harmony in particular, store this within struct tegra_harmony, itself
referenced by snd_soc_card's drvdata.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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Many portions of Tegra ASoC machine drivers will be similar or identical.
To avoid cut/paste, this file will act as a repository for all that common
code. For now, it solely includes code to reprogram the audio PLL for
44.1KHz- vs. 48KHz-based sample rates.
Signed-Off-By: Stephen Warren <swarren@nvidia.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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