From 9ef3e8ecc0f1c9a3bfad7c9f4d6a496c4a67924c Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Wed, 23 May 2012 19:08:23 +0530 Subject: spi: tegra: synchronize PPSB late write When any write is made to PPSB register, it take time to actual happen in the register due to ARM-PPSB design. Delay or readback is required to make sure that write is completed. There is no worst case guaranteed delay and hence doing the register read to make write completes actually. Change-Id: Iefd25115e1a9f02c64e83f11a4e249ad9d086d16 Signed-off-by: Laxman Dewangan Reviewed-on: http://git-master/r/102207 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bitan Biswas --- drivers/spi/spi-tegra.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/spi/spi-tegra.c b/drivers/spi/spi-tegra.c index 0a0a72f3437f..070cc1581efd 100644 --- a/drivers/spi/spi-tegra.c +++ b/drivers/spi/spi-tegra.c @@ -264,6 +264,9 @@ static inline void spi_tegra_writel(struct spi_tegra_data *tspi, if (!tspi->clk_state) BUG(); writel(val, tspi->base + reg); + + /* Synchronize write by reading back the register */ + readl(tspi->base + SLINK_MAS_DATA); } static void cancel_dma(struct tegra_dma_channel *dma_chan, @@ -1584,6 +1587,9 @@ static int tegra_spi_runtime_idle(struct device *dev) struct spi_master *master = dev_get_drvdata(dev); struct spi_tegra_data *tspi = spi_master_get_devdata(master); + /* Flush all write which are in PPSB queue by reading back */ + spi_tegra_readl(tspi, SLINK_MAS_DATA); + tspi->clk_state = 0; clk_disable(tspi->clk); clk_disable(tspi->sclk); -- cgit v1.2.3