From a91a076d29abed946577f1c002a5f62fce1ef9e7 Mon Sep 17 00:00:00 2001 From: Wojciech Bieganski Date: Wed, 8 Feb 2017 12:15:48 +0100 Subject: media: tegra_camera: add continuous clk support Signed-off-by: Wojciech Bieganski Acked-by: Marcel Ziswiler --- arch/arm/mach-tegra/board-apalis-tk1-sensors.c | 2 +- drivers/media/platform/soc_camera/tegra_camera/vi2.c | 15 ++++++++++----- 2 files changed, 11 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-tegra/board-apalis-tk1-sensors.c b/arch/arm/mach-tegra/board-apalis-tk1-sensors.c index 8f511bf45bbb..fb11b5f80467 100644 --- a/arch/arm/mach-tegra/board-apalis-tk1-sensors.c +++ b/arch/arm/mach-tegra/board-apalis-tk1-sensors.c @@ -449,7 +449,7 @@ static struct tegra_camera_platform_data apalis_tk1_adv7280_camera_platform_data .flip_h = 0, .port = TEGRA_CAMERA_PORT_CSI_C, .lanes = 1, - .continuous_clk = 0, + .continuous_clk = 1, }; static struct soc_camera_link adv7280_iclink_c = { diff --git a/drivers/media/platform/soc_camera/tegra_camera/vi2.c b/drivers/media/platform/soc_camera/tegra_camera/vi2.c index a027c1c95f03..fb03bb7854b1 100644 --- a/drivers/media/platform/soc_camera/tegra_camera/vi2.c +++ b/drivers/media/platform/soc_camera/tegra_camera/vi2.c @@ -637,8 +637,10 @@ static int vi2_capture_setup_csi_0(struct tegra_camera_dev *cam, 0x3 | (0x1 << 5) | (0x40 << 8)); #endif - TC_VI_REG_WT(cam, TEGRA_CSI_PHY_CILA_CONTROL0, 0x45); - TC_VI_REG_WT(cam, TEGRA_CSI_PHY_CILB_CONTROL0, 0x45); + TC_VI_REG_WT(cam, TEGRA_CSI_PHY_CILA_CONTROL0, + ((pdata->continuous_clk << 6) | 0x05)); + TC_VI_REG_WT(cam, TEGRA_CSI_PHY_CILB_CONTROL0, + ((pdata->continuous_clk << 6) | 0x05)); TC_VI_REG_WT(cam, TEGRA_CSI_PIXEL_STREAM_PPA_COMMAND, 0xf007); TC_VI_REG_WT(cam, TEGRA_CSI_CSI_PIXEL_PARSER_A_INTERRUPT_MASK, 0x0); TC_VI_REG_WT(cam, TEGRA_CSI_PIXEL_STREAM_A_CONTROL0, 0x280301f0); @@ -742,10 +744,13 @@ static int vi2_capture_setup_csi_1(struct tegra_camera_dev *cam, #endif if (pdata->port == TEGRA_CAMERA_PORT_CSI_B) { - TC_VI_REG_WT(cam, TEGRA_CSI_PHY_CILC_CONTROL0, 0x45); - TC_VI_REG_WT(cam, TEGRA_CSI_PHY_CILD_CONTROL0, 0x45); + TC_VI_REG_WT(cam, TEGRA_CSI_PHY_CILC_CONTROL0, + ((pdata->continuous_clk << 6) | 0x05)); + TC_VI_REG_WT(cam, TEGRA_CSI_PHY_CILD_CONTROL0, + ((pdata->continuous_clk << 6) | 0x05)); } else if (pdata->port == TEGRA_CAMERA_PORT_CSI_C) - TC_VI_REG_WT(cam, TEGRA_CSI_PHY_CILE_CONTROL0, 0x45); + TC_VI_REG_WT(cam, TEGRA_CSI_PHY_CILE_CONTROL0, + ((pdata->continuous_clk << 6) | 0x05)); TC_VI_REG_WT(cam, TEGRA_CSI_PIXEL_STREAM_PPB_COMMAND, 0xf007); TC_VI_REG_WT(cam, TEGRA_CSI_CSI_PIXEL_PARSER_B_INTERRUPT_MASK, 0x0); -- cgit v1.2.3