From e4b7f6538df9266d9ab71f4bd6a5bc75df6c2cde Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Mon, 17 Feb 2020 13:46:57 +0800 Subject: MLK-23326 arm64: dts: imx8mn-evk: Correct 1.2GHz OPP voltage When running at OD mode, VDD_ARM can NOT be lower than VDD_SOC, overwrite the 1.2GHz OPP's voltage to be same as VDD_SOC. Signed-off-by: Anson Huang Reviewed-by: Jacky Bai (cherry picked from commit 77714128a1da83fbc516b41206574e2e62348dc8) --- arch/arm64/boot/dts/freescale/fsl-imx8mn-evk.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mn-evk.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mn-evk.dts index de29477b03af..f5f139cfff84 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8mn-evk.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mn-evk.dts @@ -937,6 +937,12 @@ }; &A53_0 { + operating-points = < + /* kHz uV */ + 1500000 1000000 + 1400000 950000 + 1200000 950000 + >; arm-supply = <&buck2_reg>; }; -- cgit v1.2.3 From 5ae5b1903d4135f69e1e8b805d5872af0cd76176 Mon Sep 17 00:00:00 2001 From: Iuliana Prodan Date: Mon, 17 Feb 2020 03:05:10 +0200 Subject: LF-838: crypto: caam - increase the domain of write memory barrier to full system MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In caam_jr_enqueue, under heavy DDR load, smp_wmb() or dma_wmb() fail to make the input ring be updated before the CAAM starts reading it. So, CAAM will process, again, an old descriptor address and will put it in the output ring. This will make caam_jr_dequeue() to fail, since this old descriptor is not in the software ring. To fix this, use wmb() which works on the full system instead of inner/outer shareable domains. Signed-off-by: Iuliana Prodan Reviewed-by: Horia Geantă Signed-off-by: Leonard Crestez (cherry picked from commit e4978516eeacb083412753dbc523de7d9dca8463) It looks like this also fixes MLK-23259, so cherry-pick from LF linux-lts-nxp:lf-5.4.y into linux-imx:imx_4.14.y. Signed-off-by: Horia Geantă --- drivers/crypto/caam/jr.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/crypto/caam/jr.c b/drivers/crypto/caam/jr.c index 15371c3d5efa..aca752562821 100644 --- a/drivers/crypto/caam/jr.c +++ b/drivers/crypto/caam/jr.c @@ -452,8 +452,16 @@ int caam_jr_enqueue(struct device *dev, u32 *desc, * Guarantee that the descriptor's DMA address has been written to * the next slot in the ring before the write index is updated, since * other cores may update this index independently. + * + * Under heavy DDR load, smp_wmb() or dma_wmb() fail to make the input + * ring be updated before the CAAM starts reading it. So, CAAM will + * process, again, an old descriptor address and will put it in the + * output ring. This will make caam_jr_dequeue() to fail, since this + * old descriptor is not in the software ring. + * To fix this, use wmb() which works on the full system instead of + * inner/outer shareable domains. */ - smp_wmb(); + wmb(); jrp->inp_ring_write_index = (jrp->inp_ring_write_index + 1) & (JOBR_DEPTH - 1); -- cgit v1.2.3 From 54312465a5121aed8bd7eaf5ce40d893a1ef19e1 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Mon, 17 Feb 2020 19:19:07 +0800 Subject: MLK-23331 arm64: dts: imx8mn: Update settings according to latest datasheet According to latest datasheet Rev.0.1, 03/2020, VDD_ARM does NOT have dependency on VDD_SOC, so below table in datasheet can be used directly for VDD_ARM: Clock Voltage 1.2GHz 0.85V 1.4GHz 0.95V 1.5GHz 1.0V For DDR4 EVK board, system runs at nominal mode, so GPU can ONLY run up to 400MHz. For LPDDR4 EVK board, system runs at over-drive mode, so GPU can run up to 600MHz. Signed-off-by: Anson Huang Reviewed-by: Jacky Bai (cherry picked from commit e619dfe015d96f9322b59f386e00167ec1aab321) --- arch/arm64/boot/dts/freescale/fsl-imx8mn-ddr4-evk.dts | 19 +++++++++++++------ arch/arm64/boot/dts/freescale/fsl-imx8mn-evk.dts | 6 ------ 2 files changed, 13 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mn-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mn-ddr4-evk.dts index 86e2c78e99ff..c90b9ce20005 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8mn-ddr4-evk.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mn-ddr4-evk.dts @@ -966,12 +966,6 @@ }; &A53_0 { - operating-points = < - /* kHz uV */ - 1500000 1000000 - 1400000 950000 - 1200000 950000 - >; arm-supply = <&buck2_reg>; }; @@ -984,6 +978,19 @@ }; &gpu { + assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE_SRC>, + <&clk IMX8MN_CLK_GPU_SHADER_SRC>, + <&clk IMX8MN_CLK_GPU_AXI>, + <&clk IMX8MN_CLK_GPU_AHB>, + <&clk IMX8MN_GPU_PLL>, + <&clk IMX8MN_CLK_GPU_CORE_DIV>, + <&clk IMX8MN_CLK_GPU_SHADER_DIV>; + assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>, + <&clk IMX8MN_GPU_PLL_OUT>, + <&clk IMX8MN_SYS_PLL1_800M>, + <&clk IMX8MN_SYS_PLL1_800M>; + assigned-clock-rates = <0>, <0>, <800000000>, <400000000>, <1200000000>, + <400000000>, <400000000>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mn-evk.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mn-evk.dts index f5f139cfff84..de29477b03af 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8mn-evk.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mn-evk.dts @@ -937,12 +937,6 @@ }; &A53_0 { - operating-points = < - /* kHz uV */ - 1500000 1000000 - 1400000 950000 - 1200000 950000 - >; arm-supply = <&buck2_reg>; }; -- cgit v1.2.3 From 22b12c5f04d4a5b2247239ccdcf4d9f1e99826c6 Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Tue, 25 Feb 2020 14:02:52 +0800 Subject: MLK-23233-1 dt-bindings: ata: add the peripheral clocks for imx8qm sata Add the documentation for the peripheral clocks required by iMX8QM SATA to access the HSIO MIX regions. Signed-off-by: Richard Zhu --- Documentation/devicetree/bindings/ata/imx-sata.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/ata/imx-sata.txt b/Documentation/devicetree/bindings/ata/imx-sata.txt index 49c4135dd9f2..d4bfd51443d5 100644 --- a/Documentation/devicetree/bindings/ata/imx-sata.txt +++ b/Documentation/devicetree/bindings/ata/imx-sata.txt @@ -26,6 +26,8 @@ Optional properties: - fsl,phy-imp: PHY impedance ratio value refer to the differnt HW design. Set it to 0x6c when 85OHM is used, keep it to default value 0x80 when 100OHM is used. +- clock-names : imx8qm sata requires some extra cloks "per_clk0", + "per_clk1", "per_clk2","per_clk3", "per_clk4", "per_clk5", Examples: -- cgit v1.2.3 From e7e4a80d6b9a233ab79bc63c19f41267c3dcfe3c Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Wed, 15 Jan 2020 15:13:15 +0800 Subject: MLK-23233-2 dts: arm64: sata: add the clks into sata nodes To avoid potential dump when access the PHY and MISC CRR registers. Add the CRRS clocks into SATA node. The codes are merged back from 4.19 to 4.14 refer to MLK-21695. Signed-off-by: Richard Zhu --- arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi index 58ca9fcd3540..b7733b1c3e19 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi @@ -4180,10 +4180,18 @@ <&clk IMX8QM_HSIO_PHY_X1_PCLK>, <&clk IMX8QM_HSIO_SATA_EPCS_TX_CLK>, <&clk IMX8QM_HSIO_SATA_EPCS_RX_CLK>, + <&clk IMX8QM_HSIO_PCIE_X1_PER_CLK>, + <&clk IMX8QM_HSIO_PCIE_X2_PER_CLK>, + <&clk IMX8QM_HSIO_SATA_PER_CLK>, + <&clk IMX8QM_HSIO_PHY_X1_PER_CLK>, + <&clk IMX8QM_HSIO_PHY_X2_PER_CLK>, + <&clk IMX8QM_HSIO_MISC_PER_CLK>, <&clk IMX8QM_HSIO_PHY_X2_PCLK_0>, <&clk IMX8QM_HSIO_PHY_X2_PCLK_1>, <&clk IMX8QM_HSIO_PHY_X1_APB_CLK>; clock-names = "sata", "sata_ref", "epcs_tx", "epcs_rx", + "per_clk0", "per_clk1", "per_clk2", + "per_clk3", "per_clk4", "per_clk5", "phy_pclk0", "phy_pclk1", "phy_apbclk"; hsio = <&hsio>; power-domains = <&pd_sata0>; -- cgit v1.2.3 From 041b7a6f981bbf4785c83d747f71684b131f1ebd Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Wed, 15 Jan 2020 15:13:44 +0800 Subject: MLK-23233-3 ata: imx: add the clks into sata driver To avoid potential dump when access the PHY and MISC CRR registers. Add the CRRS clocks into SATA driver. The codes are merged back from 4.19 to 4.14 refer to MLK-21695. Signed-off-by: Richard Zhu --- drivers/ata/ahci_imx.c | 137 +++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 120 insertions(+), 17 deletions(-) diff --git a/drivers/ata/ahci_imx.c b/drivers/ata/ahci_imx.c index e50c8b7dbc77..95f2b28ef35c 100644 --- a/drivers/ata/ahci_imx.c +++ b/drivers/ata/ahci_imx.c @@ -148,6 +148,12 @@ struct imx_ahci_priv { struct clk *phy_apbclk; struct clk *phy_pclk0; struct clk *phy_pclk1; + struct clk *per_clk0; + struct clk *per_clk1; + struct clk *per_clk2; + struct clk *per_clk3; + struct clk *per_clk4; + struct clk *per_clk5; void __iomem *phy_base; int clkreq_gpio; struct regmap *gpr; @@ -483,39 +489,112 @@ static struct attribute *fsl_sata_ahci_attrs[] = { }; ATTRIBUTE_GROUPS(fsl_sata_ahci); -static int imx8_sata_enable(struct ahci_host_priv *hpriv) +static int imx8_sata_clk_enable(struct imx_ahci_priv *imxpriv) { - u32 val, reg; - int i, ret; - struct imx_ahci_priv *imxpriv = hpriv->plat_data; + int ret; struct device *dev = &imxpriv->ahci_pdev->dev; /* configure the hsio for sata */ ret = clk_prepare_enable(imxpriv->phy_pclk0); if (ret < 0) { - dev_err(dev, "can't enable phy pclk0.\n"); + dev_err(dev, "can't enable phy_pclk0.\n"); return ret; } ret = clk_prepare_enable(imxpriv->phy_pclk1); if (ret < 0) { - dev_err(dev, "can't enable phy pclk1.\n"); + dev_err(dev, "can't enable phy_pclk1.\n"); goto disable_phy_pclk0; } ret = clk_prepare_enable(imxpriv->epcs_tx_clk); if (ret < 0) { - dev_err(dev, "can't enable epcs tx clk.\n"); + dev_err(dev, "can't enable epcs_tx_clk.\n"); goto disable_phy_pclk1; } ret = clk_prepare_enable(imxpriv->epcs_rx_clk); if (ret < 0) { - dev_err(dev, "can't enable epcs rx clk.\n"); + dev_err(dev, "can't enable epcs_rx_clk.\n"); goto disable_epcs_tx_clk; } ret = clk_prepare_enable(imxpriv->phy_apbclk); if (ret < 0) { - dev_err(dev, "can't enable phy pclk1.\n"); + dev_err(dev, "can't enable phy_apbclk.\n"); goto disable_epcs_rx_clk; } + ret = clk_prepare_enable(imxpriv->per_clk0); + if (ret < 0) { + dev_err(dev, "can't enable per_clk.\n"); + goto disable_phy_apbclk; + } + ret = clk_prepare_enable(imxpriv->per_clk1); + if (ret < 0) { + dev_err(dev, "can't enable per_clk.\n"); + goto disable_per_clk0; + } + ret = clk_prepare_enable(imxpriv->per_clk2); + if (ret < 0) { + dev_err(dev, "can't enable per_clk.\n"); + goto disable_per_clk1; + } + ret = clk_prepare_enable(imxpriv->per_clk3); + if (ret < 0) { + dev_err(dev, "can't enable per_clk.\n"); + goto disable_per_clk2; + } + ret = clk_prepare_enable(imxpriv->per_clk4); + if (ret < 0) { + dev_err(dev, "can't enable per_clk.\n"); + goto disable_per_clk3; + } + ret = clk_prepare_enable(imxpriv->per_clk5); + if (ret < 0) + dev_err(dev, "can't enable per_clk.\n"); + else + return 0; + + clk_disable_unprepare(imxpriv->per_clk4); +disable_per_clk3: + clk_disable_unprepare(imxpriv->per_clk3); +disable_per_clk2: + clk_disable_unprepare(imxpriv->per_clk2); +disable_per_clk1: + clk_disable_unprepare(imxpriv->per_clk1); +disable_per_clk0: + clk_disable_unprepare(imxpriv->per_clk0); +disable_phy_apbclk: + clk_disable_unprepare(imxpriv->phy_apbclk); +disable_epcs_rx_clk: + clk_disable_unprepare(imxpriv->epcs_rx_clk); +disable_epcs_tx_clk: + clk_disable_unprepare(imxpriv->epcs_tx_clk); +disable_phy_pclk1: + clk_disable_unprepare(imxpriv->phy_pclk1); +disable_phy_pclk0: + clk_disable_unprepare(imxpriv->phy_pclk0); + return ret; +} + +static void imx8_sata_clk_disable(struct imx_ahci_priv *imxpriv) +{ + clk_disable_unprepare(imxpriv->epcs_rx_clk); + clk_disable_unprepare(imxpriv->epcs_tx_clk); + clk_disable_unprepare(imxpriv->per_clk5); + clk_disable_unprepare(imxpriv->per_clk4); + clk_disable_unprepare(imxpriv->per_clk3); + clk_disable_unprepare(imxpriv->per_clk2); + clk_disable_unprepare(imxpriv->per_clk1); + clk_disable_unprepare(imxpriv->per_clk0); +} + +static int imx8_sata_enable(struct ahci_host_priv *hpriv) +{ + u32 val, reg; + int i, ret; + struct imx_ahci_priv *imxpriv = hpriv->plat_data; + struct device *dev = &imxpriv->ahci_pdev->dev; + + ret = imx8_sata_clk_enable(imxpriv); + if (ret) + return ret; /* Configure PHYx2 PIPE_RSTN */ regmap_read(imxpriv->gpr, IMX8QM_CSR_PCIEA_OFFSET + IMX8QM_CSR_PCIE_CTRL2_OFFSET, &val); @@ -744,14 +823,9 @@ static int imx8_sata_enable(struct ahci_host_priv *hpriv) err_out: clk_disable_unprepare(imxpriv->phy_apbclk); -disable_epcs_rx_clk: - clk_disable_unprepare(imxpriv->epcs_rx_clk); -disable_epcs_tx_clk: - clk_disable_unprepare(imxpriv->epcs_tx_clk); -disable_phy_pclk1: clk_disable_unprepare(imxpriv->phy_pclk1); -disable_phy_pclk0: clk_disable_unprepare(imxpriv->phy_pclk0); + imx8_sata_clk_disable(imxpriv); return ret; } @@ -851,8 +925,7 @@ static void imx_sata_disable(struct ahci_host_priv *hpriv) } if (imxpriv->type == AHCI_IMX8QM) { - clk_disable_unprepare(imxpriv->epcs_rx_clk); - clk_disable_unprepare(imxpriv->epcs_tx_clk); + imx8_sata_clk_disable(imxpriv); } clk_disable_unprepare(imxpriv->sata_ref_clk); @@ -1160,6 +1233,36 @@ static int imx8_sata_probe(struct device *dev, struct imx_ahci_priv *imxpriv) return PTR_ERR(imxpriv->phy_apbclk); } + imxpriv->per_clk0 = devm_clk_get(dev, "per_clk0"); + if (IS_ERR(imxpriv->per_clk0)) { + dev_err(dev, "can't get per_clk0 clock.\n"); + return PTR_ERR(imxpriv->per_clk0); + } + imxpriv->per_clk1 = devm_clk_get(dev, "per_clk1"); + if (IS_ERR(imxpriv->per_clk1)) { + dev_err(dev, "can't get per_clk1 clock.\n"); + return PTR_ERR(imxpriv->per_clk1); + } + imxpriv->per_clk2 = devm_clk_get(dev, "per_clk2"); + if (IS_ERR(imxpriv->per_clk2)) { + dev_err(dev, "can't get per_clk2 clock.\n"); + return PTR_ERR(imxpriv->per_clk2); + } + imxpriv->per_clk3 = devm_clk_get(dev, "per_clk3"); + if (IS_ERR(imxpriv->per_clk3)) { + dev_err(dev, "can't get per_clk3 clock.\n"); + return PTR_ERR(imxpriv->per_clk3); + } + imxpriv->per_clk4 = devm_clk_get(dev, "per_clk4"); + if (IS_ERR(imxpriv->per_clk4)) { + dev_err(dev, "can't get per_clk4 clock.\n"); + return PTR_ERR(imxpriv->per_clk4); + } + imxpriv->per_clk5 = devm_clk_get(dev, "per_clk5"); + if (IS_ERR(imxpriv->per_clk5)) { + dev_err(dev, "can't get per_clk5 clock.\n"); + return PTR_ERR(imxpriv->per_clk5); + } /* Fetch GPIO, then enable the external OSC */ imxpriv->clkreq_gpio = of_get_named_gpio(np, "clkreq-gpio", 0); if (gpio_is_valid(imxpriv->clkreq_gpio)) { -- cgit v1.2.3 From 73a14019d0d4ccf3d0acbd20e8a6f980ceb7035b Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Fri, 17 Jan 2020 15:19:56 +0800 Subject: MLK-23233-4 arm64: dts: refine pcie dts and add the pcieax2 and pciebx1 usecase Different usecase maybe used by customer, add the PCIEA two lanes and PCIEB one lane usecase into fsl-imx8qm-pcieax2pciebx1.dts. Refine the PCIE dts nodes, add the requrired HSIO peripheral clocks for different consumers. PCIEB has one more PER clock, since the PCIEA CSR register would be configuired when PCIEB is initialized. Signed-off-by: Richard Zhu --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/fsl-imx8qm-device.dtsi | 15 ++++-- .../dts/freescale/fsl-imx8qm-pcieax2pciebx1.dts | 57 ++++++++++++++++++++++ 3 files changed, 69 insertions(+), 4 deletions(-) create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8qm-pcieax2pciebx1.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 66918738ce76..c205e89bcab6 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -40,6 +40,7 @@ dtb-$(CONFIG_ARCH_FSL_IMX8QM) += fsl-imx8qm-lpddr4-arm2.dtb \ fsl-imx8qm-mek-domu-dpu1-hdmi.dtb \ fsl-imx8qm-mek-root.dtb \ fsl-imx8qm-mek-inmate.dtb \ + fsl-imx8qm-pcieax2pciebx1.dtb \ fsl-imx8qm-lpddr4-arm2-dp.dtb \ fsl-imx8qm-lpddr4-arm2-hdmi.dtb \ fsl-imx8qm-lpddr4-arm2-hdmi-in.dtb \ diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi index b7733b1c3e19..952954294f95 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi @@ -4110,8 +4110,11 @@ <&clk IMX8QM_HSIO_PCIE_A_SLV_AXI_CLK>, <&clk IMX8QM_HSIO_PHY_X2_PCLK_0>, <&clk IMX8QM_HSIO_PCIE_X2_PER_CLK>, - <&clk IMX8QM_HSIO_PCIE_A_DBI_AXI_CLK>; - clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", "pcie_inbound_axi"; + <&clk IMX8QM_HSIO_PCIE_A_DBI_AXI_CLK>, + <&clk IMX8QM_HSIO_PHY_X2_PER_CLK>, + <&clk IMX8QM_HSIO_MISC_PER_CLK>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", + "pcie_inbound_axi", "phy_per", "misc_per"; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &gic 0 73 4>, @@ -4153,8 +4156,12 @@ <&clk IMX8QM_HSIO_PCIE_B_SLV_AXI_CLK>, <&clk IMX8QM_HSIO_PHY_X2_PCLK_1>, <&clk IMX8QM_HSIO_PCIE_X1_PER_CLK>, - <&clk IMX8QM_HSIO_PCIE_B_DBI_AXI_CLK>; - clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", "pcie_inbound_axi"; + <&clk IMX8QM_HSIO_PCIE_X2_PER_CLK>, + <&clk IMX8QM_HSIO_PCIE_B_DBI_AXI_CLK>, + <&clk IMX8QM_HSIO_PHY_X2_PER_CLK>, + <&clk IMX8QM_HSIO_MISC_PER_CLK>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", "pciex2_per", + "pcie_inbound_axi", "phy_per", "misc_per"; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &gic 0 105 4>, diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-pcieax2pciebx1.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-pcieax2pciebx1.dts new file mode 100644 index 000000000000..6bac94c0b44c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-pcieax2pciebx1.dts @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020 NXP + */ + + +#include "fsl-imx8qm-mek.dts" + +/* + * Add the PCIeA x2 lanes and PCIeB x1 lane usecase + * hsio-cfg = + * NOTE: In this case, the HSIO nodes contained + * hsio-cfg = would be re-configured. + */ +&pciea{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pciea>; + disable-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; + clkreq-gpio = <&gpio4 27 GPIO_ACTIVE_LOW>; + epdev_on-supply = <&epdev_on>; + num-lanes = <2>; + clocks = <&clk IMX8QM_HSIO_PCIE_A_MSTR_AXI_CLK>, + <&clk IMX8QM_HSIO_PCIE_A_SLV_AXI_CLK>, + <&clk IMX8QM_HSIO_PHY_X2_PCLK_0>, + <&clk IMX8QM_HSIO_PCIE_X2_PER_CLK>, + <&clk IMX8QM_HSIO_PCIE_A_DBI_AXI_CLK>, + <&clk IMX8QM_HSIO_PHY_X2_PER_CLK>, + <&clk IMX8QM_HSIO_MISC_PER_CLK>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", + "pcie_inbound_axi", "phy_per", "misc_per"; + hsio-cfg = ; + status = "okay"; +}; + +&pcieb{ + ext_osc = <1>; + clocks = <&clk IMX8QM_HSIO_PCIE_B_MSTR_AXI_CLK>, + <&clk IMX8QM_HSIO_PCIE_B_SLV_AXI_CLK>, + <&clk IMX8QM_HSIO_PHY_X1_PCLK>, + <&clk IMX8QM_HSIO_PCIE_X1_PER_CLK>, + <&clk IMX8QM_HSIO_PCIE_X2_PER_CLK>, + <&clk IMX8QM_HSIO_PCIE_B_DBI_AXI_CLK>, + <&clk IMX8QM_HSIO_PHY_X1_PER_CLK>, + <&clk IMX8QM_HSIO_MISC_PER_CLK>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", "pciex2_per", + "pcie_inbound_axi", "phy_per", "misc_per"; + power-domains = <&pd_pcie1>; + hsio-cfg = ; + status = "okay"; +}; + +&sata { + status = "disabled"; +}; + -- cgit v1.2.3 From 359d8f37b464afea3718796fdd6eb27b0d2df8b1 Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Thu, 19 Dec 2019 09:47:14 +0800 Subject: MLK-23233-5 PCI: imx: add the mandatory required peripheral clocks To avoid potential dump when access the HSIO CRR registers during PCIE initialization. Add the PHY_PER and MISC clocks for both PCI controllers. PCIEB has one more PER clock, since the PCIEA CSR register would be configuired when PCIEB is initialized. Enable the clocks before CRR registers manipulations. Signed-off-by: Richard Zhu --- drivers/pci/dwc/pci-imx6.c | 174 +++++++++++++++++++++++++++++++-------------- 1 file changed, 119 insertions(+), 55 deletions(-) diff --git a/drivers/pci/dwc/pci-imx6.c b/drivers/pci/dwc/pci-imx6.c index 39047593ff8d..b9f7d639ec10 100644 --- a/drivers/pci/dwc/pci-imx6.c +++ b/drivers/pci/dwc/pci-imx6.c @@ -78,7 +78,10 @@ struct imx_pcie { struct clk *pcie_bus; struct clk *pcie_phy; struct clk *pcie_inbound_axi; + struct clk *pciex2_per; struct clk *pcie_per; + struct clk *phy_per; + struct clk *misc_per; struct clk *pcie; struct clk *pcie_ext_src; struct regmap *iomuxc_gpr; @@ -310,6 +313,10 @@ struct imx_pcie { #define IMX8MM_GPR_PCIE_POWER_OFF BIT(17) #define IMX8MM_GPR_PCIE_SSC_EN BIT(16) +static void pci_imx_clk_disable(struct device *dev); +static void pci_imx_clk_enable(struct imx_pcie *imx_pcie); +static void pci_imx_ltssm_disable(struct device *dev); + static int pcie_phy_poll_ack(struct imx_pcie *imx_pcie, int exp_val) { struct dw_pcie *pci = imx_pcie->pci; @@ -526,21 +533,23 @@ static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie) regmap_update_bits(imx_pcie->reg_src, 0x2c, BIT(2), BIT(2)); break; case IMX8QXP: - val = IMX8QM_CSR_PCIEB_OFFSET; - regmap_update_bits(imx_pcie->iomuxc_gpr, - val + IMX8QM_CSR_PCIE_CTRL2_OFFSET, - IMX8QM_CTRL_BUTTON_RST_N, - IMX8QM_CTRL_BUTTON_RST_N); - regmap_update_bits(imx_pcie->iomuxc_gpr, - val + IMX8QM_CSR_PCIE_CTRL2_OFFSET, - IMX8QM_CTRL_PERST_N, - IMX8QM_CTRL_PERST_N); - regmap_update_bits(imx_pcie->iomuxc_gpr, - val + IMX8QM_CSR_PCIE_CTRL2_OFFSET, - IMX8QM_CTRL_POWER_UP_RST_N, - IMX8QM_CTRL_POWER_UP_RST_N); + pci_imx_clk_enable(imx_pcie); + val = IMX8QM_CSR_PCIEB_OFFSET; + regmap_update_bits(imx_pcie->iomuxc_gpr, + val + IMX8QM_CSR_PCIE_CTRL2_OFFSET, + IMX8QM_CTRL_BUTTON_RST_N, + IMX8QM_CTRL_BUTTON_RST_N); + regmap_update_bits(imx_pcie->iomuxc_gpr, + val + IMX8QM_CSR_PCIE_CTRL2_OFFSET, + IMX8QM_CTRL_PERST_N, + IMX8QM_CTRL_PERST_N); + regmap_update_bits(imx_pcie->iomuxc_gpr, + val + IMX8QM_CSR_PCIE_CTRL2_OFFSET, + IMX8QM_CTRL_POWER_UP_RST_N, + IMX8QM_CTRL_POWER_UP_RST_N); break; case IMX8QM: + pci_imx_clk_enable(imx_pcie); for (i = 0; i <= imx_pcie->ctrl_id; i++) { val = IMX8QM_CSR_PCIEA_OFFSET + i * SZ_64K; regmap_update_bits(imx_pcie->iomuxc_gpr, @@ -637,26 +646,86 @@ static int imx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie) IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN); break; - case IMX8QXP: case IMX8QM: + case IMX8QXP: ret = clk_prepare_enable(imx_pcie->pcie_inbound_axi); if (ret) { dev_err(dev, "unable to enable pcie_axi clock\n"); - break; + return ret; } ret = clk_prepare_enable(imx_pcie->pcie_per); if (ret) { dev_err(dev, "unable to enable pcie_per clock\n"); - clk_disable_unprepare(imx_pcie->pcie_inbound_axi); - break; + goto err_pcie_per; } - + ret = clk_prepare_enable(imx_pcie->phy_per); + if (unlikely(ret)) { + dev_err(dev, "unable to enable phy per clock\n"); + goto err_phy_per; + } + ret = clk_prepare_enable(imx_pcie->misc_per); + if (unlikely(ret)) { + dev_err(dev, "unable to enable misc per clock\n"); + goto err_misc_per; + } + /* + * PCIA CSR would be touched during the initialization of the + * PCIEB of 8QM. + * Enable the PCIEA peripheral clock for this case here. + */ + if (imx_pcie->variant == IMX8QM && imx_pcie->ctrl_id == 1) { + ret = clk_prepare_enable(imx_pcie->pciex2_per); + if (unlikely(ret)) { + dev_err(dev, "can't enable pciex2 per clock\n"); + goto err_pciex2_per; + } + } + break; + default: break; } + return ret; +err_pciex2_per: + clk_disable_unprepare(imx_pcie->misc_per); +err_misc_per: + clk_disable_unprepare(imx_pcie->phy_per); +err_phy_per: + clk_disable_unprepare(imx_pcie->pcie_per); +err_pcie_per: + clk_disable_unprepare(imx_pcie->pcie_inbound_axi); return ret; } +static void pci_imx_clk_enable(struct imx_pcie *imx_pcie) +{ + int ret; + struct dw_pcie *pci = imx_pcie->pci; + struct device *dev = pci->dev; + + ret = clk_prepare_enable(imx_pcie->pcie_phy); + if (ret) + dev_err(dev, "unable to enable pcie_phy clock\n"); + + if (imx_pcie->ext_osc && (imx_pcie->variant == IMX6QP)) + clk_set_parent(imx_pcie->pcie_bus, + imx_pcie->pcie_ext_src); + ret = clk_prepare_enable(imx_pcie->pcie_bus); + if (ret) + dev_err(dev, "unable to enable pcie_bus clock\n"); + + ret = clk_prepare_enable(imx_pcie->pcie); + if (ret) + dev_err(dev, "unable to enable pcie clock\n"); + + ret = imx_pcie_enable_ref_clk(imx_pcie); + if (ret) + dev_err(dev, "unable to enable pcie ref clock\n"); + + /* allow the clocks to stabilize */ + udelay(200); +} + static int imx7d_pcie_wait_for_phy_pll_lock(struct imx_pcie *imx_pcie) { u32 val; @@ -764,36 +833,16 @@ static int imx_pcie_deassert_core_reset(struct imx_pcie *imx_pcie) } } - ret = clk_prepare_enable(imx_pcie->pcie); - if (ret) { - dev_err(dev, "unable to enable pcie clock\n"); - goto err_pcie; - } - - if (imx_pcie->ext_osc && (imx_pcie->variant == IMX6QP)) - clk_set_parent(imx_pcie->pcie_bus, - imx_pcie->pcie_ext_src); - ret = clk_prepare_enable(imx_pcie->pcie_bus); - if (ret) { - dev_err(dev, "unable to enable pcie_bus clock\n"); - goto err_pcie_bus; - } - - ret = clk_prepare_enable(imx_pcie->pcie_phy); - if (ret) { - dev_err(dev, "unable to enable pcie_phy clock\n"); - goto err_pcie_phy; - } - - ret = imx_pcie_enable_ref_clk(imx_pcie); - if (ret) { - dev_err(dev, "unable to enable pcie ref clock\n"); - goto err_ref_clk; + switch (imx_pcie->variant) { + case IMX8QXP: + case IMX8QM: + /* ClKs had been enabled */ + break; + default: + pci_imx_clk_enable(imx_pcie); + break; } - /* allow the clocks to stabilize */ - udelay(200); - switch (imx_pcie->variant) { case IMX6SX: regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5, @@ -964,13 +1013,7 @@ static int imx_pcie_deassert_core_reset(struct imx_pcie *imx_pcie) if (ret == 0) return ret; -err_ref_clk: - clk_disable_unprepare(imx_pcie->pcie_phy); -err_pcie_phy: - clk_disable_unprepare(imx_pcie->pcie_bus); -err_pcie_bus: - clk_disable_unprepare(imx_pcie->pcie); -err_pcie: + pci_imx_clk_disable(dev); if (imx_pcie->vpcie && regulator_is_enabled(imx_pcie->vpcie) > 0) { ret = regulator_disable(imx_pcie->vpcie); if (ret) @@ -1490,10 +1533,14 @@ static void pci_imx_clk_disable(struct device *dev) IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN, 0); break; - case IMX8QXP: case IMX8QM: + if (imx_pcie->ctrl_id == 1) + clk_disable_unprepare(imx_pcie->pciex2_per); + case IMX8QXP: clk_disable_unprepare(imx_pcie->pcie_per); clk_disable_unprepare(imx_pcie->pcie_inbound_axi); + clk_disable_unprepare(imx_pcie->phy_per); + clk_disable_unprepare(imx_pcie->misc_per); break; } } @@ -2074,6 +2121,7 @@ static int pci_imx_suspend_noirq(struct device *dev) IMX6Q_GPR1_PCIE_TEST_PD, IMX6Q_GPR1_PCIE_TEST_PD); } else { + pci_imx_ltssm_disable(dev); pci_imx_clk_disable(dev); imx_pcie_phy_pwr_dn(imx_pcie); @@ -2142,7 +2190,6 @@ static int pci_imx_resume_noirq(struct device *dev) regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD, 0); } else { - pci_imx_ltssm_disable(dev); imx_pcie_assert_core_reset(imx_pcie); imx_pcie_init_phy(imx_pcie); ret = imx_pcie_deassert_core_reset(imx_pcie); @@ -2507,6 +2554,23 @@ static int imx_pcie_probe(struct platform_device *pdev) dev_err(dev, "pcie_per clock source missing or invalid\n"); return PTR_ERR(imx_pcie->pcie_per); } + imx_pcie->phy_per = devm_clk_get(dev, "phy_per"); + if (IS_ERR(imx_pcie->phy_per)) { + dev_err(dev, "failed to get per clock.\n"); + return PTR_ERR(imx_pcie->phy_per); + } + imx_pcie->misc_per = devm_clk_get(dev, "misc_per"); + if (IS_ERR(imx_pcie->misc_per)) { + dev_err(dev, "failed to get per clock.\n"); + return PTR_ERR(imx_pcie->misc_per); + } + if (imx_pcie->variant == IMX8QM && imx_pcie->ctrl_id == 1) { + imx_pcie->pciex2_per = devm_clk_get(dev, "pciex2_per"); + if (IS_ERR(imx_pcie->pciex2_per)) { + dev_err(dev, "can't get pciex2_per.\n"); + return PTR_ERR(imx_pcie->pciex2_per); + } + } imx_pcie->iomuxc_gpr = syscon_regmap_lookup_by_phandle(node, "hsio"); -- cgit v1.2.3 From fc7c45cf829d1ed562f04cc219b5a79419ffa0c1 Mon Sep 17 00:00:00 2001 From: Iuliana Prodan Date: Wed, 4 Mar 2020 16:06:26 +0200 Subject: MLK-23396: crypto: caam - ensure CAAM context is not sharing the cacheline MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In caam_hash_state struct, caam_ctx buffer needs to have a separate cacheline, not sharing it with "update" callback. On imx8, the cacheline size is 64 and the MAX_CTX_LEN, from caam_ctx buffer, is (8 + 64). Therefore, add a ____cacheline_aligned to the update callback, in caam_hash_state struct, to ensure that caam_ctx buffer is not sharing the cacheline. Signed-off-by: Iuliana Prodan Reviewed-by: Horia Geantă --- drivers/crypto/caam/caamhash.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/crypto/caam/caamhash.c b/drivers/crypto/caam/caamhash.c index 961d848ebc6c..6051f7dc79e6 100644 --- a/drivers/crypto/caam/caamhash.c +++ b/drivers/crypto/caam/caamhash.c @@ -119,7 +119,7 @@ struct caam_hash_state { u8 buf_1[CAAM_MAX_HASH_BLOCK_SIZE] ____cacheline_aligned; int buflen_1; u8 caam_ctx[MAX_CTX_LEN] ____cacheline_aligned; - int (*update)(struct ahash_request *req); + int (*update)(struct ahash_request *req) ____cacheline_aligned; int (*final)(struct ahash_request *req); int (*finup)(struct ahash_request *req); int current_buf; -- cgit v1.2.3 From 82a6695ed109efa89307b4b0b5a53ba12f792b29 Mon Sep 17 00:00:00 2001 From: Ming Qian Date: Tue, 24 Mar 2020 10:18:58 +0800 Subject: MLK-23220:mxc:vpu_malone:kfifo_alloc failure in VPU driver when memory fragment Suggest to use vmalloc for fifo entity. Then use kfifo_init to init the fifo structure. Then we do not have to require contiguous memory from buddy, especially in a high pressure of memory resource. Signed-off-by: Ming Qian (cherry picked from commit 0cd3c661b95ecb273da5ee76fe7353ab7abd38c9) --- drivers/mxc/vpu_malone/vpu_b0.c | 53 ++++++++++++++++++++++++++++++----------- drivers/mxc/vpu_malone/vpu_b0.h | 4 ++++ 2 files changed, 43 insertions(+), 14 deletions(-) diff --git a/drivers/mxc/vpu_malone/vpu_b0.c b/drivers/mxc/vpu_malone/vpu_b0.c index 6757f7251ec0..6482a05fca24 100644 --- a/drivers/mxc/vpu_malone/vpu_b0.c +++ b/drivers/mxc/vpu_malone/vpu_b0.c @@ -40,7 +40,7 @@ #include #include #include -#include +#include #include "vpu_b0.h" #include "insert_startcode.h" @@ -5650,8 +5650,7 @@ static int create_instance_file(struct vpu_ctx *ctx) create_instance_buffer_file(ctx); create_instance_flow_file(ctx); create_instance_perf_file(ctx); - atomic64_set(&ctx->statistic.total_dma_size, 0); - atomic64_set(&ctx->statistic.total_alloc_size, 0); + return 0; } @@ -5816,13 +5815,22 @@ static int v4l2_open(struct file *filp) mutex_init(&ctx->instance_mutex); mutex_init(&ctx->cmd_lock); mutex_init(&ctx->perf_lock); - if (kfifo_alloc(&ctx->msg_fifo, - sizeof(struct event_msg) * VID_API_MESSAGE_LIMIT, - GFP_KERNEL)) { + atomic64_set(&ctx->statistic.total_dma_size, 0); + atomic64_set(&ctx->statistic.total_alloc_size, 0); + + ctx->msg_buffer_size = sizeof(struct event_msg) * VID_API_MESSAGE_LIMIT; + ctx->msg_buffer = vzalloc(ctx->msg_buffer_size); + if (!ctx->msg_buffer) { vpu_err("fail to alloc fifo when open\n"); ret = -ENOMEM; goto err_alloc_fifo; } + atomic64_add(ctx->msg_buffer_size, &ctx->statistic.total_alloc_size); + if (kfifo_init(&ctx->msg_fifo, ctx->msg_buffer, ctx->msg_buffer_size)) { + vpu_err("fail to init fifo when open\n"); + ret = -EINVAL; + goto err_init_kfifo; + } ctx->dev = dev; ctx->str_index = idx; dev->ctx[idx] = ctx; @@ -5906,8 +5914,12 @@ err_open_crc: ctx->tsm = NULL; err_create_tsm: remove_instance_file(ctx); - kfifo_free(&ctx->msg_fifo); dev->ctx[idx] = NULL; +err_init_kfifo: + vfree(ctx->msg_buffer); + atomic64_sub(ctx->msg_buffer_size, &ctx->statistic.total_alloc_size); + ctx->msg_buffer = NULL; + ctx->msg_buffer_size = 0; err_alloc_fifo: mutex_destroy(&ctx->instance_mutex); mutex_destroy(&ctx->cmd_lock); @@ -5983,7 +5995,10 @@ static int v4l2_release(struct file *filp) mutex_lock(&ctx->dev->dev_mutex); ctx->ctx_released = true; cancel_work_sync(&ctx->instance_work); - kfifo_free(&ctx->msg_fifo); + vfree(ctx->msg_buffer); + atomic64_sub(ctx->msg_buffer_size, &ctx->statistic.total_alloc_size); + ctx->msg_buffer = NULL; + ctx->msg_buffer_size = 0; if (ctx->instance_wq) destroy_workqueue(ctx->instance_wq); mutex_unlock(&ctx->dev->dev_mutex); @@ -6331,13 +6346,19 @@ static int vpu_probe(struct platform_device *pdev) if (ret) goto err_rm_vdev; - ret = kfifo_alloc(&dev->mu_msg_fifo, - sizeof(u_int32) * VPU_MAX_NUM_STREAMS * VID_API_MESSAGE_LIMIT, - GFP_KERNEL); - if (ret) { + dev->mu_msg_buffer_size = + sizeof(u_int32) * VPU_MAX_NUM_STREAMS * VID_API_MESSAGE_LIMIT; + dev->mu_msg_buffer = vzalloc(dev->mu_msg_buffer_size); + if (!dev->mu_msg_buffer) { vpu_err("error: fail to alloc mu msg fifo\n"); goto err_rm_vdev; } + ret = kfifo_init(&dev->mu_msg_fifo, + dev->mu_msg_buffer, dev->mu_msg_buffer_size); + if (ret) { + vpu_err("error: fail to init mu msg fifo\n"); + goto err_free_fifo; + } dev->workqueue = alloc_workqueue("vpu", WQ_UNBOUND | WQ_MEM_RECLAIM, 1); if (!dev->workqueue) { @@ -6369,7 +6390,9 @@ err_poweroff: pm_runtime_put_sync(&pdev->dev); pm_runtime_disable(&pdev->dev); err_free_fifo: - kfifo_free(&dev->mu_msg_fifo); + vfree(dev->mu_msg_buffer); + dev->mu_msg_buffer = NULL; + dev->mu_msg_buffer_size = 0; err_rm_vdev: if (dev->pvpu_decoder_dev) { video_unregister_device(dev->pvpu_decoder_dev); @@ -6406,7 +6429,9 @@ static int vpu_remove(struct platform_device *pdev) dev->debugfs_root = NULL; dev->debugfs_dbglog = NULL; dev->debugfs_fwlog = NULL; - kfifo_free(&dev->mu_msg_fifo); + vfree(dev->mu_msg_buffer); + dev->mu_msg_buffer = NULL; + dev->mu_msg_buffer_size = 0; destroy_workqueue(dev->workqueue); if (dev->m0_p_fw_space_vir) iounmap(dev->m0_p_fw_space_vir); diff --git a/drivers/mxc/vpu_malone/vpu_b0.h b/drivers/mxc/vpu_malone/vpu_b0.h index e1e0949e5237..3756a9ea7765 100644 --- a/drivers/mxc/vpu_malone/vpu_b0.h +++ b/drivers/mxc/vpu_malone/vpu_b0.h @@ -314,6 +314,8 @@ struct vpu_dev { char precheck_content[1024]; struct kfifo mu_msg_fifo; + void *mu_msg_buffer; + unsigned int mu_msg_buffer_size; u_int32 vpu_irq; /* reserve for kernel version 5.4 or later */ @@ -399,6 +401,8 @@ struct vpu_ctx { int str_index; struct queue_data q_data[2]; struct kfifo msg_fifo; + void *msg_buffer; + unsigned int msg_buffer_size; struct mutex instance_mutex; struct work_struct instance_work; struct workqueue_struct *instance_wq; -- cgit v1.2.3 From c2937fd8fe144519d6461d396ed6e9066749ba21 Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Thu, 26 Mar 2020 14:13:43 +0800 Subject: MLK-23681 arm64: dts: imx: enable pcieb on 8qm mek baseboard Based on imx_4.1x kernel, enable the PCIEB on i.MX8QM MEK baseboard. Regarding to the base board HW limitation(two Disable#) are not connected. Only the standard PCIe EP device is supported on PCIEB port. Signed-off-by: Richard Zhu (cherry picked from commit d0331d84e5a14d6e2520d04540d1e893d75bd678) --- arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dtsi index 4c2c29695644..8634b5d1f30a 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dtsi @@ -466,6 +466,14 @@ >; }; + pinctrl_pcieb: pciebgrp { + fsl,pins = < + SC_P_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 0x06000021 + SC_P_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 0x04000021 + SC_P_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 0x06000021 + >; + }; + pinctrl_sim0: sim0grp { fsl,pins = < SC_P_SIM0_CLK_DMA_SIM0_CLK 0xc0000021 @@ -1138,6 +1146,15 @@ status = "okay"; }; +&pcieb { + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + reset-gpio = <&gpio5 0 GPIO_ACTIVE_LOW>; + clkreq-gpio = <&gpio4 30 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + &intmux_cm40 { status = "okay"; }; -- cgit v1.2.3 From 651364b5fe44c83cb8f89c4d9f8f89359fb787c5 Mon Sep 17 00:00:00 2001 From: Rosioru Dragos Date: Tue, 18 Feb 2020 17:56:39 +0200 Subject: LF-717: crypto: dcp - fix scatterlist linearization for hash MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The incorrect traversal of the scatterlist, during the linearization phase lead to computing the hash value of the wrong input buffer. New implementation uses scatterwalk_map_and_copy() to address this issue. Fixes: 15b59e7c3733 ("crypto: mxs - Add Freescale MXS DCP driver") Signed-off-by: Rosioru Dragos Acked-by: Horia Geantă Signed-off-by: Leonard Crestez --- drivers/crypto/mxs-dcp.c | 58 +++++++++++++++++++++++------------------------- 1 file changed, 28 insertions(+), 30 deletions(-) diff --git a/drivers/crypto/mxs-dcp.c b/drivers/crypto/mxs-dcp.c index 4915b9187477..37e842683004 100644 --- a/drivers/crypto/mxs-dcp.c +++ b/drivers/crypto/mxs-dcp.c @@ -26,6 +26,7 @@ #include #include #include +#include #define DCP_MAX_CHANS 4 #define DCP_BUF_SZ PAGE_SIZE @@ -639,49 +640,46 @@ static int dcp_sha_req_to_buf(struct crypto_async_request *arq) struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm); struct dcp_sha_req_ctx *rctx = ahash_request_ctx(req); struct hash_alg_common *halg = crypto_hash_alg_common(tfm); - const int nents = sg_nents(req->src); uint8_t *in_buf = sdcp->coh->sha_in_buf; uint8_t *out_buf = sdcp->coh->sha_out_buf; - uint8_t *src_buf; - struct scatterlist *src; - unsigned int i, len, clen; + unsigned int i, len, clen, oft = 0; int ret; int fin = rctx->fini; if (fin) rctx->fini = 0; - for_each_sg(req->src, src, nents, i) { - src_buf = sg_virt(src); - len = sg_dma_len(src); - - do { - if (actx->fill + len > DCP_BUF_SZ) - clen = DCP_BUF_SZ - actx->fill; - else - clen = len; - - memcpy(in_buf + actx->fill, src_buf, clen); - len -= clen; - src_buf += clen; - actx->fill += clen; + src = req->src; + len = req->nbytes; - /* - * If we filled the buffer and still have some - * more data, submit the buffer. - */ - if (len && actx->fill == DCP_BUF_SZ) { - ret = mxs_dcp_run_sha(req); - if (ret) - return ret; - actx->fill = 0; - rctx->init = 0; - } - } while (len); + while (len) { + if (actx->fill + len > DCP_BUF_SZ) + clen = DCP_BUF_SZ - actx->fill; + else + clen = len; + + scatterwalk_map_and_copy(in_buf + actx->fill, src, oft, clen, + 0); + + len -= clen; + oft += clen; + actx->fill += clen; + + /* + * If we filled the buffer and still have some + * more data, submit the buffer. + */ + if (len && actx->fill == DCP_BUF_SZ) { + ret = mxs_dcp_run_sha(req); + if (ret) + return ret; + actx->fill = 0; + rctx->init = 0; + } } if (fin) { -- cgit v1.2.3 From 02e96760b8fbeffcab1769f9a9a45da661409cc2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Horia=20Geant=C4=83?= Date: Mon, 23 Mar 2020 11:37:11 +0200 Subject: MLK-21644 crypto: tcrypt - workaround for overlapping src, dst AAD MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is a temporary workround for the case when: -SWIOTLB is used for DMA bounce buffering AND -data to be DMA-ed is mapped DMA_FROM_DEVICE and device only partially overwrites the "original" data AND -it's expected that the "original" data that was not overwritten by the device to be untouched As discussed in upstream, the proper fix should be: -either an extension of the DMA API OR -a workaround in the device driver (considering these cases are rarely met in practice) Since both alternatives are not trivial (to say the least), add a workaround for the few cases matching the error conditions listed above. Link: https://lore.kernel.org/lkml/VI1PR0402MB348537CB86926B3E6D1DBE0A98070@VI1PR0402MB3485.eurprd04.prod.outlook.com/ Link: https://lore.kernel.org/lkml/20190522072018.10660-1-horia.geanta@nxp.com/ Signed-off-by: Horia Geantă Reviewed-by: Valentin Ciocoi Radulescu Reviewed-by: Iuliana Prodan --- crypto/tcrypt.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/crypto/tcrypt.c b/crypto/tcrypt.c index 54952bd885c4..8bbc5de37ca4 100644 --- a/crypto/tcrypt.c +++ b/crypto/tcrypt.c @@ -224,7 +224,7 @@ static void test_aead_speed(const char *algo, int enc, unsigned int secs, struct scatterlist *sg; struct scatterlist *sgout; const char *e; - void *assoc; + void *assoc, *assoc_out; char *iv; char *xbuf[XBUFSIZE]; char *xoutbuf[XBUFSIZE]; @@ -287,6 +287,8 @@ static void test_aead_speed(const char *algo, int enc, unsigned int secs, do { assoc = axbuf[0]; memset(assoc, 0xff, aad_size); + assoc_out = axbuf[1]; + memset(assoc_out, 0xff, aad_size); if ((*keysize + *b_size) > TVMEMSIZE * PAGE_SIZE) { pr_err("template (%u) too big for tvmem (%lu)\n", @@ -326,7 +328,7 @@ static void test_aead_speed(const char *algo, int enc, unsigned int secs, assoc, aad_size); sg_init_aead(sgout, xoutbuf, - *b_size + (enc ? authsize : 0), assoc, + *b_size + (enc ? authsize : 0), assoc_out, aad_size); aead_request_set_ad(req, aad_size); @@ -348,6 +350,9 @@ static void test_aead_speed(const char *algo, int enc, unsigned int secs, ret); break; } + + memset(assoc, 0xff, aad_size); + memset(assoc_out, 0xff, aad_size); } aead_request_set_crypt(req, sg, sgout, -- cgit v1.2.3 From 252217e0dc992ffed64f76fabf79cedae95e09f5 Mon Sep 17 00:00:00 2001 From: Shijie Qin Date: Sat, 18 Apr 2020 09:55:53 +0800 Subject: LF-1236 mxc: vpu_malone: roundup allocated kfifo size to power-of-two kfifo memory size must roundup to power-of-two if it is allocated by driver. Because kfifo elements size will roundup to power-of-two in kfifo_init(), must guarantee allocated memory is enough. Signed-off-by: Shijie Qin Reviewed-by: ming_qian (cherry picked from commit c900bb4cd98efc43dddfb18d96c8af358e804481) --- drivers/mxc/vpu_malone/vpu_b0.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/mxc/vpu_malone/vpu_b0.c b/drivers/mxc/vpu_malone/vpu_b0.c index 6482a05fca24..7ee3e8a5f570 100644 --- a/drivers/mxc/vpu_malone/vpu_b0.c +++ b/drivers/mxc/vpu_malone/vpu_b0.c @@ -5819,6 +5819,8 @@ static int v4l2_open(struct file *filp) atomic64_set(&ctx->statistic.total_alloc_size, 0); ctx->msg_buffer_size = sizeof(struct event_msg) * VID_API_MESSAGE_LIMIT; + if (!is_power_of_2(ctx->msg_buffer_size)) + ctx->msg_buffer_size = roundup_pow_of_two(ctx->msg_buffer_size); ctx->msg_buffer = vzalloc(ctx->msg_buffer_size); if (!ctx->msg_buffer) { vpu_err("fail to alloc fifo when open\n"); @@ -6348,6 +6350,8 @@ static int vpu_probe(struct platform_device *pdev) dev->mu_msg_buffer_size = sizeof(u_int32) * VPU_MAX_NUM_STREAMS * VID_API_MESSAGE_LIMIT; + if (!is_power_of_2(dev->mu_msg_buffer_size)) + dev->mu_msg_buffer_size = roundup_pow_of_two(dev->mu_msg_buffer_size); dev->mu_msg_buffer = vzalloc(dev->mu_msg_buffer_size); if (!dev->mu_msg_buffer) { vpu_err("error: fail to alloc mu msg fifo\n"); -- cgit v1.2.3 From 03cfd33c5f341370509952e7d8f06bd60fdc92b5 Mon Sep 17 00:00:00 2001 From: Richard Liu Date: Fri, 20 Mar 2020 15:42:01 +0000 Subject: MGS-5565 staging: android: ion: Flush cache after zero CMA allocated memory ION CMA memory default is cacheable, need flush cache after memset(), else cache and physical memory not sync may cause problem. Issue case: VPU Video playback or GPU render have dirty line issue. Root cause: ION CMA allocate cacheable buffer and do memset(), some data still in cache not in physical memory, VPU or GPU write the buffer with physical address, or user call ion_mmap() to map the buffer through pgprot_writecombine() as no-cache and write the buffer, later some CPU cache access trigger cache flush, previous memset() data go to physical memory as dirty data. Change-Id: I82b4cb61bbe6cffc687d452f9f81c1e35914d2f1 Signed-off-by: Richard Liu (cherry picked from commit 5d360f25f3523311b5f478b7b1c7bc9020cfda58) --- drivers/staging/android/ion/ion_cma_heap.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/staging/android/ion/ion_cma_heap.c b/drivers/staging/android/ion/ion_cma_heap.c index fa3e4b7e0c9f..80df813372e4 100644 --- a/drivers/staging/android/ion/ion_cma_heap.c +++ b/drivers/staging/android/ion/ion_cma_heap.c @@ -22,6 +22,7 @@ #include #include #include +#include #include "ion.h" @@ -60,12 +61,22 @@ static int ion_cma_allocate(struct ion_heap *heap, struct ion_buffer *buffer, void *vaddr = kmap_atomic(page); memset(vaddr, 0, PAGE_SIZE); +#ifdef CONFIG_ARM64 + __flush_dcache_area(vaddr,PAGE_SIZE); +#else + __cpuc_flush_dcache_area(vaddr,PAGE_SIZE); +#endif kunmap_atomic(vaddr); page++; nr_clear_pages--; } } else { memset(page_address(pages), 0, size); +#ifdef CONFIG_ARM64 + __flush_dcache_area(page_address(pages),size); +#else + __cpuc_flush_dcache_area(page_address(pages),size); +#endif } table = kmalloc(sizeof(*table), GFP_KERNEL); -- cgit v1.2.3 From 52635c5ba1ff8a4c7b4469e85db4f87c337a354b Mon Sep 17 00:00:00 2001 From: Richard Liu Date: Mon, 23 Mar 2020 17:08:08 +0000 Subject: MGS-5565-1 staging: android: ion: Flush outer cache after zero CMA allocated memory Need flush outer cache after zero CMA allocated memory on arm32 platform. Change-Id: Ieaa7c62bf65e4490f904d68bed1fa16fb7c5d8fa Signed-off-by: Richard Liu Reviewed-by: Bing Song (cherry picked from commit 9e51da339eb290f35eb79d9acc0ea147d8bdf0cf) --- drivers/staging/android/ion/ion_cma_heap.c | 26 +++++++++++++++++++------- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/drivers/staging/android/ion/ion_cma_heap.c b/drivers/staging/android/ion/ion_cma_heap.c index 80df813372e4..8589eff9b77f 100644 --- a/drivers/staging/android/ion/ion_cma_heap.c +++ b/drivers/staging/android/ion/ion_cma_heap.c @@ -23,6 +23,9 @@ #include #include #include +#ifdef CONFIG_ARM +#include +#endif #include "ion.h" @@ -56,26 +59,35 @@ static int ion_cma_allocate(struct ion_heap *heap, struct ion_buffer *buffer, if (PageHighMem(pages)) { unsigned long nr_clear_pages = nr_pages; struct page *page = pages; +#ifdef CONFIG_ARM + phys_addr_t base = __pfn_to_phys(page_to_pfn(pages)); + phys_addr_t end = base + size; +#endif while (nr_clear_pages > 0) { void *vaddr = kmap_atomic(page); memset(vaddr, 0, PAGE_SIZE); -#ifdef CONFIG_ARM64 - __flush_dcache_area(vaddr,PAGE_SIZE); -#else +#ifdef CONFIG_ARM __cpuc_flush_dcache_area(vaddr,PAGE_SIZE); +#else + __flush_dcache_area(vaddr,PAGE_SIZE); #endif kunmap_atomic(vaddr); page++; nr_clear_pages--; } +#ifdef CONFIG_ARM + outer_flush_range(base, end); +#endif } else { - memset(page_address(pages), 0, size); -#ifdef CONFIG_ARM64 - __flush_dcache_area(page_address(pages),size); + void *ptr = page_address(pages); + memset(ptr, 0, size); +#ifdef CONFIG_ARM + __cpuc_flush_dcache_area(ptr,size); + outer_flush_range(__pa(ptr), __pa(ptr) + size); #else - __cpuc_flush_dcache_area(page_address(pages),size); + __flush_dcache_area(ptr,size); #endif } -- cgit v1.2.3 From 96c179b63e7bbd755f7288cdc408921e0f16a425 Mon Sep 17 00:00:00 2001 From: Robin Gong Date: Tue, 11 Feb 2020 19:37:59 +0800 Subject: MLK-23275-1: ARM64: dts: freescale: fsl-imx8mm-evk: correct ldo1/ldo2 voltage Correct ldo1/ldo2 voltage as below: ldo1 --NVCC_SNVS_1V8 ldo2 --VDD_SNVS_0V8 Signed-off-by: Robin Gong Reviewed-by: Jacky Bai (cherry picked from commit 6e1db954c1261c9a8a40f7c4e33f03173c4d05b6) (cherry picked from commit 8574922dd583141a332be58fe1656ee05c9e5dd4) --- arch/arm64/boot/dts/freescale/fsl-imx8mm-evk.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk.dts index 5a522e6c05fc..30dd84f67da6 100755 --- a/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk.dts @@ -630,8 +630,8 @@ ldo1_reg: regulator@8 { reg = <8>; regulator-compatible = "ldo1"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1900000>; regulator-boot-on; regulator-always-on; }; @@ -639,7 +639,7 @@ ldo2_reg: regulator@9 { reg = <9>; regulator-compatible = "ldo2"; - regulator-min-microvolt = <900000>; + regulator-min-microvolt = <800000>; regulator-max-microvolt = <900000>; regulator-boot-on; regulator-always-on; -- cgit v1.2.3 From 167cbe000b2e884b9b5d936ce83ae775d4a4ad32 Mon Sep 17 00:00:00 2001 From: Robin Gong Date: Tue, 11 Feb 2020 19:41:05 +0800 Subject: MLK-23275-2: ARM64: dts: freescale: fsl-imx8mn-ddr4-evk: correct ldo1/ldo2 voltage Correct ldo1/ldo2 voltage as below: ldo1 --NVCC_SNVS_1V8 ldo2 --VDD_SNVS_0V8 Signed-off-by: Robin Gong Reviewed-by: Jacky Bai (cherry picked from commit d11796134f55d88b49d79bf25d6c42b677ff47bc) (cherry picked from commit 1c923bdd27021b011358f9422a6a18cbf30de491) --- arch/arm64/boot/dts/freescale/fsl-imx8mn-ddr4-evk.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mn-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mn-ddr4-evk.dts index c90b9ce20005..d8a516c71e22 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8mn-ddr4-evk.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mn-ddr4-evk.dts @@ -613,8 +613,8 @@ ldo1_reg: regulator@8 { reg = <8>; regulator-compatible = "ldo1"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1900000>; regulator-boot-on; regulator-always-on; }; @@ -622,7 +622,7 @@ ldo2_reg: regulator@9 { reg = <9>; regulator-compatible = "ldo2"; - regulator-min-microvolt = <900000>; + regulator-min-microvolt = <800000>; regulator-max-microvolt = <900000>; regulator-boot-on; regulator-always-on; -- cgit v1.2.3 From aa5d66d3571e82e401d6578993bbd315dbb680a3 Mon Sep 17 00:00:00 2001 From: Robin Gong Date: Thu, 23 Apr 2020 21:42:05 +0800 Subject: MLK-23275-3: regulator: bd71837: correct ldo1/ldo2 group Only one group voltage support on L4.14 so that the below two patches for dts are not enough since 1.8V/0.8V not support by pmic driver: commit 1c923bdd27021b011358f9422a6a18cbf30de491 ("MLK-23275-2: ARM64: dts: freescale: fsl-imx8mn-ddr4-evk: correct ldo1/ldo2 voltage") commit 8574922dd583141a332be58fe1656ee05c9e5dd4 ("MLK-23275-1: ARM64: dts: freescale: fsl-imx8mm-evk: correct ldo1/ldo2 voltage") So change ldo1/ldo2 voltage to 1.6V~1.9V/0.8V per i.mx8mm/i.mx8mn for quick fix. For the kernel from L4.19, no need this patch. Signed-off-by: Robin Gong Reviewed-by: Jacky Bai (cherry picked from commit 4166421be644aea1c7add0f786c859c4b81f6923) --- drivers/regulator/bd71837-regulator.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/regulator/bd71837-regulator.c b/drivers/regulator/bd71837-regulator.c index 0052f0212a27..73e6cf809d78 100644 --- a/drivers/regulator/bd71837-regulator.c +++ b/drivers/regulator/bd71837-regulator.c @@ -174,10 +174,10 @@ static const struct regulator_linear_range bd71837_buck8_voltage_ranges[] = { /* * LDO1 - * 3.0 to 3.3V (100mV step) + * 1.6 to 1.9V (100mV step) */ static const struct regulator_linear_range bd71837_ldo1_voltage_ranges[] = { - REGULATOR_LINEAR_RANGE(3000000, 0x00, 0x03, 100000), + REGULATOR_LINEAR_RANGE(1600000, 0x00, 0x03, 100000), }; /* @@ -350,7 +350,7 @@ static const struct regulator_desc bd71837_regulators[] = { .owner = THIS_MODULE, }, /* - * LDO2 0.9V + * LDO2 0.8V * Fixed voltage */ { @@ -359,7 +359,7 @@ static const struct regulator_desc bd71837_regulators[] = { .ops = &bd71837_fixed_regulator_ops, .type = REGULATOR_VOLTAGE, .n_voltages = BD71837_LDO2_VOLTAGE_NUM, - .min_uV = 900000, + .min_uV = 800000, .enable_reg = BD71837_REG_LDO2_VOLT, .enable_mask = LDO2_EN, .owner = THIS_MODULE, -- cgit v1.2.3 From 20a5e74485abe60c61f555e7ce8e561b8f3f176b Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Wed, 29 Apr 2020 22:36:55 +0800 Subject: MLK-23880 arm64: dts: imx8dx: refine the pcieb clocks - Refine the PCIe clocks for iMX8DX and iMX8QXP. - Correct the HSIO power domain name on iMX8QXP, otherwise, the peripheral clocks wouldn't be enabled. Signed-off-by: Richard Zhu Reviewed-by: Fugang Duan (cherry picked from commit a2c09691aeafc818c287f25d69e53b6411d4ef26) --- arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi index 5c377c2ce64d..72040461e67a 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi @@ -1108,7 +1108,7 @@ }; }; - pd_hsio: hsio-power-domain { + pd_hsio: PD_HSIO { compatible = "nxp,imx8-pd"; reg = ; #power-domain-cells = <0>; @@ -3442,8 +3442,11 @@ <&clk IMX8QXP_HSIO_PCIE_SLV_AXI_CLK>, <&clk IMX8QXP_HSIO_PHY_X1_PCLK>, <&clk IMX8QXP_HSIO_PCIE_X1_PER_CLK>, - <&clk IMX8QXP_HSIO_PCIE_DBI_AXI_CLK>; - clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", "pcie_inbound_axi"; + <&clk IMX8QXP_HSIO_PCIE_DBI_AXI_CLK>, + <&clk IMX8QXP_HSIO_PHY_X1_PER_CLK>, + <&clk IMX8QXP_HSIO_MISC_PER_CLK>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", + "pcie_inbound_axi", "phy_per", "misc_per"; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &gic 0 105 4>, -- cgit v1.2.3 From 0347fe7527d062e1762498cb5863bcd5bde0997b Mon Sep 17 00:00:00 2001 From: Zhang Peng Date: Wed, 29 Apr 2020 20:08:56 +0800 Subject: MLK-23837 Asoc: fsl_dsp: Fix system crash when do dsp suspend test The issue is GPU will crash when do dsp suspend test, and only meet this issue when load GPU as module. The reason is that dsp framework's global data set size little than actul size. So dsp will touch the memory that not owned dsp, then caused GPU crash. Signed-off-by: Zhang Peng (cherry picked from commit 1a17334e714037f8424e5f1df5cbcd06f6e79294) --- sound/soc/fsl/fsl_dsp.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/soc/fsl/fsl_dsp.h b/sound/soc/fsl/fsl_dsp.h index fb01a4985c48..c813d531a5bc 100644 --- a/sound/soc/fsl/fsl_dsp.h +++ b/sound/soc/fsl/fsl_dsp.h @@ -128,7 +128,7 @@ struct fsl_dsp { #define MSG_BUF_SIZE 8192 #define INPUT_BUF_SIZE 4096 #define OUTPUT_BUF_SIZE 16384 -#define DSP_CONFIG_SIZE 4096 +#define DSP_CONFIG_SIZE 8192 void *memcpy_dsp(void *dest, const void *src, size_t count); void *memset_dsp(void *dest, int c, size_t count); -- cgit v1.2.3