From dc7fee5c4476eafd8a3add48b90b56d44bd4fa24 Mon Sep 17 00:00:00 2001 From: Sandor Yu Date: Fri, 28 Aug 2015 18:04:46 +0800 Subject: MLK-11431-3: ARM: DTS: imx6 Add IPU and display support Add IPU, HDMI and LDB support. Signed-off-by: Sandor Yu --- arch/arm/boot/dts/imx6dl-sabresd.dts | 20 ++- arch/arm/boot/dts/imx6dl.dtsi | 26 ++-- arch/arm/boot/dts/imx6q-sabreauto.dts | 22 +++- arch/arm/boot/dts/imx6q-sabresd.dts | 28 ++++- arch/arm/boot/dts/imx6q.dtsi | 162 ++++--------------------- arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 160 +++++++++++++++++++++++- arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 201 ++++++++++++++++++++++++++++++- arch/arm/boot/dts/imx6qdl.dtsi | 181 ++++++++-------------------- arch/arm/boot/dts/imx6qp-sabreauto.dts | 16 +++ 9 files changed, 525 insertions(+), 291 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-sabresd.dts b/arch/arm/boot/dts/imx6dl-sabresd.dts index 1e45f2f9d0b6..2181a82a7d80 100644 --- a/arch/arm/boot/dts/imx6dl-sabresd.dts +++ b/arch/arm/boot/dts/imx6dl-sabresd.dts @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013 Freescale Semiconductor, Inc. + * Copyright (C) 2013-2015 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -15,3 +15,21 @@ model = "Freescale i.MX6 DualLite SABRE Smart Device Board"; compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl"; }; + +&ldb { + lvds-channel@0 { + crtc = "ipu1-di0"; + }; + + lvds-channel@1 { + crtc = "ipu1-di1"; + }; +}; + +&mxcfb1 { + status = "okay"; +}; + +&mxcfb2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index 32de59f99a54..a9f3d6314910 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi @@ -1,6 +1,6 @@ /* - * Copyright 2013 Freescale Semiconductor, Inc. + * Copyright 2013-2015 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -119,24 +119,22 @@ }; }; }; - - display-subsystem { - compatible = "fsl,imx-display-subsystem"; - ports = <&ipu1_di0>, <&ipu1_di1>; - }; -}; - -&hdmi { - compatible = "fsl,imx6dl-hdmi"; }; &ldb { - clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, + compatible = "fsl,imx6dl-ldb", "fsl,imx53-ldb"; + clocks = <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>, <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, - <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>; - clock-names = "di0_pll", "di1_pll", + <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI0_DIV_3_5>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_3_5>, + <&clks IMX6QDL_CLK_LDB_DI0_DIV_7>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_7>, + <&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>; + clock-names = "ldb_di0", "ldb_di1", "di0_sel", "di1_sel", - "di0", "di1"; + "di2_sel", + "ldb_di0_div_3_5", "ldb_di1_div_3_5", + "ldb_di0_div_7", "ldb_di1_div_7", + "ldb_di0_div_sel", "ldb_di1_div_sel"; }; &vpu { diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-sabreauto.dts index 334b9247e78c..a321a20832df 100644 --- a/arch/arm/boot/dts/imx6q-sabreauto.dts +++ b/arch/arm/boot/dts/imx6q-sabreauto.dts @@ -1,5 +1,5 @@ /* - * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2012-2015 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. * * The code contained herein is licensed under the GNU General Public @@ -20,6 +20,26 @@ compatible = "fsl,imx6q-sabreauto", "fsl,imx6q"; }; +&ldb { + lvds-channel@0 { + crtc = "ipu2-di0"; + }; + lvds-channel@1 { + crtc = "ipu2-di1"; + }; +}; +&mxcfb1 { + status = "okay"; +}; +&mxcfb2 { + status = "okay"; +}; +&mxcfb3 { + status = "okay"; +}; +&mxcfb4 { + status = "okay"; +}; &sata { status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts index 9cbdfe7a0931..6a0497acc2bc 100644 --- a/arch/arm/boot/dts/imx6q-sabresd.dts +++ b/arch/arm/boot/dts/imx6q-sabresd.dts @@ -1,5 +1,5 @@ /* - * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2012=2015 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. * * The code contained herein is licensed under the GNU General Public @@ -20,6 +20,32 @@ compatible = "fsl,imx6q-sabresd", "fsl,imx6q"; }; +&ldb { + lvds-channel@0 { + crtc = "ipu2-di0"; + }; + + lvds-channel@1 { + crtc = "ipu2-di1"; + }; +}; + +&mxcfb1 { + status = "okay"; +}; + +&mxcfb2 { + status = "okay"; +}; + +&mxcfb3 { + status = "okay"; +}; + +&mxcfb4 { + status = "okay"; +}; + &sata { status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 05685a5264f5..e7380729da52 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -1,6 +1,6 @@ /* - * Copyright 2013 Freescale Semiconductor, Inc. + * Copyright 2013-2015 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -176,156 +176,38 @@ interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, <0 7 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_IPU2>, - <&clks IMX6QDL_CLK_IPU2_DI0>, - <&clks IMX6QDL_CLK_IPU2_DI1>; - clock-names = "bus", "di0", "di1"; - resets = <&src 4>; - - ipu2_csi0: port@0 { - reg = <0>; - }; - - ipu2_csi1: port@1 { - reg = <1>; - }; - - ipu2_di0: port@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - ipu2_di0_disp0: endpoint@0 { - }; - - ipu2_di0_hdmi: endpoint@1 { - remote-endpoint = <&hdmi_mux_2>; - }; - - ipu2_di0_mipi: endpoint@2 { - }; - - ipu2_di0_lvds0: endpoint@3 { - remote-endpoint = <&lvds0_mux_2>; - }; - - ipu2_di0_lvds1: endpoint@4 { - remote-endpoint = <&lvds1_mux_2>; - }; - }; - - ipu2_di1: port@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; + <&clks IMX6QDL_CLK_IPU2_DI0>, <&clks IMX6QDL_CLK_IPU2_DI1>, + <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>, + <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>; + clock-names = "bus", + "di0", "di1", + "di0_sel", "di1_sel", + "ldb_di0", "ldb_di1"; - ipu2_di1_hdmi: endpoint@1 { - remote-endpoint = <&hdmi_mux_3>; - }; - - ipu2_di1_mipi: endpoint@2 { - }; - - ipu2_di1_lvds0: endpoint@3 { - remote-endpoint = <&lvds0_mux_3>; - }; + resets = <&src 4>; + bypass_reset = <0>; - ipu2_di1_lvds1: endpoint@4 { - remote-endpoint = <&lvds1_mux_3>; - }; }; }; }; - display-subsystem { - compatible = "fsl,imx-display-subsystem"; - ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>; - }; -}; - -&hdmi { - compatible = "fsl,imx6q-hdmi"; - - port@2 { - reg = <2>; - - hdmi_mux_2: endpoint { - remote-endpoint = <&ipu2_di0_hdmi>; - }; - }; - - port@3 { - reg = <3>; - - hdmi_mux_3: endpoint { - remote-endpoint = <&ipu2_di1_hdmi>; - }; - }; -}; &ldb { - clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, + compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb"; + + clocks = <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>, <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>, - <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>; - clock-names = "di0_pll", "di1_pll", - "di0_sel", "di1_sel", "di2_sel", "di3_sel", - "di0", "di1"; - - lvds-channel@0 { - port@2 { - reg = <2>; - - lvds0_mux_2: endpoint { - remote-endpoint = <&ipu2_di0_lvds0>; - }; - }; - - port@3 { - reg = <3>; - - lvds0_mux_3: endpoint { - remote-endpoint = <&ipu2_di1_lvds0>; - }; - }; - }; - - lvds-channel@1 { - port@2 { - reg = <2>; - - lvds1_mux_2: endpoint { - remote-endpoint = <&ipu2_di0_lvds1>; - }; - }; + <&clks IMX6QDL_CLK_LDB_DI0_DIV_3_5>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_3_5>, + <&clks IMX6QDL_CLK_LDB_DI0_DIV_7>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_7>, + <&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>; + clock-names = "ldb_di0", "ldb_di1", + "di0_sel", "di1_sel", + "di2_sel", "di3_sel", + "ldb_di0_div_3_5", "ldb_di1_div_3_5", + "ldb_di0_div_7", "ldb_di1_div_7", + "ldb_di0_div_sel", "ldb_di1_div_sel"; - port@3 { - reg = <3>; - - lvds1_mux_3: endpoint { - remote-endpoint = <&ipu2_di1_lvds1>; - }; - }; - }; -}; - -&mipi_dsi { - ports { - port@2 { - reg = <2>; - - mipi_mux_2: endpoint { - remote-endpoint = <&ipu2_di0_mipi>; - }; - }; - - port@3 { - reg = <3>; - - mipi_mux_3: endpoint { - remote-endpoint = <&ipu2_di1_mipi>; - }; - }; - }; }; &vpu { diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index eaaa1d55bc54..e79cfb41fa48 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -1,5 +1,5 @@ /* - * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2012-2015 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. * * The code contained herein is licensed under the GNU General Public @@ -13,6 +13,13 @@ #include / { + aliases { + mxcfb0 = &mxcfb1; + mxcfb1 = &mxcfb2; + mxcfb2 = &mxcfb3; + mxcfb3 = &mxcfb4; + }; + memory: memory { reg = <0x10000000 0x80000000>; }; @@ -97,7 +104,63 @@ regulator-max-microvolt = <5000000>; regulator-always-on; }; + }; + + hannstar_cabc { + compatible = "hannstar,cabc"; + + lvds_share { + gpios = <&max7310_a 0 GPIO_ACTIVE_HIGH>; + }; + }; + + sound-hdmi { + compatible = "fsl,imx6q-audio-hdmi", + "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + }; + + mxcfb1: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb2: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1920x1080M@60"; + default_bpp = <24>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb3: fb@2 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "lcd"; + interface_pix_fmt = "RGB565"; + mode_str ="CLAA-WVGA"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + mxcfb4: fb@3 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; }; clocks { @@ -200,12 +263,44 @@ status = "okay"; }; +&hdmi_audio { + status = "okay"; +}; + +&hdmi_cec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_cec>; + status = "okay"; +}; + +&hdmi_core { + ipu_id = <0>; + disp_id = <1>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; + status = "okay"; +}; + &i2c2 { clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; + egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_egalax_int>; + interrupt-parent = <&gpio2>; + interrupts = <28 2>; + wakeup-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; + }; + pmic: pfuze100@08 { compatible = "fsl,pfuze100"; reg = <0x08>; @@ -305,6 +400,11 @@ }; }; + hdmi: edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; + codec: cs42888@48 { compatible = "cirrus,cs42888"; reg = <0x48>; @@ -421,6 +521,12 @@ >; }; + pinctrl_egalax_int: egalax_intgrp { + fsl,pins = < + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x80000000 + >; + }; + pinctrl_enet: enetgrp { fsl,pins = < MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 @@ -493,6 +599,30 @@ >; }; + pinctrl_ipu1_1: ipu1grp-1 { /* parallel port 16-bit */ + fsl,pins = < + MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000 + MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000 + MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000 + MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000 + MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000 + MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000 + MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000 + MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000 + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 @@ -650,6 +780,12 @@ >; }; }; + + pinctrl_hdmi_cec: hdmicecgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; }; &ldb { @@ -658,6 +794,7 @@ lvds-channel@0 { fsl,data-mapping = "spwg"; fsl,data-width = <18>; + primary; status = "okay"; display-timings { @@ -675,6 +812,27 @@ }; }; }; + + lvds-channel@1 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&timing1>; + timing1: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; }; &mlb { diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index e4e2c7448831..48739cc39236 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -1,5 +1,5 @@ /* - * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2012-2015 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. * * The code contained herein is licensed under the GNU General Public @@ -14,6 +14,23 @@ #include / { + aliases { + mxcfb0 = &mxcfb1; + mxcfb1 = &mxcfb2; + mxcfb2 = &mxcfb3; + mxcfb3 = &mxcfb4; + }; + + hannstar_cabc { + compatible = "hannstar,cabc"; + lvds0 { + gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; + }; + lvds1 { + gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; + }; + }; + chosen { stdout-path = &uart1; }; @@ -126,6 +143,65 @@ mux-ext-port = <3>; }; + sound-hdmi { + compatible = "fsl,imx6q-audio-hdmi", + "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + }; + + mxcfb1: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb2: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1920x1080M@60"; + default_bpp = <24>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb3: fb@2 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "lcd"; + interface_pix_fmt = "RGB565"; + mode_str ="CLAA-WVGA"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb4: fb@3 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + lcd@0 { + compatible = "fsl,lcd"; + ipu_id = <0>; + disp_id = <0>; + default_ifmt = "RGB565"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1>; + status = "okay"; + }; + backlight { compatible = "pwm-backlight"; pwms = <&pwm1 0 5000000>; @@ -176,8 +252,25 @@ status = "okay"; }; -&hdmi { - ddc-i2c-bus = <&i2c2>; +&hdmi_audio { + status = "okay"; +}; + +&hdmi_cec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_cec>; + status = "okay"; +}; + +&hdmi_core { + ipu_id = <0>; + disp_id = <0>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; status = "okay"; }; @@ -227,6 +320,14 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; + egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupt-parent = <&gpio6>; + interrupts = <8 2>; + wakeup-gpios = <&gpio6 8 0>; + }; + pmic: pfuze100@08 { compatible = "fsl,pfuze100"; reg = <0x08>; @@ -325,6 +426,11 @@ }; }; }; + + hdmi: edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; }; &i2c3 { @@ -374,6 +480,7 @@ MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x80000000 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 @@ -431,6 +538,19 @@ >; }; + pinctrl_hdmi_cec: hdmicecgrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_hdmi_hdcp: hdmihdcpgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 @@ -452,6 +572,57 @@ >; }; + pinctrl_ipu1: ipu1grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */ + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 + MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000 + >; + }; + pinctrl_pcie: pciegrp { fsl,pins = < MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 @@ -559,7 +730,7 @@ &ldb { status = "okay"; - lvds-channel@1 { + lvds-channel@0 { fsl,data-mapping = "spwg"; fsl,data-width = <18>; status = "okay"; @@ -579,6 +750,28 @@ }; }; }; + + lvds-channel@1 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + primary; + status = "okay"; + + display-timings { + native-mode = <&timing1>; + timing1: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; }; &pcie { diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 15a2dfb36152..d524b83c4186 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -1,5 +1,5 @@ /* - * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011-2015 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. * * The code contained herein is licensed under the GNU General Public @@ -30,6 +30,7 @@ i2c0 = &i2c1; i2c1 = &i2c2; i2c2 = &i2c3; + ipu0 = &ipu1; mmc0 = &usdhc1; mmc1 = &usdhc2; mmc2 = &usdhc3; @@ -181,6 +182,45 @@ interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; }; + hdmi_core: hdmi_core@00120000 { + compatible = "fsl,imx6q-hdmi-core"; + reg = <0x00120000 0x9000>; + clocks = <&clks IMX6QDL_CLK_HDMI_ISFR>, + <&clks IMX6QDL_CLK_HDMI_IAHB>, + <&clks IMX6QDL_CLK_HSI_TX>; + clock-names = "hdmi_isfr", "hdmi_iahb", "mipi_core"; + status = "disabled"; + }; + + hdmi_video: hdmi_video@020e0000 { + compatible = "fsl,imx6q-hdmi-video"; + reg = <0x020e0000 0x1000>; + reg-names = "hdmi_gpr"; + interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_HDMI_ISFR>, + <&clks IMX6QDL_CLK_HDMI_IAHB>, + <&clks IMX6QDL_CLK_HSI_TX>; + clock-names = "hdmi_isfr", "hdmi_iahb", "mipi_core"; + status = "disabled"; + }; + + hdmi_audio: hdmi_audio@00120000 { + compatible = "fsl,imx6q-hdmi-audio"; + clocks = <&clks IMX6QDL_CLK_HDMI_ISFR>, + <&clks IMX6QDL_CLK_HDMI_IAHB>, + <&clks IMX6QDL_CLK_HSI_TX>; + clock-names = "hdmi_isfr", "hdmi_iahb", "mipi_core"; + dmas = <&sdma 2 24 0>; + dma-names = "tx"; + status = "disabled"; + }; + + hdmi_cec: hdmi_cec@00120000 { + compatible = "fsl,imx6q-hdmi-cec"; + interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + aips-bus@02000000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; @@ -801,7 +841,6 @@ ldb: ldb@020e0008 { #address-cells = <1>; #size-cells = <0>; - compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb"; gpr = <&gpr>; status = "disabled"; @@ -810,22 +849,6 @@ #size-cells = <0>; reg = <0>; status = "disabled"; - - port@0 { - reg = <0>; - - lvds0_mux_0: endpoint { - remote-endpoint = <&ipu1_di0_lvds0>; - }; - }; - - port@1 { - reg = <1>; - - lvds0_mux_1: endpoint { - remote-endpoint = <&ipu1_di1_lvds0>; - }; - }; }; lvds-channel@1 { @@ -833,50 +856,6 @@ #size-cells = <0>; reg = <1>; status = "disabled"; - - port@0 { - reg = <0>; - - lvds1_mux_0: endpoint { - remote-endpoint = <&ipu1_di0_lvds1>; - }; - }; - - port@1 { - reg = <1>; - - lvds1_mux_1: endpoint { - remote-endpoint = <&ipu1_di1_lvds1>; - }; - }; - }; - }; - - hdmi: hdmi@0120000 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x00120000 0x9000>; - interrupts = <0 115 0x04>; - gpr = <&gpr>; - clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>, - <&clks IMX6QDL_CLK_HDMI_ISFR>; - clock-names = "iahb", "isfr"; - status = "disabled"; - - port@0 { - reg = <0>; - - hdmi_mux_0: endpoint { - remote-endpoint = <&ipu1_di0_hdmi>; - }; - }; - - port@1 { - reg = <1>; - - hdmi_mux_1: endpoint { - remote-endpoint = <&ipu1_di1_hdmi>; - }; }; }; @@ -1153,24 +1132,21 @@ port@0 { reg = <0>; - mipi_mux_0: endpoint { - remote-endpoint = <&ipu1_di0_mipi>; - }; }; port@1 { reg = <1>; - mipi_mux_1: endpoint { - remote-endpoint = <&ipu1_di1_mipi>; - }; }; }; }; vdoa@021e4000 { + compatible = "fsl,imx6q-vdoa"; reg = <0x021e4000 0x4000>; interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_VDOA>; + iram = <&ocram>; }; uart2: serial@021e8000 { @@ -1230,68 +1206,15 @@ interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>, <0 5 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_IPU1>, - <&clks IMX6QDL_CLK_IPU1_DI0>, - <&clks IMX6QDL_CLK_IPU1_DI1>; - clock-names = "bus", "di0", "di1"; + <&clks IMX6QDL_CLK_IPU1_DI0>, <&clks IMX6QDL_CLK_IPU1_DI1>, + <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, + <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>; + clock-names = "bus", + "di0", "di1", + "di0_sel", "di1_sel", + "ldb_di0", "ldb_di1"; resets = <&src 2>; - - ipu1_csi0: port@0 { - reg = <0>; - }; - - ipu1_csi1: port@1 { - reg = <1>; - }; - - ipu1_di0: port@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - ipu1_di0_disp0: endpoint@0 { - }; - - ipu1_di0_hdmi: endpoint@1 { - remote-endpoint = <&hdmi_mux_0>; - }; - - ipu1_di0_mipi: endpoint@2 { - remote-endpoint = <&mipi_mux_0>; - }; - - ipu1_di0_lvds0: endpoint@3 { - remote-endpoint = <&lvds0_mux_0>; - }; - - ipu1_di0_lvds1: endpoint@4 { - remote-endpoint = <&lvds1_mux_0>; - }; - }; - - ipu1_di1: port@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - ipu1_di0_disp1: endpoint@0 { - }; - - ipu1_di1_hdmi: endpoint@1 { - remote-endpoint = <&hdmi_mux_1>; - }; - - ipu1_di1_mipi: endpoint@2 { - remote-endpoint = <&mipi_mux_1>; - }; - - ipu1_di1_lvds0: endpoint@3 { - remote-endpoint = <&lvds0_mux_1>; - }; - - ipu1_di1_lvds1: endpoint@4 { - remote-endpoint = <&lvds1_mux_1>; - }; - }; + bypass_reset = <0>; }; }; }; diff --git a/arch/arm/boot/dts/imx6qp-sabreauto.dts b/arch/arm/boot/dts/imx6qp-sabreauto.dts index cc961c7700ed..c130dea8d55d 100644 --- a/arch/arm/boot/dts/imx6qp-sabreauto.dts +++ b/arch/arm/boot/dts/imx6qp-sabreauto.dts @@ -13,6 +13,22 @@ model = "Freescale i.MX6 Quad Plus SABRE Automotive Board"; }; +&mxcfb1 { + prefetch; +}; + +&mxcfb2 { + prefetch; +}; + +&mxcfb3 { + prefetch; +}; + +&mxcfb4 { + prefetch; +}; + &fec { pinctrl-assert-gpios = <&max7322 0 GPIO_ACTIVE_HIGH>; }; -- cgit v1.2.3