From e4d0573ae88aa7e1216fa6dbc0fcbeb61cc70a49 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Thu, 3 Sep 2015 01:05:48 +0800 Subject: MLK-11492 ARM: imx: keep weak 2p5 on for USB vbus wakeup Since i.MX6SX, if USB vbus wake up is enabled, weak 2P5 needs to be on even if the DRAM is LPDDR2, previously, we need to set stop_mode_config to keep 2P5 on, so enter DSM, if USB vbus wakeup is enabled, we need to keep weak 2P5 on. Signed-off-by: Anson Huang --- arch/arm/mach-imx/anatop.c | 6 ++++-- arch/arm/mach-imx/common.h | 1 + arch/arm/mach-imx/gpc.c | 21 +++++++++++++++++++++ 3 files changed, 26 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-imx/anatop.c b/arch/arm/mach-imx/anatop.c index 22c30081f020..9770a5f17d89 100644 --- a/arch/arm/mach-imx/anatop.c +++ b/arch/arm/mach-imx/anatop.c @@ -137,7 +137,8 @@ void imx_anatop_pre_suspend(void) if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0) imx_anatop_disable_pu(true); - if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2) + if ((imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2) && + !imx_gpc_usb_wakeup_enabled()) imx_anatop_enable_2p5_pulldown(true); else imx_anatop_enable_weak2p5(true); @@ -164,7 +165,8 @@ void imx_anatop_post_resume(void) if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0) imx_anatop_disable_pu(false); - if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2) + if ((imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2) && + !imx_gpc_usb_wakeup_enabled()) imx_anatop_enable_2p5_pulldown(false); else imx_anatop_enable_weak2p5(false); diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index 679c2979f65d..e8c369ad5245 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -174,6 +174,7 @@ void imx6sx_low_power_idle(void); void imx6q_enable_rbc(bool enable); void imx7d_low_power_idle(void); int imx7d_idle_secondary_finish(unsigned long val); +bool imx_gpc_usb_wakeup_enabled(void); void imx_cpu_die(unsigned int cpu); int imx_cpu_kill(unsigned int cpu); diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c index 88915c3232b6..6ee4127afb3f 100644 --- a/arch/arm/mach-imx/gpc.c +++ b/arch/arm/mach-imx/gpc.c @@ -62,6 +62,9 @@ #define DEFAULT_IPG_RATE 66000000 #define GPC_PU_UP_DELAY_MARGIN 2 +/* for irq #74 and #75 */ +#define GPC_USB_VBUS_WAKEUP_IRQ_MASK 0xc00 + struct pu_domain { struct generic_pm_domain base; struct regulator *reg; @@ -148,6 +151,24 @@ unsigned int imx_gpc_is_m4_sleeping(void) return 0; } +bool imx_gpc_usb_wakeup_enabled(void) +{ + if (!(cpu_is_imx6sx() || cpu_is_imx6ul())) + return false; + + /* + * for SoC later than i.MX6SX, USB vbus wakeup + * only needs weak 2P5 on, stop_mode_config is + * NOT needed, so we check if is USB vbus wakeup + * is enabled(assume irq #74 and #75) to decide + * if to keep weak 2P5 on. + */ + if (gpc_wake_irqs[1] & GPC_USB_VBUS_WAKEUP_IRQ_MASK) + return true; + + return false; +} + unsigned int imx_gpc_is_mf_mix_off(void) { return readl_relaxed(gpc_base + GPC_PGC_MF_PDN); -- cgit v1.2.3