From f4f4b4d6567ac6102e90a8d74c61474696766946 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 8 Jun 2012 11:40:27 +0300 Subject: video: tegra: host: Support per Soc hardware headers Make all chip specific functions static. Include the chip specific functions in SoC files after including the hardware headers. This makes the chip specific functions to be compiled per SoC, and with the correct hardware definitions. Bug 982965 Change-Id: I4774d4dc351951cb886d9d4da66cf021f3f0121e Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/107581 Reviewed-by: Automatic_Commit_Validation_User --- drivers/video/tegra/host/gr3d/gr3d.c | 4 +- drivers/video/tegra/host/gr3d/gr3d_t20.c | 4 +- drivers/video/tegra/host/gr3d/gr3d_t20.h | 3 + drivers/video/tegra/host/gr3d/gr3d_t30.c | 3 +- drivers/video/tegra/host/gr3d/gr3d_t30.h | 3 + drivers/video/tegra/host/host1x/Makefile | 7 +- .../video/tegra/host/host1x/host1x01_hardware.h | 170 ++++++++ drivers/video/tegra/host/host1x/host1x_cdma.c | 48 +-- drivers/video/tegra/host/host1x/host1x_cdma.h | 5 +- drivers/video/tegra/host/host1x/host1x_channel.c | 63 ++- drivers/video/tegra/host/host1x/host1x_channel.h | 45 -- drivers/video/tegra/host/host1x/host1x_debug.c | 19 +- drivers/video/tegra/host/host1x/host1x_hardware.h | 170 -------- drivers/video/tegra/host/host1x/host1x_intr.c | 27 +- drivers/video/tegra/host/host1x/host1x_syncpt.c | 32 +- drivers/video/tegra/host/host1x/host1x_syncpt.h | 7 - .../video/tegra/host/host1x/hw_host1x01_channel.h | 182 ++++++++ drivers/video/tegra/host/host1x/hw_host1x01_sync.h | 398 +++++++++++++++++ .../video/tegra/host/host1x/hw_host1x01_uclass.h | 474 +++++++++++++++++++++ .../video/tegra/host/host1x/hw_host1x_channel.h | 182 -------- drivers/video/tegra/host/host1x/hw_host1x_sync.h | 398 ----------------- drivers/video/tegra/host/host1x/hw_host1x_uclass.h | 474 --------------------- drivers/video/tegra/host/mpe/mpe.c | 4 +- drivers/video/tegra/host/t20/t20.c | 90 +--- drivers/video/tegra/host/t20/t20.h | 7 - drivers/video/tegra/host/t30/t30.c | 92 +--- drivers/video/tegra/host/t30/t30.h | 3 - 27 files changed, 1376 insertions(+), 1538 deletions(-) create mode 100644 drivers/video/tegra/host/host1x/host1x01_hardware.h delete mode 100644 drivers/video/tegra/host/host1x/host1x_channel.h delete mode 100644 drivers/video/tegra/host/host1x/host1x_hardware.h create mode 100644 drivers/video/tegra/host/host1x/hw_host1x01_channel.h create mode 100644 drivers/video/tegra/host/host1x/hw_host1x01_sync.h create mode 100644 drivers/video/tegra/host/host1x/hw_host1x01_uclass.h delete mode 100644 drivers/video/tegra/host/host1x/hw_host1x_channel.h delete mode 100644 drivers/video/tegra/host/host1x/hw_host1x_sync.h delete mode 100644 drivers/video/tegra/host/host1x/hw_host1x_uclass.h diff --git a/drivers/video/tegra/host/gr3d/gr3d.c b/drivers/video/tegra/host/gr3d/gr3d.c index 3cc041d3b3bb..e2af384fb09a 100644 --- a/drivers/video/tegra/host/gr3d/gr3d.c +++ b/drivers/video/tegra/host/gr3d/gr3d.c @@ -22,9 +22,7 @@ #include #include "t20/t20.h" -#include "host1x/host1x_channel.h" -#include "host1x/host1x_hardware.h" -#include "host1x/host1x_syncpt.h" +#include "host1x/host1x01_hardware.h" #include "nvhost_hwctx.h" #include "dev.h" #include "gr3d.h" diff --git a/drivers/video/tegra/host/gr3d/gr3d_t20.c b/drivers/video/tegra/host/gr3d/gr3d_t20.c index 23cd1557c420..b6e3896fe50c 100644 --- a/drivers/video/tegra/host/gr3d/gr3d_t20.c +++ b/drivers/video/tegra/host/gr3d/gr3d_t20.c @@ -21,9 +21,7 @@ #include "nvhost_hwctx.h" #include "nvhost_channel.h" #include "host1x/host1x.h" -#include "host1x/host1x_channel.h" -#include "host1x/host1x_hardware.h" -#include "host1x/host1x_syncpt.h" +#include "host1x/host1x01_hardware.h" #include "gr3d.h" #include "chip_support.h" #include "nvhost_memmgr.h" diff --git a/drivers/video/tegra/host/gr3d/gr3d_t20.h b/drivers/video/tegra/host/gr3d/gr3d_t20.h index 5fe6d50d0c30..e6fb8fdf8aba 100644 --- a/drivers/video/tegra/host/gr3d/gr3d_t20.h +++ b/drivers/video/tegra/host/gr3d/gr3d_t20.h @@ -21,7 +21,10 @@ #ifndef __NVHOST_GR3D_GR3D_T20_H #define __NVHOST_GR3D_GR3D_T20_H +#include + struct nvhost_hwctx_handler; +struct nvhost_channel; struct nvhost_hwctx_handler *nvhost_gr3d_t20_ctxhandler_init( u32 syncpt, u32 waitbase, diff --git a/drivers/video/tegra/host/gr3d/gr3d_t30.c b/drivers/video/tegra/host/gr3d/gr3d_t30.c index efff61304d20..8674a91024f6 100644 --- a/drivers/video/tegra/host/gr3d/gr3d_t30.c +++ b/drivers/video/tegra/host/gr3d/gr3d_t30.c @@ -22,8 +22,7 @@ #include "nvhost_channel.h" #include "nvhost_cdma.h" #include "dev.h" -#include "host1x/host1x_hardware.h" -#include "host1x/host1x_syncpt.h" +#include "host1x/host1x01_hardware.h" #include "gr3d.h" #include "chip_support.h" #include "nvhost_memmgr.h" diff --git a/drivers/video/tegra/host/gr3d/gr3d_t30.h b/drivers/video/tegra/host/gr3d/gr3d_t30.h index d1b787e14b44..94d5dc0f353b 100644 --- a/drivers/video/tegra/host/gr3d/gr3d_t30.h +++ b/drivers/video/tegra/host/gr3d/gr3d_t30.h @@ -21,7 +21,10 @@ #ifndef __NVHOST_GR3D_GR3D_T30_H #define __NVHOST_GR3D_GR3D_T30_H +#include + struct nvhost_hwctx_handler; +struct nvhost_channel; struct nvhost_hwctx_handler *nvhost_gr3d_t30_ctxhandler_init( u32 syncpt, u32 waitbase, diff --git a/drivers/video/tegra/host/host1x/Makefile b/drivers/video/tegra/host/host1x/Makefile index 55fcb375709a..76664945e12b 100644 --- a/drivers/video/tegra/host/host1x/Makefile +++ b/drivers/video/tegra/host/host1x/Makefile @@ -3,11 +3,6 @@ GCOV_PROFILE := y EXTRA_CFLAGS += -Idrivers/video/tegra/host nvhost-host1x-objs = \ - host1x.o \ - host1x_syncpt.o \ - host1x_channel.o \ - host1x_intr.o \ - host1x_cdma.o \ - host1x_debug.o + host1x.o obj-$(CONFIG_TEGRA_GRHOST) += nvhost-host1x.o diff --git a/drivers/video/tegra/host/host1x/host1x01_hardware.h b/drivers/video/tegra/host/host1x/host1x01_hardware.h new file mode 100644 index 000000000000..1d30cc74266a --- /dev/null +++ b/drivers/video/tegra/host/host1x/host1x01_hardware.h @@ -0,0 +1,170 @@ +/* + * drivers/video/tegra/host/host1x/host1x01_hardware.h + * + * Tegra Graphics Host Register Offsets for T20/T30 + * + * Copyright (c) 2010-2012 NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef __NVHOST_HOST1X01_HARDWARE_H +#define __NVHOST_HOST1X01_HARDWARE_H + +#include +#include +#include "hw_host1x01_channel.h" +#include "hw_host1x01_sync.h" +#include "hw_host1x01_uclass.h" + +/* class ids */ +enum { + NV_HOST1X_CLASS_ID = 0x1, + NV_VIDEO_ENCODE_MPEG_CLASS_ID = 0x20, + NV_GRAPHICS_3D_CLASS_ID = 0x60 +}; + + +/* channel registers */ +#define NV_HOST1X_CHANNEL_MAP_SIZE_BYTES 16384 +#define NV_HOST1X_SYNC_MLOCK_NUM 16 + +/* sync registers */ +#define HOST1X_CHANNEL_SYNC_REG_BASE 0x3000 +#define NV_HOST1X_NB_MLOCKS 16 + +static inline u32 nvhost_class_host_wait_syncpt( + unsigned indx, unsigned threshold) +{ + return (indx << 24) | (threshold & 0xffffff); +} + +static inline u32 nvhost_class_host_load_syncpt_base( + unsigned indx, unsigned threshold) +{ + return host1x_uclass_wait_syncpt_indx_f(indx) + | host1x_uclass_wait_syncpt_thresh_f(threshold); +} + +static inline u32 nvhost_class_host_wait_syncpt_base( + unsigned indx, unsigned base_indx, unsigned offset) +{ + return host1x_uclass_wait_syncpt_base_indx_f(indx) + | host1x_uclass_wait_syncpt_base_base_indx_f(base_indx) + | host1x_uclass_wait_syncpt_base_offset_f(offset); +} + +static inline u32 nvhost_class_host_incr_syncpt_base( + unsigned base_indx, unsigned offset) +{ + return host1x_uclass_incr_syncpt_base_base_indx_f(base_indx) + | host1x_uclass_incr_syncpt_base_offset_f(offset); +} + +static inline u32 nvhost_class_host_incr_syncpt( + unsigned cond, unsigned indx) +{ + return host1x_uclass_incr_syncpt_cond_f(cond) + | host1x_uclass_incr_syncpt_indx_f(indx); +} + +enum { + NV_HOST_MODULE_HOST1X = 0, + NV_HOST_MODULE_MPE = 1, + NV_HOST_MODULE_GR3D = 6 +}; + +static inline u32 nvhost_class_host_indoff_reg_write( + unsigned mod_id, unsigned offset, bool auto_inc) +{ + u32 v = host1x_uclass_indoff_indbe_f(0xf) + | host1x_uclass_indoff_indmodid_f(mod_id) + | host1x_uclass_indoff_indroffset_f(offset); + if (auto_inc) + v |= host1x_uclass_indoff_autoinc_f(1); + return v; +} + +static inline u32 nvhost_class_host_indoff_reg_read( + unsigned mod_id, unsigned offset, bool auto_inc) +{ + u32 v = host1x_uclass_indoff_indmodid_f(mod_id) + | host1x_uclass_indoff_indroffset_f(offset) + | host1x_uclass_indoff_rwn_read_v(); + if (auto_inc) + v |= host1x_uclass_indoff_autoinc_f(1); + return v; +} + + +/* cdma opcodes */ +static inline u32 nvhost_opcode_setclass( + unsigned class_id, unsigned offset, unsigned mask) +{ + return (0 << 28) | (offset << 16) | (class_id << 6) | mask; +} + +static inline u32 nvhost_opcode_incr(unsigned offset, unsigned count) +{ + return (1 << 28) | (offset << 16) | count; +} + +static inline u32 nvhost_opcode_nonincr(unsigned offset, unsigned count) +{ + return (2 << 28) | (offset << 16) | count; +} + +static inline u32 nvhost_opcode_mask(unsigned offset, unsigned mask) +{ + return (3 << 28) | (offset << 16) | mask; +} + +static inline u32 nvhost_opcode_imm(unsigned offset, unsigned value) +{ + return (4 << 28) | (offset << 16) | value; +} + +static inline u32 nvhost_opcode_imm_incr_syncpt(unsigned cond, unsigned indx) +{ + return nvhost_opcode_imm(host1x_uclass_incr_syncpt_r(), + nvhost_class_host_incr_syncpt(cond, indx)); +} + +static inline u32 nvhost_opcode_restart(unsigned address) +{ + return (5 << 28) | (address >> 4); +} + +static inline u32 nvhost_opcode_gather(unsigned count) +{ + return (6 << 28) | count; +} + +static inline u32 nvhost_opcode_gather_nonincr(unsigned offset, unsigned count) +{ + return (6 << 28) | (offset << 16) | BIT(15) | count; +} + +static inline u32 nvhost_opcode_gather_incr(unsigned offset, unsigned count) +{ + return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count; +} + +#define NVHOST_OPCODE_NOOP nvhost_opcode_nonincr(0, 0) + +static inline u32 nvhost_mask2(unsigned x, unsigned y) +{ + return 1 | (1 << (y - x)); +} + +#endif diff --git a/drivers/video/tegra/host/host1x/host1x_cdma.c b/drivers/video/tegra/host/host1x/host1x_cdma.c index 8017c71bdd14..2e7ff5783a37 100644 --- a/drivers/video/tegra/host/host1x/host1x_cdma.c +++ b/drivers/video/tegra/host/host1x/host1x_cdma.c @@ -26,8 +26,6 @@ #include "chip_support.h" #include "nvhost_memmgr.h" -#include "host1x_hardware.h" -#include "host1x_syncpt.h" #include "host1x_cdma.h" #include "host1x_hwctx.h" @@ -371,7 +369,7 @@ static void cdma_stop(struct nvhost_cdma *cdma) * Stops both channel's command processor and CDMA immediately. * Also, tears down the channel and resets corresponding module. */ -void cdma_timeout_teardown_begin(struct nvhost_cdma *cdma) +static void cdma_timeout_teardown_begin(struct nvhost_cdma *cdma) { struct nvhost_master *dev = cdma_to_dev(cdma); struct nvhost_channel *ch = cdma_to_channel(cdma); @@ -403,7 +401,7 @@ void cdma_timeout_teardown_begin(struct nvhost_cdma *cdma) cdma->torndown = true; } -void cdma_timeout_teardown_end(struct nvhost_cdma *cdma, u32 getptr) +static void cdma_timeout_teardown_end(struct nvhost_cdma *cdma, u32 getptr) { struct nvhost_master *dev = cdma_to_dev(cdma); struct nvhost_channel *ch = cdma_to_channel(cdma); @@ -492,25 +490,25 @@ static void cdma_timeout_handler(struct work_struct *work) mutex_unlock(&cdma->lock); } -int host1x_init_cdma_support(struct nvhost_chip_support *op) -{ - op->cdma.start = cdma_start; - op->cdma.stop = cdma_stop; - op->cdma.kick = cdma_kick; - - op->cdma.timeout_init = cdma_timeout_init; - op->cdma.timeout_destroy = cdma_timeout_destroy; - op->cdma.timeout_teardown_begin = cdma_timeout_teardown_begin; - op->cdma.timeout_teardown_end = cdma_timeout_teardown_end; - op->cdma.timeout_cpu_incr = cdma_timeout_cpu_incr; - - op->push_buffer.reset = push_buffer_reset; - op->push_buffer.init = push_buffer_init; - op->push_buffer.destroy = push_buffer_destroy; - op->push_buffer.push_to = push_buffer_push_to; - op->push_buffer.pop_from = push_buffer_pop_from; - op->push_buffer.space = push_buffer_space; - op->push_buffer.putptr = push_buffer_putptr; +static const struct nvhost_cdma_ops host1x_cdma_ops = { + .start = cdma_start, + .stop = cdma_stop, + .kick = cdma_kick, + + .timeout_init = cdma_timeout_init, + .timeout_destroy = cdma_timeout_destroy, + .timeout_teardown_begin = cdma_timeout_teardown_begin, + .timeout_teardown_end = cdma_timeout_teardown_end, + .timeout_cpu_incr = cdma_timeout_cpu_incr, +}; + +static const struct nvhost_pushbuffer_ops host1x_pushbuffer_ops = { + .reset = push_buffer_reset, + .init = push_buffer_init, + .destroy = push_buffer_destroy, + .push_to = push_buffer_push_to, + .pop_from = push_buffer_pop_from, + .space = push_buffer_space, + .putptr = push_buffer_putptr, +}; - return 0; -} diff --git a/drivers/video/tegra/host/host1x/host1x_cdma.h b/drivers/video/tegra/host/host1x/host1x_cdma.h index 9c533d6a5154..94bfc092c8c9 100644 --- a/drivers/video/tegra/host/host1x/host1x_cdma.h +++ b/drivers/video/tegra/host/host1x/host1x_cdma.h @@ -1,7 +1,7 @@ /* * drivers/video/tegra/host/host1x/host1x_cdma.h * - * Tegra Graphics Host Channel + * Tegra Graphics Host Command DMA * * Copyright (c) 2011-2012, NVIDIA Corporation. * @@ -36,7 +36,4 @@ * and replaces the original timed out contexts GATHER slots */ #define SYNCPT_INCR_BUFFER_SIZE_WORDS (4096 / sizeof(u32)) -struct nvhost_chip_support; -int host1x_init_cdma_support(struct nvhost_chip_support *); - #endif diff --git a/drivers/video/tegra/host/host1x/host1x_channel.c b/drivers/video/tegra/host/host1x/host1x_channel.c index 09f022b0f94d..98af5758df56 100644 --- a/drivers/video/tegra/host/host1x/host1x_channel.c +++ b/drivers/video/tegra/host/host1x/host1x_channel.c @@ -26,14 +26,14 @@ #include #include -#include "host1x_syncpt.h" -#include "host1x_channel.h" -#include "host1x_hardware.h" #include "host1x_hwctx.h" #include "nvhost_intr.h" #define NV_FIFO_READ_TIMEOUT 200000 +static int host1x_drain_read_fifo(struct nvhost_channel *ch, + u32 *ptr, unsigned int count, unsigned int *pending); + static void sync_waitbases(struct nvhost_channel *ch, u32 syncpt_val) { unsigned long waitbase; @@ -151,7 +151,7 @@ static void submit_ctxrestore(struct nvhost_job *job) trace_nvhost_channel_context_restore(ch->dev->name, &ctx->hwctx); } -void submit_nullkickoff(struct nvhost_job *job, int user_syncpt_incrs) +static void submit_nullkickoff(struct nvhost_job *job, int user_syncpt_incrs) { struct nvhost_channel *ch = job->ch; int incr; @@ -180,7 +180,7 @@ void submit_nullkickoff(struct nvhost_job *job, int user_syncpt_incrs) } } -void submit_gathers(struct nvhost_job *job) +static void submit_gathers(struct nvhost_job *job) { /* push user gathers */ int i; @@ -195,7 +195,7 @@ void submit_gathers(struct nvhost_job *job) } } -int host1x_channel_submit(struct nvhost_job *job) +static int host1x_channel_submit(struct nvhost_job *job) { struct nvhost_channel *ch = job->ch; struct nvhost_syncpt *sp = &nvhost_get_host(job->ch->dev)->syncpt; @@ -298,7 +298,7 @@ error: return err; } -int host1x_channel_read_3d_reg( +static int host1x_channel_read_3d_reg( struct nvhost_channel *channel, struct nvhost_hwctx *hwctx, u32 offset, @@ -485,7 +485,7 @@ done: } -int host1x_drain_read_fifo(struct nvhost_channel *ch, +static int host1x_drain_read_fifo(struct nvhost_channel *ch, u32 *ptr, unsigned int count, unsigned int *pending) { unsigned int entries = *pending; @@ -528,7 +528,7 @@ int host1x_drain_read_fifo(struct nvhost_channel *ch, return 0; } -int host1x_save_context(struct nvhost_channel *ch) +static int host1x_save_context(struct nvhost_channel *ch) { struct nvhost_device *dev = ch->dev; struct nvhost_hwctx *hwctx_to_save; @@ -622,3 +622,48 @@ done: kfree(wakeup_waiter); return err; } + +static inline void __iomem *host1x_channel_aperture(void __iomem *p, int ndx) +{ + p += ndx * NV_HOST1X_CHANNEL_MAP_SIZE_BYTES; + return p; +} + +static inline int host1x_hwctx_handler_init(struct nvhost_channel *ch) +{ + int err = 0; + unsigned long syncpts = ch->dev->syncpts; + unsigned long waitbases = ch->dev->waitbases; + u32 syncpt = find_first_bit(&syncpts, BITS_PER_LONG); + u32 waitbase = find_first_bit(&waitbases, BITS_PER_LONG); + struct nvhost_driver *drv = to_nvhost_driver(ch->dev->dev.driver); + + if (drv->alloc_hwctx_handler) { + ch->ctxhandler = drv->alloc_hwctx_handler(syncpt, + waitbase, ch); + if (!ch->ctxhandler) + err = -ENOMEM; + } + + return err; +} + +static int host1x_channel_init(struct nvhost_channel *ch, + struct nvhost_master *dev, int index) +{ + ch->chid = index; + mutex_init(&ch->reflock); + mutex_init(&ch->submitlock); + + ch->aperture = host1x_channel_aperture(dev->aperture, index); + + return host1x_hwctx_handler_init(ch); +} + +static const struct nvhost_channel_ops host1x_channel_ops = { + .init = host1x_channel_init, + .submit = host1x_channel_submit, + .read3dreg = host1x_channel_read_3d_reg, + .save_context = host1x_save_context, + .drain_read_fifo = host1x_drain_read_fifo, +}; diff --git a/drivers/video/tegra/host/host1x/host1x_channel.h b/drivers/video/tegra/host/host1x/host1x_channel.h deleted file mode 100644 index 98a67c7985ab..000000000000 --- a/drivers/video/tegra/host/host1x/host1x_channel.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * drivers/video/tegra/host/host1x/host1x_channel.h - * - * Tegra Graphics Host Channel - * - * Copyright (c) 2011-2012, NVIDIA Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef __NVHOST_HOST1X_CHANNEL_H -#define __NVHOST_HOST1X_CHANNEL_H - -struct nvhost_job; -struct nvhost_channel; -struct nvhost_hwctx; -struct nvhost_device; - -/* Submit job to a host1x client */ -int host1x_channel_submit(struct nvhost_job *job); - -/* Read 3d register via FIFO */ -int host1x_channel_read_3d_reg( - struct nvhost_channel *channel, - struct nvhost_hwctx *hwctx, - u32 offset, - u32 *value); - -/* Reads words from FIFO */ -int host1x_drain_read_fifo(struct nvhost_channel *ch, - u32 *ptr, unsigned int count, unsigned int *pending); - -int host1x_save_context(struct nvhost_channel *ch); - -#endif diff --git a/drivers/video/tegra/host/host1x/host1x_debug.c b/drivers/video/tegra/host/host1x/host1x_debug.c index ff70acd23315..1c4ed684dd84 100644 --- a/drivers/video/tegra/host/host1x/host1x_debug.c +++ b/drivers/video/tegra/host/host1x/host1x_debug.c @@ -25,10 +25,8 @@ #include "dev.h" #include "debug.h" -#include "host1x_hardware.h" #include "nvhost_cdma.h" #include "nvhost_channel.h" -#include "host1x_cdma.h" #include "nvhost_job.h" #include "chip_support.h" #include "nvhost_memmgr.h" @@ -229,7 +227,7 @@ static void show_channel_gather(struct output *o, u32 addr, #endif } -void show_channel_gathers(struct output *o, struct nvhost_cdma *cdma) +static void show_channel_gathers(struct output *o, struct nvhost_cdma *cdma) { struct nvhost_job *job; @@ -324,7 +322,7 @@ static void t20_debug_show_channel_cdma(struct nvhost_master *m, nvhost_debug_output(o, "\n"); } -void t20_debug_show_channel_fifo(struct nvhost_master *m, +static void t20_debug_show_channel_fifo(struct nvhost_master *m, struct nvhost_channel *ch, struct output *o, int chid) { u32 val, rd_ptr, wr_ptr, start, end; @@ -400,11 +398,8 @@ static void t20_debug_show_mlocks(struct nvhost_master *m, struct output *o) nvhost_debug_output(o, "\n"); } -int nvhost_init_t20_debug_support(struct nvhost_chip_support *op) -{ - op->debug.show_channel_cdma = t20_debug_show_channel_cdma; - op->debug.show_channel_fifo = t20_debug_show_channel_fifo; - op->debug.show_mlocks = t20_debug_show_mlocks; - - return 0; -} +static const struct nvhost_debug_ops host1x_debug_ops = { + .show_channel_cdma = t20_debug_show_channel_cdma, + .show_channel_fifo = t20_debug_show_channel_fifo, + .show_mlocks = t20_debug_show_mlocks, +}; diff --git a/drivers/video/tegra/host/host1x/host1x_hardware.h b/drivers/video/tegra/host/host1x/host1x_hardware.h deleted file mode 100644 index 357b61d42b50..000000000000 --- a/drivers/video/tegra/host/host1x/host1x_hardware.h +++ /dev/null @@ -1,170 +0,0 @@ -/* - * drivers/video/tegra/host/host1x/host1x_hardware.h - * - * Tegra Graphics Host Register Offsets - * - * Copyright (c) 2010-2012 NVIDIA Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef __NVHOST_HOST1X_HOST1X_HARDWARE_H -#define __NVHOST_HOST1X_HOST1X_HARDWARE_H - -#include -#include -#include "hw_host1x_channel.h" -#include "hw_host1x_sync.h" -#include "hw_host1x_uclass.h" - -/* class ids */ -enum { - NV_HOST1X_CLASS_ID = 0x1, - NV_VIDEO_ENCODE_MPEG_CLASS_ID = 0x20, - NV_GRAPHICS_3D_CLASS_ID = 0x60 -}; - - -/* channel registers */ -#define NV_HOST1X_CHANNEL_MAP_SIZE_BYTES 16384 -#define NV_HOST1X_SYNC_MLOCK_NUM 16 - -/* sync registers */ -#define HOST1X_CHANNEL_SYNC_REG_BASE 0x3000 -#define NV_HOST1X_NB_MLOCKS 16 - -static inline u32 nvhost_class_host_wait_syncpt( - unsigned indx, unsigned threshold) -{ - return (indx << 24) | (threshold & 0xffffff); -} - -static inline u32 nvhost_class_host_load_syncpt_base( - unsigned indx, unsigned threshold) -{ - return host1x_uclass_wait_syncpt_indx_f(indx) - | host1x_uclass_wait_syncpt_thresh_f(threshold); -} - -static inline u32 nvhost_class_host_wait_syncpt_base( - unsigned indx, unsigned base_indx, unsigned offset) -{ - return host1x_uclass_wait_syncpt_base_indx_f(indx) - | host1x_uclass_wait_syncpt_base_base_indx_f(base_indx) - | host1x_uclass_wait_syncpt_base_offset_f(offset); -} - -static inline u32 nvhost_class_host_incr_syncpt_base( - unsigned base_indx, unsigned offset) -{ - return host1x_uclass_incr_syncpt_base_base_indx_f(base_indx) - | host1x_uclass_incr_syncpt_base_offset_f(offset); -} - -static inline u32 nvhost_class_host_incr_syncpt( - unsigned cond, unsigned indx) -{ - return host1x_uclass_incr_syncpt_cond_f(cond) - | host1x_uclass_incr_syncpt_indx_f(indx); -} - -enum { - NV_HOST_MODULE_HOST1X = 0, - NV_HOST_MODULE_MPE = 1, - NV_HOST_MODULE_GR3D = 6 -}; - -static inline u32 nvhost_class_host_indoff_reg_write( - unsigned mod_id, unsigned offset, bool auto_inc) -{ - u32 v = host1x_uclass_indoff_indbe_f(0xf) - | host1x_uclass_indoff_indmodid_f(mod_id) - | host1x_uclass_indoff_indroffset_f(offset); - if (auto_inc) - v |= host1x_uclass_indoff_autoinc_f(1); - return v; -} - -static inline u32 nvhost_class_host_indoff_reg_read( - unsigned mod_id, unsigned offset, bool auto_inc) -{ - u32 v = host1x_uclass_indoff_indmodid_f(mod_id) - | host1x_uclass_indoff_indroffset_f(offset) - | host1x_uclass_indoff_rwn_read_v(); - if (auto_inc) - v |= host1x_uclass_indoff_autoinc_f(1); - return v; -} - - -/* cdma opcodes */ -static inline u32 nvhost_opcode_setclass( - unsigned class_id, unsigned offset, unsigned mask) -{ - return (0 << 28) | (offset << 16) | (class_id << 6) | mask; -} - -static inline u32 nvhost_opcode_incr(unsigned offset, unsigned count) -{ - return (1 << 28) | (offset << 16) | count; -} - -static inline u32 nvhost_opcode_nonincr(unsigned offset, unsigned count) -{ - return (2 << 28) | (offset << 16) | count; -} - -static inline u32 nvhost_opcode_mask(unsigned offset, unsigned mask) -{ - return (3 << 28) | (offset << 16) | mask; -} - -static inline u32 nvhost_opcode_imm(unsigned offset, unsigned value) -{ - return (4 << 28) | (offset << 16) | value; -} - -static inline u32 nvhost_opcode_imm_incr_syncpt(unsigned cond, unsigned indx) -{ - return nvhost_opcode_imm(host1x_uclass_incr_syncpt_r(), - nvhost_class_host_incr_syncpt(cond, indx)); -} - -static inline u32 nvhost_opcode_restart(unsigned address) -{ - return (5 << 28) | (address >> 4); -} - -static inline u32 nvhost_opcode_gather(unsigned count) -{ - return (6 << 28) | count; -} - -static inline u32 nvhost_opcode_gather_nonincr(unsigned offset, unsigned count) -{ - return (6 << 28) | (offset << 16) | BIT(15) | count; -} - -static inline u32 nvhost_opcode_gather_incr(unsigned offset, unsigned count) -{ - return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count; -} - -#define NVHOST_OPCODE_NOOP nvhost_opcode_nonincr(0, 0) - -static inline u32 nvhost_mask2(unsigned x, unsigned y) -{ - return 1 | (1 << (y - x)); -} - -#endif diff --git a/drivers/video/tegra/host/host1x/host1x_intr.c b/drivers/video/tegra/host/host1x/host1x_intr.c index 6ec6dd394ebb..62fd07cbb9ba 100644 --- a/drivers/video/tegra/host/host1x/host1x_intr.c +++ b/drivers/video/tegra/host/host1x/host1x_intr.c @@ -26,8 +26,6 @@ #include "nvhost_intr.h" #include "dev.h" -#include "host1x_hardware.h" -#include "chip_support.h" /* Spacing between sync registers */ #define REGISTER_STRIDE 4 @@ -158,7 +156,7 @@ static void t20_intr_disable_all_syncpt_intrs(struct nvhost_intr *intr) * Sync point threshold interrupt service function * Handles sync point threshold triggers, in interrupt context */ -irqreturn_t t20_intr_syncpt_thresh_isr(int irq, void *dev_id) +static irqreturn_t t20_intr_syncpt_thresh_isr(int irq, void *dev_id) { struct nvhost_intr_syncpt *syncpt = dev_id; unsigned int id = syncpt->id; @@ -273,16 +271,13 @@ static int t20_request_syncpt_irq(struct nvhost_intr_syncpt *syncpt) return 0; } -int nvhost_init_t20_intr_support(struct nvhost_chip_support *op) -{ - op->intr.init_host_sync = t20_intr_init_host_sync; - op->intr.set_host_clocks_per_usec = t20_intr_set_host_clocks_per_usec; - op->intr.set_syncpt_threshold = t20_intr_set_syncpt_threshold; - op->intr.enable_syncpt_intr = t20_intr_enable_syncpt_intr; - op->intr.disable_all_syncpt_intrs = t20_intr_disable_all_syncpt_intrs; - op->intr.request_host_general_irq = t20_intr_request_host_general_irq; - op->intr.free_host_general_irq = t20_intr_free_host_general_irq; - op->intr.request_syncpt_irq = t20_request_syncpt_irq; - - return 0; -} +static const struct nvhost_intr_ops host1x_intr_ops = { + .init_host_sync = t20_intr_init_host_sync, + .set_host_clocks_per_usec = t20_intr_set_host_clocks_per_usec, + .set_syncpt_threshold = t20_intr_set_syncpt_threshold, + .enable_syncpt_intr = t20_intr_enable_syncpt_intr, + .disable_all_syncpt_intrs = t20_intr_disable_all_syncpt_intrs, + .request_host_general_irq = t20_intr_request_host_general_irq, + .free_host_general_irq = t20_intr_free_host_general_irq, + .request_syncpt_irq = t20_request_syncpt_irq, +}; diff --git a/drivers/video/tegra/host/host1x/host1x_syncpt.c b/drivers/video/tegra/host/host1x/host1x_syncpt.c index c53733cf2766..8cca9dbbbc08 100644 --- a/drivers/video/tegra/host/host1x/host1x_syncpt.c +++ b/drivers/video/tegra/host/host1x/host1x_syncpt.c @@ -24,8 +24,6 @@ #include "nvhost_syncpt.h" #include "nvhost_acm.h" #include "host1x.h" -#include "host1x_syncpt.h" -#include "host1x_hardware.h" #include "chip_support.h" /** @@ -168,21 +166,15 @@ static void syncpt_mutex_unlock(struct nvhost_syncpt *sp, writel(0, sync_regs + (host1x_sync_mlock_0_r() + idx * 4)); } -int host1x_init_syncpt_support(struct nvhost_master *host, - struct nvhost_chip_support *op) -{ - host->sync_aperture = host->aperture + HOST1X_CHANNEL_SYNC_REG_BASE; - - op->syncpt.reset = t20_syncpt_reset; - op->syncpt.reset_wait_base = t20_syncpt_reset_wait_base; - op->syncpt.read_wait_base = t20_syncpt_read_wait_base; - op->syncpt.update_min = t20_syncpt_update_min; - op->syncpt.cpu_incr = t20_syncpt_cpu_incr; - op->syncpt.patch_wait = host1x_syncpt_patch_wait; - op->syncpt.debug = t20_syncpt_debug; - op->syncpt.name = t20_syncpt_name; - op->syncpt.mutex_try_lock = syncpt_mutex_try_lock; - op->syncpt.mutex_unlock = syncpt_mutex_unlock; - - return 0; -} +static const struct nvhost_syncpt_ops host1x_syncpt_ops = { + .reset = t20_syncpt_reset, + .reset_wait_base = t20_syncpt_reset_wait_base, + .read_wait_base = t20_syncpt_read_wait_base, + .update_min = t20_syncpt_update_min, + .cpu_incr = t20_syncpt_cpu_incr, + .patch_wait = host1x_syncpt_patch_wait, + .debug = t20_syncpt_debug, + .name = t20_syncpt_name, + .mutex_try_lock = syncpt_mutex_try_lock, + .mutex_unlock = syncpt_mutex_unlock, +}; diff --git a/drivers/video/tegra/host/host1x/host1x_syncpt.h b/drivers/video/tegra/host/host1x/host1x_syncpt.h index f624a755da9c..8440ef1047ed 100644 --- a/drivers/video/tegra/host/host1x/host1x_syncpt.h +++ b/drivers/video/tegra/host/host1x/host1x_syncpt.h @@ -63,11 +63,4 @@ #define NVWAITBASE_3D (3) #define NVWAITBASE_MPE (4) -struct nvhost_master; -struct nvhost_chip_support; - -int host1x_init_syncpt(struct nvhost_master *host); -int host1x_init_syncpt_support(struct nvhost_master *host, - struct nvhost_chip_support *op); - #endif diff --git a/drivers/video/tegra/host/host1x/hw_host1x01_channel.h b/drivers/video/tegra/host/host1x/hw_host1x01_channel.h new file mode 100644 index 000000000000..ca2f9a0778cd --- /dev/null +++ b/drivers/video/tegra/host/host1x/hw_host1x01_channel.h @@ -0,0 +1,182 @@ +/* + * drivers/video/tegra/host/host1x/hw_host1x_channel_host1x.h + * + * Copyright (c) 2012, NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + */ + + /* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ + +#ifndef __hw_host1x_channel_host1x_h__ +#define __hw_host1x_channel_host1x_h__ +/*This file is autogenerated. Do not edit. */ + +static inline u32 host1x_channel_fifostat_r(void) +{ + return 0x0; +} +static inline u32 host1x_channel_fifostat_cfempty_s(void) +{ + return 1; +} +static inline u32 host1x_channel_fifostat_cfempty_f(u32 v) +{ + return (v & 0x1) << 10; +} +static inline u32 host1x_channel_fifostat_cfempty_m(void) +{ + return 0x1 << 10; +} +static inline u32 host1x_channel_fifostat_cfempty_v(u32 r) +{ + return (r >> 10) & 0x1; +} +static inline u32 host1x_channel_fifostat_cfempty_notempty_v(void) +{ + return 0; +} +static inline u32 host1x_channel_fifostat_cfempty_empty_v(void) +{ + return 1; +} +static inline u32 host1x_channel_fifostat_outfentries_s(void) +{ + return 5; +} +static inline u32 host1x_channel_fifostat_outfentries_f(u32 v) +{ + return (v & 0x1f) << 24; +} +static inline u32 host1x_channel_fifostat_outfentries_m(void) +{ + return 0x1f << 24; +} +static inline u32 host1x_channel_fifostat_outfentries_v(u32 r) +{ + return (r >> 24) & 0x1f; +} +static inline u32 host1x_channel_inddata_r(void) +{ + return 0xc; +} +static inline u32 host1x_channel_dmastart_r(void) +{ + return 0x14; +} +static inline u32 host1x_channel_dmaput_r(void) +{ + return 0x18; +} +static inline u32 host1x_channel_dmaget_r(void) +{ + return 0x1c; +} +static inline u32 host1x_channel_dmaend_r(void) +{ + return 0x20; +} +static inline u32 host1x_channel_dmactrl_r(void) +{ + return 0x24; +} +static inline u32 host1x_channel_dmactrl_dmastop_s(void) +{ + return 1; +} +static inline u32 host1x_channel_dmactrl_dmastop_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 host1x_channel_dmactrl_dmastop_m(void) +{ + return 0x1 << 0; +} +static inline u32 host1x_channel_dmactrl_dmastop_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 host1x_channel_dmactrl_dmastop_run_v(void) +{ + return 0; +} +static inline u32 host1x_channel_dmactrl_dmastop_stop_v(void) +{ + return 1; +} +static inline u32 host1x_channel_dmactrl_dmagetrst_s(void) +{ + return 1; +} +static inline u32 host1x_channel_dmactrl_dmagetrst_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 host1x_channel_dmactrl_dmagetrst_m(void) +{ + return 0x1 << 1; +} +static inline u32 host1x_channel_dmactrl_dmagetrst_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 host1x_channel_dmactrl_dmainitget_s(void) +{ + return 1; +} +static inline u32 host1x_channel_dmactrl_dmainitget_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 host1x_channel_dmactrl_dmainitget_m(void) +{ + return 0x1 << 2; +} +static inline u32 host1x_channel_dmactrl_dmainitget_v(u32 r) +{ + return (r >> 2) & 0x1; +} + +#endif /* __hw_host1x_channel_host1x_h__ */ diff --git a/drivers/video/tegra/host/host1x/hw_host1x01_sync.h b/drivers/video/tegra/host/host1x/hw_host1x01_sync.h new file mode 100644 index 000000000000..67f0cbfb85b9 --- /dev/null +++ b/drivers/video/tegra/host/host1x/hw_host1x01_sync.h @@ -0,0 +1,398 @@ +/* + * drivers/video/tegra/host/host1x/hw_host1x_sync_host1x.h + * + * Copyright (c) 2012, NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + */ + + /* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ + +#ifndef __hw_host1x_sync_host1x_h__ +#define __hw_host1x_sync_host1x_h__ +/*This file is autogenerated. Do not edit. */ + +static inline u32 host1x_sync_intmask_r(void) +{ + return 0x4; +} +static inline u32 host1x_sync_intc0mask_r(void) +{ + return 0x8; +} +static inline u32 host1x_sync_hintstatus_r(void) +{ + return 0x20; +} +static inline u32 host1x_sync_hintmask_r(void) +{ + return 0x24; +} +static inline u32 host1x_sync_hintstatus_ext_r(void) +{ + return 0x28; +} +static inline u32 host1x_sync_hintstatus_ext_ip_read_int_s(void) +{ + return 1; +} +static inline u32 host1x_sync_hintstatus_ext_ip_read_int_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 host1x_sync_hintstatus_ext_ip_read_int_m(void) +{ + return 0x1 << 30; +} +static inline u32 host1x_sync_hintstatus_ext_ip_read_int_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 host1x_sync_hintstatus_ext_ip_write_int_s(void) +{ + return 1; +} +static inline u32 host1x_sync_hintstatus_ext_ip_write_int_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 host1x_sync_hintstatus_ext_ip_write_int_m(void) +{ + return 0x1 << 31; +} +static inline u32 host1x_sync_hintstatus_ext_ip_write_int_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 host1x_sync_hintmask_ext_r(void) +{ + return 0x2c; +} +static inline u32 host1x_sync_syncpt_thresh_cpu0_int_status_r(void) +{ + return 0x40; +} +static inline u32 host1x_sync_syncpt_thresh_cpu1_int_status_r(void) +{ + return 0x48; +} +static inline u32 host1x_sync_syncpt_thresh_int_disable_r(void) +{ + return 0x60; +} +static inline u32 host1x_sync_syncpt_thresh_int_enable_cpu0_r(void) +{ + return 0x68; +} +static inline u32 host1x_sync_cf0_setup_r(void) +{ + return 0x80; +} +static inline u32 host1x_sync_cf0_setup_cf0_base_s(void) +{ + return 9; +} +static inline u32 host1x_sync_cf0_setup_cf0_base_f(u32 v) +{ + return (v & 0x1ff) << 0; +} +static inline u32 host1x_sync_cf0_setup_cf0_base_m(void) +{ + return 0x1ff << 0; +} +static inline u32 host1x_sync_cf0_setup_cf0_base_v(u32 r) +{ + return (r >> 0) & 0x1ff; +} +static inline u32 host1x_sync_cf0_setup_cf0_limit_s(void) +{ + return 9; +} +static inline u32 host1x_sync_cf0_setup_cf0_limit_f(u32 v) +{ + return (v & 0x1ff) << 16; +} +static inline u32 host1x_sync_cf0_setup_cf0_limit_m(void) +{ + return 0x1ff << 16; +} +static inline u32 host1x_sync_cf0_setup_cf0_limit_v(u32 r) +{ + return (r >> 16) & 0x1ff; +} +static inline u32 host1x_sync_cmdproc_stop_r(void) +{ + return 0xac; +} +static inline u32 host1x_sync_ch_teardown_r(void) +{ + return 0xb0; +} +static inline u32 host1x_sync_usec_clk_r(void) +{ + return 0x1a4; +} +static inline u32 host1x_sync_ctxsw_timeout_cfg_r(void) +{ + return 0x1a8; +} +static inline u32 host1x_sync_ip_busy_timeout_r(void) +{ + return 0x1bc; +} +static inline u32 host1x_sync_ip_read_timeout_addr_r(void) +{ + return 0x1c0; +} +static inline u32 host1x_sync_ip_write_timeout_addr_r(void) +{ + return 0x1c4; +} +static inline u32 host1x_sync_mlock_0_r(void) +{ + return 0x2c0; +} +static inline u32 host1x_sync_mlock_owner_0_r(void) +{ + return 0x340; +} +static inline u32 host1x_sync_mlock_owner_0_mlock_owner_chid_0_s(void) +{ + return 4; +} +static inline u32 host1x_sync_mlock_owner_0_mlock_owner_chid_0_f(u32 v) +{ + return (v & 0xf) << 8; +} +static inline u32 host1x_sync_mlock_owner_0_mlock_owner_chid_0_m(void) +{ + return 0xf << 8; +} +static inline u32 host1x_sync_mlock_owner_0_mlock_owner_chid_0_v(u32 r) +{ + return (r >> 8) & 0xf; +} +static inline u32 host1x_sync_mlock_owner_0_mlock_cpu_owns_0_s(void) +{ + return 1; +} +static inline u32 host1x_sync_mlock_owner_0_mlock_cpu_owns_0_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 host1x_sync_mlock_owner_0_mlock_cpu_owns_0_m(void) +{ + return 0x1 << 1; +} +static inline u32 host1x_sync_mlock_owner_0_mlock_cpu_owns_0_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 host1x_sync_mlock_owner_0_mlock_ch_owns_0_s(void) +{ + return 1; +} +static inline u32 host1x_sync_mlock_owner_0_mlock_ch_owns_0_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 host1x_sync_mlock_owner_0_mlock_ch_owns_0_m(void) +{ + return 0x1 << 0; +} +static inline u32 host1x_sync_mlock_owner_0_mlock_ch_owns_0_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 host1x_sync_syncpt_0_r(void) +{ + return 0x400; +} +static inline u32 host1x_sync_syncpt_int_thresh_0_r(void) +{ + return 0x500; +} +static inline u32 host1x_sync_syncpt_base_0_r(void) +{ + return 0x600; +} +static inline u32 host1x_sync_syncpt_cpu_incr_r(void) +{ + return 0x700; +} +static inline u32 host1x_sync_cbread0_r(void) +{ + return 0x720; +} +static inline u32 host1x_sync_cfpeek_ctrl_r(void) +{ + return 0x74c; +} +static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_addr_s(void) +{ + return 9; +} +static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_addr_f(u32 v) +{ + return (v & 0x1ff) << 0; +} +static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_addr_m(void) +{ + return 0x1ff << 0; +} +static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_addr_v(u32 r) +{ + return (r >> 0) & 0x1ff; +} +static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_channr_s(void) +{ + return 3; +} +static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_channr_f(u32 v) +{ + return (v & 0x7) << 16; +} +static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_channr_m(void) +{ + return 0x7 << 16; +} +static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_channr_v(u32 r) +{ + return (r >> 16) & 0x7; +} +static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_ena_s(void) +{ + return 1; +} +static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_ena_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_ena_m(void) +{ + return 0x1 << 31; +} +static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_ena_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 host1x_sync_cfpeek_read_r(void) +{ + return 0x750; +} +static inline u32 host1x_sync_cfpeek_ptrs_r(void) +{ + return 0x754; +} +static inline u32 host1x_sync_cfpeek_ptrs_cf_rd_ptr_s(void) +{ + return 9; +} +static inline u32 host1x_sync_cfpeek_ptrs_cf_rd_ptr_f(u32 v) +{ + return (v & 0x1ff) << 0; +} +static inline u32 host1x_sync_cfpeek_ptrs_cf_rd_ptr_m(void) +{ + return 0x1ff << 0; +} +static inline u32 host1x_sync_cfpeek_ptrs_cf_rd_ptr_v(u32 r) +{ + return (r >> 0) & 0x1ff; +} +static inline u32 host1x_sync_cfpeek_ptrs_cf_wr_ptr_s(void) +{ + return 9; +} +static inline u32 host1x_sync_cfpeek_ptrs_cf_wr_ptr_f(u32 v) +{ + return (v & 0x1ff) << 16; +} +static inline u32 host1x_sync_cfpeek_ptrs_cf_wr_ptr_m(void) +{ + return 0x1ff << 16; +} +static inline u32 host1x_sync_cfpeek_ptrs_cf_wr_ptr_v(u32 r) +{ + return (r >> 16) & 0x1ff; +} +static inline u32 host1x_sync_cbstat_0_r(void) +{ + return 0x758; +} +static inline u32 host1x_sync_cbstat_0_cboffset0_s(void) +{ + return 16; +} +static inline u32 host1x_sync_cbstat_0_cboffset0_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 host1x_sync_cbstat_0_cboffset0_m(void) +{ + return 0xffff << 0; +} +static inline u32 host1x_sync_cbstat_0_cboffset0_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 host1x_sync_cbstat_0_cbclass0_s(void) +{ + return 10; +} +static inline u32 host1x_sync_cbstat_0_cbclass0_f(u32 v) +{ + return (v & 0x3ff) << 16; +} +static inline u32 host1x_sync_cbstat_0_cbclass0_m(void) +{ + return 0x3ff << 16; +} +static inline u32 host1x_sync_cbstat_0_cbclass0_v(u32 r) +{ + return (r >> 16) & 0x3ff; +} + +#endif /* __hw_host1x_sync_host1x_h__ */ diff --git a/drivers/video/tegra/host/host1x/hw_host1x01_uclass.h b/drivers/video/tegra/host/host1x/hw_host1x01_uclass.h new file mode 100644 index 000000000000..ed6e4b706ab9 --- /dev/null +++ b/drivers/video/tegra/host/host1x/hw_host1x01_uclass.h @@ -0,0 +1,474 @@ +/* + * drivers/video/tegra/host/host1x/hw_host1x_uclass_host1x.h + * + * Copyright (c) 2012, NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + */ + + /* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ + +#ifndef __hw_host1x_uclass_host1x_h__ +#define __hw_host1x_uclass_host1x_h__ +/*This file is autogenerated. Do not edit. */ + +static inline u32 host1x_uclass_incr_syncpt_r(void) +{ + return 0x0; +} +static inline u32 host1x_uclass_incr_syncpt_cond_s(void) +{ + return 8; +} +static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 host1x_uclass_incr_syncpt_cond_m(void) +{ + return 0xff << 8; +} +static inline u32 host1x_uclass_incr_syncpt_cond_v(u32 r) +{ + return (r >> 8) & 0xff; +} +static inline u32 host1x_uclass_incr_syncpt_cond_immediate_v(void) +{ + return 0; +} +static inline u32 host1x_uclass_incr_syncpt_cond_op_done_v(void) +{ + return 1; +} +static inline u32 host1x_uclass_incr_syncpt_cond_rd_done_v(void) +{ + return 2; +} +static inline u32 host1x_uclass_incr_syncpt_cond_reg_wr_safe_v(void) +{ + return 3; +} +static inline u32 host1x_uclass_incr_syncpt_indx_s(void) +{ + return 8; +} +static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 host1x_uclass_incr_syncpt_indx_m(void) +{ + return 0xff << 0; +} +static inline u32 host1x_uclass_incr_syncpt_indx_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 host1x_uclass_wait_syncpt_r(void) +{ + return 0x8; +} +static inline u32 host1x_uclass_wait_syncpt_indx_s(void) +{ + return 8; +} +static inline u32 host1x_uclass_wait_syncpt_indx_f(u32 v) +{ + return (v & 0xff) << 24; +} +static inline u32 host1x_uclass_wait_syncpt_indx_m(void) +{ + return 0xff << 24; +} +static inline u32 host1x_uclass_wait_syncpt_indx_v(u32 r) +{ + return (r >> 24) & 0xff; +} +static inline u32 host1x_uclass_wait_syncpt_thresh_s(void) +{ + return 24; +} +static inline u32 host1x_uclass_wait_syncpt_thresh_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +static inline u32 host1x_uclass_wait_syncpt_thresh_m(void) +{ + return 0xffffff << 0; +} +static inline u32 host1x_uclass_wait_syncpt_thresh_v(u32 r) +{ + return (r >> 0) & 0xffffff; +} +static inline u32 host1x_uclass_wait_syncpt_base_r(void) +{ + return 0x9; +} +static inline u32 host1x_uclass_wait_syncpt_base_indx_s(void) +{ + return 8; +} +static inline u32 host1x_uclass_wait_syncpt_base_indx_f(u32 v) +{ + return (v & 0xff) << 24; +} +static inline u32 host1x_uclass_wait_syncpt_base_indx_m(void) +{ + return 0xff << 24; +} +static inline u32 host1x_uclass_wait_syncpt_base_indx_v(u32 r) +{ + return (r >> 24) & 0xff; +} +static inline u32 host1x_uclass_wait_syncpt_base_base_indx_s(void) +{ + return 8; +} +static inline u32 host1x_uclass_wait_syncpt_base_base_indx_f(u32 v) +{ + return (v & 0xff) << 16; +} +static inline u32 host1x_uclass_wait_syncpt_base_base_indx_m(void) +{ + return 0xff << 16; +} +static inline u32 host1x_uclass_wait_syncpt_base_base_indx_v(u32 r) +{ + return (r >> 16) & 0xff; +} +static inline u32 host1x_uclass_wait_syncpt_base_offset_s(void) +{ + return 16; +} +static inline u32 host1x_uclass_wait_syncpt_base_offset_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 host1x_uclass_wait_syncpt_base_offset_m(void) +{ + return 0xffff << 0; +} +static inline u32 host1x_uclass_wait_syncpt_base_offset_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 host1x_uclass_load_syncpt_base_r(void) +{ + return 0xb; +} +static inline u32 host1x_uclass_load_syncpt_base_base_indx_s(void) +{ + return 8; +} +static inline u32 host1x_uclass_load_syncpt_base_base_indx_f(u32 v) +{ + return (v & 0xff) << 24; +} +static inline u32 host1x_uclass_load_syncpt_base_base_indx_m(void) +{ + return 0xff << 24; +} +static inline u32 host1x_uclass_load_syncpt_base_base_indx_v(u32 r) +{ + return (r >> 24) & 0xff; +} +static inline u32 host1x_uclass_load_syncpt_base_value_s(void) +{ + return 24; +} +static inline u32 host1x_uclass_load_syncpt_base_value_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +static inline u32 host1x_uclass_load_syncpt_base_value_m(void) +{ + return 0xffffff << 0; +} +static inline u32 host1x_uclass_load_syncpt_base_value_v(u32 r) +{ + return (r >> 0) & 0xffffff; +} +static inline u32 host1x_uclass_incr_syncpt_base_r(void) +{ + return 0xc; +} +static inline u32 host1x_uclass_incr_syncpt_base_base_indx_s(void) +{ + return 8; +} +static inline u32 host1x_uclass_incr_syncpt_base_base_indx_f(u32 v) +{ + return (v & 0xff) << 24; +} +static inline u32 host1x_uclass_incr_syncpt_base_base_indx_m(void) +{ + return 0xff << 24; +} +static inline u32 host1x_uclass_incr_syncpt_base_base_indx_v(u32 r) +{ + return (r >> 24) & 0xff; +} +static inline u32 host1x_uclass_incr_syncpt_base_offset_s(void) +{ + return 24; +} +static inline u32 host1x_uclass_incr_syncpt_base_offset_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +static inline u32 host1x_uclass_incr_syncpt_base_offset_m(void) +{ + return 0xffffff << 0; +} +static inline u32 host1x_uclass_incr_syncpt_base_offset_v(u32 r) +{ + return (r >> 0) & 0xffffff; +} +static inline u32 host1x_uclass_indoff_r(void) +{ + return 0x2d; +} +static inline u32 host1x_uclass_indoff_indbe_s(void) +{ + return 4; +} +static inline u32 host1x_uclass_indoff_indbe_f(u32 v) +{ + return (v & 0xf) << 28; +} +static inline u32 host1x_uclass_indoff_indbe_m(void) +{ + return 0xf << 28; +} +static inline u32 host1x_uclass_indoff_indbe_v(u32 r) +{ + return (r >> 28) & 0xf; +} +static inline u32 host1x_uclass_indoff_autoinc_s(void) +{ + return 1; +} +static inline u32 host1x_uclass_indoff_autoinc_f(u32 v) +{ + return (v & 0x1) << 27; +} +static inline u32 host1x_uclass_indoff_autoinc_m(void) +{ + return 0x1 << 27; +} +static inline u32 host1x_uclass_indoff_autoinc_v(u32 r) +{ + return (r >> 27) & 0x1; +} +static inline u32 host1x_uclass_indoff_spool_s(void) +{ + return 1; +} +static inline u32 host1x_uclass_indoff_spool_f(u32 v) +{ + return (v & 0x1) << 26; +} +static inline u32 host1x_uclass_indoff_spool_m(void) +{ + return 0x1 << 26; +} +static inline u32 host1x_uclass_indoff_spool_v(u32 r) +{ + return (r >> 26) & 0x1; +} +static inline u32 host1x_uclass_indoff_indoffset_s(void) +{ + return 24; +} +static inline u32 host1x_uclass_indoff_indoffset_f(u32 v) +{ + return (v & 0xffffff) << 2; +} +static inline u32 host1x_uclass_indoff_indoffset_m(void) +{ + return 0xffffff << 2; +} +static inline u32 host1x_uclass_indoff_indoffset_v(u32 r) +{ + return (r >> 2) & 0xffffff; +} +static inline u32 host1x_uclass_indoff_indmodid_s(void) +{ + return 8; +} +static inline u32 host1x_uclass_indoff_indmodid_f(u32 v) +{ + return (v & 0xff) << 18; +} +static inline u32 host1x_uclass_indoff_indmodid_m(void) +{ + return 0xff << 18; +} +static inline u32 host1x_uclass_indoff_indmodid_v(u32 r) +{ + return (r >> 18) & 0xff; +} +static inline u32 host1x_uclass_indoff_indmodid_host1x_v(void) +{ + return 0; +} +static inline u32 host1x_uclass_indoff_indmodid_mpe_v(void) +{ + return 1; +} +static inline u32 host1x_uclass_indoff_indmodid_vi_v(void) +{ + return 2; +} +static inline u32 host1x_uclass_indoff_indmodid_epp_v(void) +{ + return 3; +} +static inline u32 host1x_uclass_indoff_indmodid_isp_v(void) +{ + return 4; +} +static inline u32 host1x_uclass_indoff_indmodid_gr2d_v(void) +{ + return 5; +} +static inline u32 host1x_uclass_indoff_indmodid_gr3d_v(void) +{ + return 6; +} +static inline u32 host1x_uclass_indoff_indmodid_display_v(void) +{ + return 8; +} +static inline u32 host1x_uclass_indoff_indmodid_tvo_v(void) +{ + return 11; +} +static inline u32 host1x_uclass_indoff_indmodid_displayb_v(void) +{ + return 9; +} +static inline u32 host1x_uclass_indoff_indmodid_dsi_v(void) +{ + return 12; +} +static inline u32 host1x_uclass_indoff_indmodid_hdmi_v(void) +{ + return 10; +} +static inline u32 host1x_uclass_indoff_indmodid_dsib_v(void) +{ + return 16; +} +static inline u32 host1x_uclass_indoff_indroffset_s(void) +{ + return 16; +} +static inline u32 host1x_uclass_indoff_indroffset_f(u32 v) +{ + return (v & 0xffff) << 2; +} +static inline u32 host1x_uclass_indoff_indroffset_m(void) +{ + return 0xffff << 2; +} +static inline u32 host1x_uclass_indoff_indroffset_v(u32 r) +{ + return (r >> 2) & 0xffff; +} +static inline u32 host1x_uclass_indoff_acctype_s(void) +{ + return 1; +} +static inline u32 host1x_uclass_indoff_acctype_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 host1x_uclass_indoff_acctype_m(void) +{ + return 0x1 << 1; +} +static inline u32 host1x_uclass_indoff_acctype_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 host1x_uclass_indoff_acctype_reg_v(void) +{ + return 0; +} +static inline u32 host1x_uclass_indoff_acctype_fb_v(void) +{ + return 1; +} +static inline u32 host1x_uclass_indoff_rwn_s(void) +{ + return 1; +} +static inline u32 host1x_uclass_indoff_rwn_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 host1x_uclass_indoff_rwn_m(void) +{ + return 0x1 << 0; +} +static inline u32 host1x_uclass_indoff_rwn_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 host1x_uclass_indoff_rwn_write_v(void) +{ + return 0; +} +static inline u32 host1x_uclass_indoff_rwn_read_v(void) +{ + return 1; +} +static inline u32 host1x_uclass_inddata_r(void) +{ + return 0x2e; +} + +#endif /* __hw_host1x_uclass_host1x_h__ */ diff --git a/drivers/video/tegra/host/host1x/hw_host1x_channel.h b/drivers/video/tegra/host/host1x/hw_host1x_channel.h deleted file mode 100644 index ca2f9a0778cd..000000000000 --- a/drivers/video/tegra/host/host1x/hw_host1x_channel.h +++ /dev/null @@ -1,182 +0,0 @@ -/* - * drivers/video/tegra/host/host1x/hw_host1x_channel_host1x.h - * - * Copyright (c) 2012, NVIDIA Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - * - */ - - /* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ - -#ifndef __hw_host1x_channel_host1x_h__ -#define __hw_host1x_channel_host1x_h__ -/*This file is autogenerated. Do not edit. */ - -static inline u32 host1x_channel_fifostat_r(void) -{ - return 0x0; -} -static inline u32 host1x_channel_fifostat_cfempty_s(void) -{ - return 1; -} -static inline u32 host1x_channel_fifostat_cfempty_f(u32 v) -{ - return (v & 0x1) << 10; -} -static inline u32 host1x_channel_fifostat_cfempty_m(void) -{ - return 0x1 << 10; -} -static inline u32 host1x_channel_fifostat_cfempty_v(u32 r) -{ - return (r >> 10) & 0x1; -} -static inline u32 host1x_channel_fifostat_cfempty_notempty_v(void) -{ - return 0; -} -static inline u32 host1x_channel_fifostat_cfempty_empty_v(void) -{ - return 1; -} -static inline u32 host1x_channel_fifostat_outfentries_s(void) -{ - return 5; -} -static inline u32 host1x_channel_fifostat_outfentries_f(u32 v) -{ - return (v & 0x1f) << 24; -} -static inline u32 host1x_channel_fifostat_outfentries_m(void) -{ - return 0x1f << 24; -} -static inline u32 host1x_channel_fifostat_outfentries_v(u32 r) -{ - return (r >> 24) & 0x1f; -} -static inline u32 host1x_channel_inddata_r(void) -{ - return 0xc; -} -static inline u32 host1x_channel_dmastart_r(void) -{ - return 0x14; -} -static inline u32 host1x_channel_dmaput_r(void) -{ - return 0x18; -} -static inline u32 host1x_channel_dmaget_r(void) -{ - return 0x1c; -} -static inline u32 host1x_channel_dmaend_r(void) -{ - return 0x20; -} -static inline u32 host1x_channel_dmactrl_r(void) -{ - return 0x24; -} -static inline u32 host1x_channel_dmactrl_dmastop_s(void) -{ - return 1; -} -static inline u32 host1x_channel_dmactrl_dmastop_f(u32 v) -{ - return (v & 0x1) << 0; -} -static inline u32 host1x_channel_dmactrl_dmastop_m(void) -{ - return 0x1 << 0; -} -static inline u32 host1x_channel_dmactrl_dmastop_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 host1x_channel_dmactrl_dmastop_run_v(void) -{ - return 0; -} -static inline u32 host1x_channel_dmactrl_dmastop_stop_v(void) -{ - return 1; -} -static inline u32 host1x_channel_dmactrl_dmagetrst_s(void) -{ - return 1; -} -static inline u32 host1x_channel_dmactrl_dmagetrst_f(u32 v) -{ - return (v & 0x1) << 1; -} -static inline u32 host1x_channel_dmactrl_dmagetrst_m(void) -{ - return 0x1 << 1; -} -static inline u32 host1x_channel_dmactrl_dmagetrst_v(u32 r) -{ - return (r >> 1) & 0x1; -} -static inline u32 host1x_channel_dmactrl_dmainitget_s(void) -{ - return 1; -} -static inline u32 host1x_channel_dmactrl_dmainitget_f(u32 v) -{ - return (v & 0x1) << 2; -} -static inline u32 host1x_channel_dmactrl_dmainitget_m(void) -{ - return 0x1 << 2; -} -static inline u32 host1x_channel_dmactrl_dmainitget_v(u32 r) -{ - return (r >> 2) & 0x1; -} - -#endif /* __hw_host1x_channel_host1x_h__ */ diff --git a/drivers/video/tegra/host/host1x/hw_host1x_sync.h b/drivers/video/tegra/host/host1x/hw_host1x_sync.h deleted file mode 100644 index 67f0cbfb85b9..000000000000 --- a/drivers/video/tegra/host/host1x/hw_host1x_sync.h +++ /dev/null @@ -1,398 +0,0 @@ -/* - * drivers/video/tegra/host/host1x/hw_host1x_sync_host1x.h - * - * Copyright (c) 2012, NVIDIA Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - * - */ - - /* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ - -#ifndef __hw_host1x_sync_host1x_h__ -#define __hw_host1x_sync_host1x_h__ -/*This file is autogenerated. Do not edit. */ - -static inline u32 host1x_sync_intmask_r(void) -{ - return 0x4; -} -static inline u32 host1x_sync_intc0mask_r(void) -{ - return 0x8; -} -static inline u32 host1x_sync_hintstatus_r(void) -{ - return 0x20; -} -static inline u32 host1x_sync_hintmask_r(void) -{ - return 0x24; -} -static inline u32 host1x_sync_hintstatus_ext_r(void) -{ - return 0x28; -} -static inline u32 host1x_sync_hintstatus_ext_ip_read_int_s(void) -{ - return 1; -} -static inline u32 host1x_sync_hintstatus_ext_ip_read_int_f(u32 v) -{ - return (v & 0x1) << 30; -} -static inline u32 host1x_sync_hintstatus_ext_ip_read_int_m(void) -{ - return 0x1 << 30; -} -static inline u32 host1x_sync_hintstatus_ext_ip_read_int_v(u32 r) -{ - return (r >> 30) & 0x1; -} -static inline u32 host1x_sync_hintstatus_ext_ip_write_int_s(void) -{ - return 1; -} -static inline u32 host1x_sync_hintstatus_ext_ip_write_int_f(u32 v) -{ - return (v & 0x1) << 31; -} -static inline u32 host1x_sync_hintstatus_ext_ip_write_int_m(void) -{ - return 0x1 << 31; -} -static inline u32 host1x_sync_hintstatus_ext_ip_write_int_v(u32 r) -{ - return (r >> 31) & 0x1; -} -static inline u32 host1x_sync_hintmask_ext_r(void) -{ - return 0x2c; -} -static inline u32 host1x_sync_syncpt_thresh_cpu0_int_status_r(void) -{ - return 0x40; -} -static inline u32 host1x_sync_syncpt_thresh_cpu1_int_status_r(void) -{ - return 0x48; -} -static inline u32 host1x_sync_syncpt_thresh_int_disable_r(void) -{ - return 0x60; -} -static inline u32 host1x_sync_syncpt_thresh_int_enable_cpu0_r(void) -{ - return 0x68; -} -static inline u32 host1x_sync_cf0_setup_r(void) -{ - return 0x80; -} -static inline u32 host1x_sync_cf0_setup_cf0_base_s(void) -{ - return 9; -} -static inline u32 host1x_sync_cf0_setup_cf0_base_f(u32 v) -{ - return (v & 0x1ff) << 0; -} -static inline u32 host1x_sync_cf0_setup_cf0_base_m(void) -{ - return 0x1ff << 0; -} -static inline u32 host1x_sync_cf0_setup_cf0_base_v(u32 r) -{ - return (r >> 0) & 0x1ff; -} -static inline u32 host1x_sync_cf0_setup_cf0_limit_s(void) -{ - return 9; -} -static inline u32 host1x_sync_cf0_setup_cf0_limit_f(u32 v) -{ - return (v & 0x1ff) << 16; -} -static inline u32 host1x_sync_cf0_setup_cf0_limit_m(void) -{ - return 0x1ff << 16; -} -static inline u32 host1x_sync_cf0_setup_cf0_limit_v(u32 r) -{ - return (r >> 16) & 0x1ff; -} -static inline u32 host1x_sync_cmdproc_stop_r(void) -{ - return 0xac; -} -static inline u32 host1x_sync_ch_teardown_r(void) -{ - return 0xb0; -} -static inline u32 host1x_sync_usec_clk_r(void) -{ - return 0x1a4; -} -static inline u32 host1x_sync_ctxsw_timeout_cfg_r(void) -{ - return 0x1a8; -} -static inline u32 host1x_sync_ip_busy_timeout_r(void) -{ - return 0x1bc; -} -static inline u32 host1x_sync_ip_read_timeout_addr_r(void) -{ - return 0x1c0; -} -static inline u32 host1x_sync_ip_write_timeout_addr_r(void) -{ - return 0x1c4; -} -static inline u32 host1x_sync_mlock_0_r(void) -{ - return 0x2c0; -} -static inline u32 host1x_sync_mlock_owner_0_r(void) -{ - return 0x340; -} -static inline u32 host1x_sync_mlock_owner_0_mlock_owner_chid_0_s(void) -{ - return 4; -} -static inline u32 host1x_sync_mlock_owner_0_mlock_owner_chid_0_f(u32 v) -{ - return (v & 0xf) << 8; -} -static inline u32 host1x_sync_mlock_owner_0_mlock_owner_chid_0_m(void) -{ - return 0xf << 8; -} -static inline u32 host1x_sync_mlock_owner_0_mlock_owner_chid_0_v(u32 r) -{ - return (r >> 8) & 0xf; -} -static inline u32 host1x_sync_mlock_owner_0_mlock_cpu_owns_0_s(void) -{ - return 1; -} -static inline u32 host1x_sync_mlock_owner_0_mlock_cpu_owns_0_f(u32 v) -{ - return (v & 0x1) << 1; -} -static inline u32 host1x_sync_mlock_owner_0_mlock_cpu_owns_0_m(void) -{ - return 0x1 << 1; -} -static inline u32 host1x_sync_mlock_owner_0_mlock_cpu_owns_0_v(u32 r) -{ - return (r >> 1) & 0x1; -} -static inline u32 host1x_sync_mlock_owner_0_mlock_ch_owns_0_s(void) -{ - return 1; -} -static inline u32 host1x_sync_mlock_owner_0_mlock_ch_owns_0_f(u32 v) -{ - return (v & 0x1) << 0; -} -static inline u32 host1x_sync_mlock_owner_0_mlock_ch_owns_0_m(void) -{ - return 0x1 << 0; -} -static inline u32 host1x_sync_mlock_owner_0_mlock_ch_owns_0_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 host1x_sync_syncpt_0_r(void) -{ - return 0x400; -} -static inline u32 host1x_sync_syncpt_int_thresh_0_r(void) -{ - return 0x500; -} -static inline u32 host1x_sync_syncpt_base_0_r(void) -{ - return 0x600; -} -static inline u32 host1x_sync_syncpt_cpu_incr_r(void) -{ - return 0x700; -} -static inline u32 host1x_sync_cbread0_r(void) -{ - return 0x720; -} -static inline u32 host1x_sync_cfpeek_ctrl_r(void) -{ - return 0x74c; -} -static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_addr_s(void) -{ - return 9; -} -static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_addr_f(u32 v) -{ - return (v & 0x1ff) << 0; -} -static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_addr_m(void) -{ - return 0x1ff << 0; -} -static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_addr_v(u32 r) -{ - return (r >> 0) & 0x1ff; -} -static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_channr_s(void) -{ - return 3; -} -static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_channr_f(u32 v) -{ - return (v & 0x7) << 16; -} -static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_channr_m(void) -{ - return 0x7 << 16; -} -static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_channr_v(u32 r) -{ - return (r >> 16) & 0x7; -} -static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_ena_s(void) -{ - return 1; -} -static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_ena_f(u32 v) -{ - return (v & 0x1) << 31; -} -static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_ena_m(void) -{ - return 0x1 << 31; -} -static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_ena_v(u32 r) -{ - return (r >> 31) & 0x1; -} -static inline u32 host1x_sync_cfpeek_read_r(void) -{ - return 0x750; -} -static inline u32 host1x_sync_cfpeek_ptrs_r(void) -{ - return 0x754; -} -static inline u32 host1x_sync_cfpeek_ptrs_cf_rd_ptr_s(void) -{ - return 9; -} -static inline u32 host1x_sync_cfpeek_ptrs_cf_rd_ptr_f(u32 v) -{ - return (v & 0x1ff) << 0; -} -static inline u32 host1x_sync_cfpeek_ptrs_cf_rd_ptr_m(void) -{ - return 0x1ff << 0; -} -static inline u32 host1x_sync_cfpeek_ptrs_cf_rd_ptr_v(u32 r) -{ - return (r >> 0) & 0x1ff; -} -static inline u32 host1x_sync_cfpeek_ptrs_cf_wr_ptr_s(void) -{ - return 9; -} -static inline u32 host1x_sync_cfpeek_ptrs_cf_wr_ptr_f(u32 v) -{ - return (v & 0x1ff) << 16; -} -static inline u32 host1x_sync_cfpeek_ptrs_cf_wr_ptr_m(void) -{ - return 0x1ff << 16; -} -static inline u32 host1x_sync_cfpeek_ptrs_cf_wr_ptr_v(u32 r) -{ - return (r >> 16) & 0x1ff; -} -static inline u32 host1x_sync_cbstat_0_r(void) -{ - return 0x758; -} -static inline u32 host1x_sync_cbstat_0_cboffset0_s(void) -{ - return 16; -} -static inline u32 host1x_sync_cbstat_0_cboffset0_f(u32 v) -{ - return (v & 0xffff) << 0; -} -static inline u32 host1x_sync_cbstat_0_cboffset0_m(void) -{ - return 0xffff << 0; -} -static inline u32 host1x_sync_cbstat_0_cboffset0_v(u32 r) -{ - return (r >> 0) & 0xffff; -} -static inline u32 host1x_sync_cbstat_0_cbclass0_s(void) -{ - return 10; -} -static inline u32 host1x_sync_cbstat_0_cbclass0_f(u32 v) -{ - return (v & 0x3ff) << 16; -} -static inline u32 host1x_sync_cbstat_0_cbclass0_m(void) -{ - return 0x3ff << 16; -} -static inline u32 host1x_sync_cbstat_0_cbclass0_v(u32 r) -{ - return (r >> 16) & 0x3ff; -} - -#endif /* __hw_host1x_sync_host1x_h__ */ diff --git a/drivers/video/tegra/host/host1x/hw_host1x_uclass.h b/drivers/video/tegra/host/host1x/hw_host1x_uclass.h deleted file mode 100644 index ed6e4b706ab9..000000000000 --- a/drivers/video/tegra/host/host1x/hw_host1x_uclass.h +++ /dev/null @@ -1,474 +0,0 @@ -/* - * drivers/video/tegra/host/host1x/hw_host1x_uclass_host1x.h - * - * Copyright (c) 2012, NVIDIA Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - * - */ - - /* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ - -#ifndef __hw_host1x_uclass_host1x_h__ -#define __hw_host1x_uclass_host1x_h__ -/*This file is autogenerated. Do not edit. */ - -static inline u32 host1x_uclass_incr_syncpt_r(void) -{ - return 0x0; -} -static inline u32 host1x_uclass_incr_syncpt_cond_s(void) -{ - return 8; -} -static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v) -{ - return (v & 0xff) << 8; -} -static inline u32 host1x_uclass_incr_syncpt_cond_m(void) -{ - return 0xff << 8; -} -static inline u32 host1x_uclass_incr_syncpt_cond_v(u32 r) -{ - return (r >> 8) & 0xff; -} -static inline u32 host1x_uclass_incr_syncpt_cond_immediate_v(void) -{ - return 0; -} -static inline u32 host1x_uclass_incr_syncpt_cond_op_done_v(void) -{ - return 1; -} -static inline u32 host1x_uclass_incr_syncpt_cond_rd_done_v(void) -{ - return 2; -} -static inline u32 host1x_uclass_incr_syncpt_cond_reg_wr_safe_v(void) -{ - return 3; -} -static inline u32 host1x_uclass_incr_syncpt_indx_s(void) -{ - return 8; -} -static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v) -{ - return (v & 0xff) << 0; -} -static inline u32 host1x_uclass_incr_syncpt_indx_m(void) -{ - return 0xff << 0; -} -static inline u32 host1x_uclass_incr_syncpt_indx_v(u32 r) -{ - return (r >> 0) & 0xff; -} -static inline u32 host1x_uclass_wait_syncpt_r(void) -{ - return 0x8; -} -static inline u32 host1x_uclass_wait_syncpt_indx_s(void) -{ - return 8; -} -static inline u32 host1x_uclass_wait_syncpt_indx_f(u32 v) -{ - return (v & 0xff) << 24; -} -static inline u32 host1x_uclass_wait_syncpt_indx_m(void) -{ - return 0xff << 24; -} -static inline u32 host1x_uclass_wait_syncpt_indx_v(u32 r) -{ - return (r >> 24) & 0xff; -} -static inline u32 host1x_uclass_wait_syncpt_thresh_s(void) -{ - return 24; -} -static inline u32 host1x_uclass_wait_syncpt_thresh_f(u32 v) -{ - return (v & 0xffffff) << 0; -} -static inline u32 host1x_uclass_wait_syncpt_thresh_m(void) -{ - return 0xffffff << 0; -} -static inline u32 host1x_uclass_wait_syncpt_thresh_v(u32 r) -{ - return (r >> 0) & 0xffffff; -} -static inline u32 host1x_uclass_wait_syncpt_base_r(void) -{ - return 0x9; -} -static inline u32 host1x_uclass_wait_syncpt_base_indx_s(void) -{ - return 8; -} -static inline u32 host1x_uclass_wait_syncpt_base_indx_f(u32 v) -{ - return (v & 0xff) << 24; -} -static inline u32 host1x_uclass_wait_syncpt_base_indx_m(void) -{ - return 0xff << 24; -} -static inline u32 host1x_uclass_wait_syncpt_base_indx_v(u32 r) -{ - return (r >> 24) & 0xff; -} -static inline u32 host1x_uclass_wait_syncpt_base_base_indx_s(void) -{ - return 8; -} -static inline u32 host1x_uclass_wait_syncpt_base_base_indx_f(u32 v) -{ - return (v & 0xff) << 16; -} -static inline u32 host1x_uclass_wait_syncpt_base_base_indx_m(void) -{ - return 0xff << 16; -} -static inline u32 host1x_uclass_wait_syncpt_base_base_indx_v(u32 r) -{ - return (r >> 16) & 0xff; -} -static inline u32 host1x_uclass_wait_syncpt_base_offset_s(void) -{ - return 16; -} -static inline u32 host1x_uclass_wait_syncpt_base_offset_f(u32 v) -{ - return (v & 0xffff) << 0; -} -static inline u32 host1x_uclass_wait_syncpt_base_offset_m(void) -{ - return 0xffff << 0; -} -static inline u32 host1x_uclass_wait_syncpt_base_offset_v(u32 r) -{ - return (r >> 0) & 0xffff; -} -static inline u32 host1x_uclass_load_syncpt_base_r(void) -{ - return 0xb; -} -static inline u32 host1x_uclass_load_syncpt_base_base_indx_s(void) -{ - return 8; -} -static inline u32 host1x_uclass_load_syncpt_base_base_indx_f(u32 v) -{ - return (v & 0xff) << 24; -} -static inline u32 host1x_uclass_load_syncpt_base_base_indx_m(void) -{ - return 0xff << 24; -} -static inline u32 host1x_uclass_load_syncpt_base_base_indx_v(u32 r) -{ - return (r >> 24) & 0xff; -} -static inline u32 host1x_uclass_load_syncpt_base_value_s(void) -{ - return 24; -} -static inline u32 host1x_uclass_load_syncpt_base_value_f(u32 v) -{ - return (v & 0xffffff) << 0; -} -static inline u32 host1x_uclass_load_syncpt_base_value_m(void) -{ - return 0xffffff << 0; -} -static inline u32 host1x_uclass_load_syncpt_base_value_v(u32 r) -{ - return (r >> 0) & 0xffffff; -} -static inline u32 host1x_uclass_incr_syncpt_base_r(void) -{ - return 0xc; -} -static inline u32 host1x_uclass_incr_syncpt_base_base_indx_s(void) -{ - return 8; -} -static inline u32 host1x_uclass_incr_syncpt_base_base_indx_f(u32 v) -{ - return (v & 0xff) << 24; -} -static inline u32 host1x_uclass_incr_syncpt_base_base_indx_m(void) -{ - return 0xff << 24; -} -static inline u32 host1x_uclass_incr_syncpt_base_base_indx_v(u32 r) -{ - return (r >> 24) & 0xff; -} -static inline u32 host1x_uclass_incr_syncpt_base_offset_s(void) -{ - return 24; -} -static inline u32 host1x_uclass_incr_syncpt_base_offset_f(u32 v) -{ - return (v & 0xffffff) << 0; -} -static inline u32 host1x_uclass_incr_syncpt_base_offset_m(void) -{ - return 0xffffff << 0; -} -static inline u32 host1x_uclass_incr_syncpt_base_offset_v(u32 r) -{ - return (r >> 0) & 0xffffff; -} -static inline u32 host1x_uclass_indoff_r(void) -{ - return 0x2d; -} -static inline u32 host1x_uclass_indoff_indbe_s(void) -{ - return 4; -} -static inline u32 host1x_uclass_indoff_indbe_f(u32 v) -{ - return (v & 0xf) << 28; -} -static inline u32 host1x_uclass_indoff_indbe_m(void) -{ - return 0xf << 28; -} -static inline u32 host1x_uclass_indoff_indbe_v(u32 r) -{ - return (r >> 28) & 0xf; -} -static inline u32 host1x_uclass_indoff_autoinc_s(void) -{ - return 1; -} -static inline u32 host1x_uclass_indoff_autoinc_f(u32 v) -{ - return (v & 0x1) << 27; -} -static inline u32 host1x_uclass_indoff_autoinc_m(void) -{ - return 0x1 << 27; -} -static inline u32 host1x_uclass_indoff_autoinc_v(u32 r) -{ - return (r >> 27) & 0x1; -} -static inline u32 host1x_uclass_indoff_spool_s(void) -{ - return 1; -} -static inline u32 host1x_uclass_indoff_spool_f(u32 v) -{ - return (v & 0x1) << 26; -} -static inline u32 host1x_uclass_indoff_spool_m(void) -{ - return 0x1 << 26; -} -static inline u32 host1x_uclass_indoff_spool_v(u32 r) -{ - return (r >> 26) & 0x1; -} -static inline u32 host1x_uclass_indoff_indoffset_s(void) -{ - return 24; -} -static inline u32 host1x_uclass_indoff_indoffset_f(u32 v) -{ - return (v & 0xffffff) << 2; -} -static inline u32 host1x_uclass_indoff_indoffset_m(void) -{ - return 0xffffff << 2; -} -static inline u32 host1x_uclass_indoff_indoffset_v(u32 r) -{ - return (r >> 2) & 0xffffff; -} -static inline u32 host1x_uclass_indoff_indmodid_s(void) -{ - return 8; -} -static inline u32 host1x_uclass_indoff_indmodid_f(u32 v) -{ - return (v & 0xff) << 18; -} -static inline u32 host1x_uclass_indoff_indmodid_m(void) -{ - return 0xff << 18; -} -static inline u32 host1x_uclass_indoff_indmodid_v(u32 r) -{ - return (r >> 18) & 0xff; -} -static inline u32 host1x_uclass_indoff_indmodid_host1x_v(void) -{ - return 0; -} -static inline u32 host1x_uclass_indoff_indmodid_mpe_v(void) -{ - return 1; -} -static inline u32 host1x_uclass_indoff_indmodid_vi_v(void) -{ - return 2; -} -static inline u32 host1x_uclass_indoff_indmodid_epp_v(void) -{ - return 3; -} -static inline u32 host1x_uclass_indoff_indmodid_isp_v(void) -{ - return 4; -} -static inline u32 host1x_uclass_indoff_indmodid_gr2d_v(void) -{ - return 5; -} -static inline u32 host1x_uclass_indoff_indmodid_gr3d_v(void) -{ - return 6; -} -static inline u32 host1x_uclass_indoff_indmodid_display_v(void) -{ - return 8; -} -static inline u32 host1x_uclass_indoff_indmodid_tvo_v(void) -{ - return 11; -} -static inline u32 host1x_uclass_indoff_indmodid_displayb_v(void) -{ - return 9; -} -static inline u32 host1x_uclass_indoff_indmodid_dsi_v(void) -{ - return 12; -} -static inline u32 host1x_uclass_indoff_indmodid_hdmi_v(void) -{ - return 10; -} -static inline u32 host1x_uclass_indoff_indmodid_dsib_v(void) -{ - return 16; -} -static inline u32 host1x_uclass_indoff_indroffset_s(void) -{ - return 16; -} -static inline u32 host1x_uclass_indoff_indroffset_f(u32 v) -{ - return (v & 0xffff) << 2; -} -static inline u32 host1x_uclass_indoff_indroffset_m(void) -{ - return 0xffff << 2; -} -static inline u32 host1x_uclass_indoff_indroffset_v(u32 r) -{ - return (r >> 2) & 0xffff; -} -static inline u32 host1x_uclass_indoff_acctype_s(void) -{ - return 1; -} -static inline u32 host1x_uclass_indoff_acctype_f(u32 v) -{ - return (v & 0x1) << 1; -} -static inline u32 host1x_uclass_indoff_acctype_m(void) -{ - return 0x1 << 1; -} -static inline u32 host1x_uclass_indoff_acctype_v(u32 r) -{ - return (r >> 1) & 0x1; -} -static inline u32 host1x_uclass_indoff_acctype_reg_v(void) -{ - return 0; -} -static inline u32 host1x_uclass_indoff_acctype_fb_v(void) -{ - return 1; -} -static inline u32 host1x_uclass_indoff_rwn_s(void) -{ - return 1; -} -static inline u32 host1x_uclass_indoff_rwn_f(u32 v) -{ - return (v & 0x1) << 0; -} -static inline u32 host1x_uclass_indoff_rwn_m(void) -{ - return 0x1 << 0; -} -static inline u32 host1x_uclass_indoff_rwn_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 host1x_uclass_indoff_rwn_write_v(void) -{ - return 0; -} -static inline u32 host1x_uclass_indoff_rwn_read_v(void) -{ - return 1; -} -static inline u32 host1x_uclass_inddata_r(void) -{ - return 0x2e; -} - -#endif /* __hw_host1x_uclass_host1x_h__ */ diff --git a/drivers/video/tegra/host/mpe/mpe.c b/drivers/video/tegra/host/mpe/mpe.c index 7b76393de6c6..e47c1029a3c5 100644 --- a/drivers/video/tegra/host/mpe/mpe.c +++ b/drivers/video/tegra/host/mpe/mpe.c @@ -21,9 +21,7 @@ #include "nvhost_hwctx.h" #include "nvhost_channel.h" #include "dev.h" -#include "host1x/host1x_hardware.h" -#include "host1x/host1x_channel.h" -#include "host1x/host1x_syncpt.h" +#include "host1x/host1x01_hardware.h" #include "host1x/host1x_hwctx.h" #include "t20/t20.h" #include "chip_support.h" diff --git a/drivers/video/tegra/host/t20/t20.c b/drivers/video/tegra/host/t20/t20.c index 1f8f14394b67..00c1e2825920 100644 --- a/drivers/video/tegra/host/t20/t20.c +++ b/drivers/video/tegra/host/t20/t20.c @@ -18,24 +18,18 @@ * along with this program. If not, see . */ -#include #include #include #include #include "t20.h" -#include "host1x/host1x_syncpt.h" -#include "host1x/host1x_hardware.h" -#include "gr3d/gr3d.h" #include "gr3d/gr3d_t20.h" #include "mpe/mpe.h" #include "host1x/host1x.h" -#include "nvhost_hwctx.h" #include "nvhost_channel.h" -#include "host1x/host1x_channel.h" -#include "host1x/host1x_cdma.h" -#include "chip_support.h" -#include "nvmap.h" #include "nvhost_memmgr.h" +#include "host1x/host1x01_hardware.h" +#include "host1x/host1x_syncpt.h" +#include "chip_support.h" #define NVMODMUTEX_2D_FULL (1) #define NVMODMUTEX_2D_SIMPLE (2) @@ -251,55 +245,6 @@ int tegra2_register_host1x_devices(void) return nvhost_add_devices(t20_devices, ARRAY_SIZE(t20_devices)); } -static inline void __iomem *t20_channel_aperture(void __iomem *p, int ndx) -{ - p += ndx * NV_HOST1X_CHANNEL_MAP_SIZE_BYTES; - return p; -} - -static inline int t20_nvhost_hwctx_handler_init(struct nvhost_channel *ch) -{ - int err = 0; - unsigned long syncpts = ch->dev->syncpts; - unsigned long waitbases = ch->dev->waitbases; - u32 syncpt = find_first_bit(&syncpts, BITS_PER_LONG); - u32 waitbase = find_first_bit(&waitbases, BITS_PER_LONG); - struct nvhost_driver *drv = to_nvhost_driver(ch->dev->dev.driver); - - if (drv->alloc_hwctx_handler) { - ch->ctxhandler = drv->alloc_hwctx_handler(syncpt, - waitbase, ch); - if (!ch->ctxhandler) - err = -ENOMEM; - } - - return err; -} - -static int t20_channel_init(struct nvhost_channel *ch, - struct nvhost_master *dev, int index) -{ - ch->chid = index; - mutex_init(&ch->reflock); - mutex_init(&ch->submitlock); - - ch->aperture = t20_channel_aperture(dev->aperture, index); - - return t20_nvhost_hwctx_handler_init(ch); -} - -int nvhost_init_t20_channel_support(struct nvhost_master *host, - struct nvhost_chip_support *op) -{ - op->channel.init = t20_channel_init; - op->channel.submit = host1x_channel_submit; - op->channel.read3dreg = host1x_channel_read_3d_reg; - op->channel.save_context = host1x_save_context; - op->channel.drain_read_fifo = host1x_drain_read_fifo; - - return 0; -} - static void t20_free_nvhost_channel(struct nvhost_channel *ch) { nvhost_free_channel_internal(ch, &t20_num_alloc_channels); @@ -313,28 +258,27 @@ static struct nvhost_channel *t20_alloc_nvhost_channel( &t20_num_alloc_channels); } +#include "host1x/host1x_channel.c" +#include "host1x/host1x_cdma.c" +#include "host1x/host1x_debug.c" +#include "host1x/host1x_syncpt.c" +#include "host1x/host1x_intr.c" + int nvhost_init_t20_support(struct nvhost_master *host, struct nvhost_chip_support *op) { int err; - /* don't worry about cleaning up on failure... "remove" does it. */ - err = nvhost_init_t20_channel_support(host, op); - if (err) - return err; - err = host1x_init_cdma_support(op); - if (err) - return err; - err = nvhost_init_t20_debug_support(op); - if (err) - return err; - err = host1x_init_syncpt_support(host, op); - if (err) - return err; - err = nvhost_init_t20_intr_support(op); + op->channel = host1x_channel_ops; + op->cdma = host1x_cdma_ops; + op->push_buffer = host1x_pushbuffer_ops; + op->debug = host1x_debug_ops; + host->sync_aperture = host->aperture + HOST1X_CHANNEL_SYNC_REG_BASE; + op->syncpt = host1x_syncpt_ops; + op->intr = host1x_intr_ops; + err = nvhost_memmgr_init(op); if (err) return err; - err = nvhost_memmgr_init(op); op->nvhost_dev.alloc_nvhost_channel = t20_alloc_nvhost_channel; op->nvhost_dev.free_nvhost_channel = t20_free_nvhost_channel; diff --git a/drivers/video/tegra/host/t20/t20.h b/drivers/video/tegra/host/t20/t20.h index 456d3ae1bc03..729f9d8e85e4 100644 --- a/drivers/video/tegra/host/t20/t20.h +++ b/drivers/video/tegra/host/t20/t20.h @@ -21,16 +21,9 @@ #define _NVHOST_T20_H_ struct nvhost_master; -struct nvhost_module; struct nvhost_chip_support; -int nvhost_init_t20_channel_support(struct nvhost_master *, - struct nvhost_chip_support *); -int nvhost_init_t20_debug_support(struct nvhost_chip_support *); -int nvhost_init_t20_syncpt_support(struct nvhost_master *); -int nvhost_init_t20_intr_support(struct nvhost_chip_support *); int nvhost_init_t20_support(struct nvhost_master *, struct nvhost_chip_support *); -int nvhost_t20_save_context(struct nvhost_module *mod, u32 syncpt_id); #endif /* _NVHOST_T20_H_ */ diff --git a/drivers/video/tegra/host/t30/t30.c b/drivers/video/tegra/host/t30/t30.c index b74c561c05aa..88a489244b48 100644 --- a/drivers/video/tegra/host/t30/t30.c +++ b/drivers/video/tegra/host/t30/t30.c @@ -18,24 +18,20 @@ * along with this program. If not, see . */ -#include #include #include #include #include "t20/t20.h" #include "t30.h" -#include "gr3d/gr3d.h" #include "gr3d/gr3d_t30.h" #include "gr3d/scale3d.h" #include "mpe/mpe.h" #include "host1x/host1x.h" -#include "host1x/host1x_hardware.h" -#include "host1x/host1x_syncpt.h" +#include "host1x/host1x01_hardware.h" #include "chip_support.h" #include "nvhost_channel.h" -#include "host1x/host1x_cdma.h" -#include "nvmap.h" #include "nvhost_memmgr.h" +#include "host1x/host1x_syncpt.h" #define NVMODMUTEX_2D_FULL (1) #define NVMODMUTEX_2D_SIMPLE (2) @@ -259,60 +255,6 @@ int tegra3_register_host1x_devices(void) return nvhost_add_devices(t30_devices, ARRAY_SIZE(t30_devices)); } -static inline int t30_nvhost_hwctx_handler_init(struct nvhost_channel *ch) -{ - int err = 0; - unsigned long syncpts = ch->dev->syncpts; - unsigned long waitbases = ch->dev->waitbases; - u32 syncpt = find_first_bit(&syncpts, BITS_PER_LONG); - u32 waitbase = find_first_bit(&waitbases, BITS_PER_LONG); - struct nvhost_driver *drv = to_nvhost_driver(ch->dev->dev.driver); - - if (drv->alloc_hwctx_handler) { - ch->ctxhandler = drv->alloc_hwctx_handler(syncpt, - waitbase, ch); - if (!ch->ctxhandler) - err = -ENOMEM; - } - - return err; -} - -static inline void __iomem *t30_channel_aperture(void __iomem *p, int ndx) -{ - p += ndx * NV_HOST1X_CHANNEL_MAP_SIZE_BYTES; - return p; -} - -static int t30_channel_init(struct nvhost_channel *ch, - struct nvhost_master *dev, int index) -{ - ch->chid = index; - mutex_init(&ch->reflock); - mutex_init(&ch->submitlock); - - ch->aperture = t30_channel_aperture(dev->aperture, index); - - return t30_nvhost_hwctx_handler_init(ch); -} - -int nvhost_init_t30_channel_support(struct nvhost_master *host, - struct nvhost_chip_support *op) -{ - int result = nvhost_init_t20_channel_support(host, op); - op->channel.init = t30_channel_init; - - return result; -} - -int nvhost_init_t30_debug_support(struct nvhost_chip_support *op) -{ - nvhost_init_t20_debug_support(op); - op->debug.debug_init = nvhost_scale3d_debug_init; - - return 0; -} - static void t30_free_nvhost_channel(struct nvhost_channel *ch) { nvhost_free_channel_internal(ch, &t30_num_alloc_channels); @@ -326,27 +268,25 @@ static struct nvhost_channel *t30_alloc_nvhost_channel( &t30_num_alloc_channels); } +#include "host1x/host1x_channel.c" +#include "host1x/host1x_cdma.c" +#include "host1x/host1x_debug.c" +#include "host1x/host1x_syncpt.c" +#include "host1x/host1x_intr.c" + int nvhost_init_t30_support(struct nvhost_master *host, struct nvhost_chip_support *op) { int err; - /* don't worry about cleaning up on failure... "remove" does it. */ - err = nvhost_init_t30_channel_support(host, op); - if (err) - return err; - err = host1x_init_cdma_support(op); - if (err) - return err; - err = nvhost_init_t30_debug_support(op); - if (err) - return err; - err = host1x_init_syncpt_support(host, op); - if (err) - return err; - err = nvhost_init_t20_intr_support(op); - if (err) - return err; + op->channel = host1x_channel_ops; + op->cdma = host1x_cdma_ops; + op->push_buffer = host1x_pushbuffer_ops; + op->debug = host1x_debug_ops; + op->debug.debug_init = nvhost_scale3d_debug_init; + host->sync_aperture = host->aperture + HOST1X_CHANNEL_SYNC_REG_BASE; + op->syncpt = host1x_syncpt_ops; + op->intr = host1x_intr_ops; err = nvhost_memmgr_init(op); if (err) return err; diff --git a/drivers/video/tegra/host/t30/t30.h b/drivers/video/tegra/host/t30/t30.h index e4db97b5613d..80838a5e287c 100644 --- a/drivers/video/tegra/host/t30/t30.h +++ b/drivers/video/tegra/host/t30/t30.h @@ -23,9 +23,6 @@ struct nvhost_master; struct nvhost_chip_support; -int nvhost_init_t30_channel_support(struct nvhost_master *, - struct nvhost_chip_support *); -int nvhost_init_t30_debug_support(struct nvhost_chip_support *); int nvhost_init_t30_support(struct nvhost_master *host, struct nvhost_chip_support *); -- cgit v1.2.3