From d6dbddcdad60a1572d4a29c7a92f12ee9f0555df Mon Sep 17 00:00:00 2001 From: Huang Shijie Date: Wed, 23 Apr 2014 11:59:26 +0800 Subject: ENGR00318895-6 Documentation: fsl-quadspi: update the document The patch updates the document by adding more information to describe the DT proporties used by the Freescale Quadspi driver and the childs nodes. For the child node for SPI NOR flash, we add the required property ("spi-max-frequency"), and refer to spi-nor-flash.txt for the optional properties. Signed-off-by: Huang Shijie (cherry picked from commit d7b296f51eb077b0c77580ad63ffd69ce722bf6c) --- Documentation/devicetree/bindings/mtd/fsl-quadspi.txt | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'Documentation/devicetree/bindings/mtd') diff --git a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt index c34aa6f8a424..951655466a11 100644 --- a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt +++ b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt @@ -1,5 +1,11 @@ * Freescale Quad Serial Peripheral Interface(QuadSPI) +The QuadSPI controller acts as the SPI master. It is described with a node +for the controller and a set of child nodes for each SPI NOR flash. + +Part I - The DT node for the controller: +------------------------------ + Required properties: - compatible : Should be "fsl,vf610-qspi", "fsl,imx6sx-qspi", "fsl,imx7d-qspi", "fsl,imx6ul-qspi", @@ -24,6 +30,16 @@ Optional properties: (Please check the board's schematic.) - big-endian : That means the IP register is big endian +Part II - The DT nodes for each SPI NOR flash +------------------------------ +Required properties: +- spi-max-frequency : Maximum frequency of the SPI bus the chip can operate at + +Optional properties: + Please refer to the Documentation/devicetree/bindings/mtd/spi-nor-flash.txt + If you set the "spi-nor,ddr-quad-read-dummy", it means you enable the DDR + quad read feature for the driver. + Example: qspi0: quadspi@40044000 { -- cgit v1.2.3