From 5de1540b7bc4c23470f86add1e517be41e7fefe2 Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Tue, 21 Jun 2011 10:59:34 -0600 Subject: drivers/amba: create devices from device tree Add a function to create amba_devices (i.e. primecell peripherals) from device tree nodes. The device tree scanning is done by the of_platform_populate() function which can call of_amba_device_create based on a match table entry. Nodes with a "arm,primecell-periphid" property can override the h/w peripheral id value. Based on the original work by Jeremy Kerr. Signed-off-by: Jeremy Kerr Acked-by: Linus Walleij Signed-off-by: Rob Herring Reviewed-by: Arnd Bergmann [grant.likely: add Jeremy's original s-o-b line, changes from review comments, and moved all code to drivers/of/platform.c] Signed-off-by: Grant Likely --- Documentation/devicetree/bindings/arm/primecell.txt | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/primecell.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/primecell.txt b/Documentation/devicetree/bindings/arm/primecell.txt new file mode 100644 index 000000000000..1d5d7a870ec7 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/primecell.txt @@ -0,0 +1,21 @@ +* ARM Primecell Peripherals + +ARM, Ltd. Primecell peripherals have a standard id register that can be used to +identify the peripheral type, vendor, and revision. This value can be used for +driver matching. + +Required properties: + +- compatible : should be a specific value for peripheral and "arm,primecell" + +Optional properties: + +- arm,primecell-periphid : Value to override the h/w value with + +Example: + +serial@fff36000 { + compatible = "arm,pl011", "arm,primecell"; + arm,primecell-periphid = <0x00341011>; +}; + -- cgit v1.2.3 From 61ab1a90d81b5b8a53fc221a3665715c61614fb7 Mon Sep 17 00:00:00 2001 From: Jamie Iles Date: Mon, 27 Jun 2011 13:32:33 +0100 Subject: dt: document the of_serial bindings The of_serial bindings can be used to register a number of serial devices. Document this binding with all of the others. v3: remove device-type and clarify used-by-rtas Signed-off-by: Jamie Iles Acked-by: Arnd Bergmann Signed-off-by: Grant Likely --- .../devicetree/bindings/tty/serial/of-serial.txt | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/tty/serial/of-serial.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/tty/serial/of-serial.txt b/Documentation/devicetree/bindings/tty/serial/of-serial.txt new file mode 100644 index 000000000000..35e53ae85eec --- /dev/null +++ b/Documentation/devicetree/bindings/tty/serial/of-serial.txt @@ -0,0 +1,33 @@ +* UART (Universal Asynchronous Receiver/Transmitter) + +Required properties: +- compatible : one of: + - "ns8250" + - "ns16450" + - "ns16550a" + - "ns16550" + - "ns16750" + - "ns16850" + - "nvidia,tegra250-uart" + - "ibm,qpace-nwp-serial" + - "serial" if the port type is unknown. +- reg : offset and length of the register set for the device. +- interrupts : should contain uart interrupt. +- clock-frequency : the input clock frequency for the UART. + +Optional properties: +- current-speed : the current active speed of the UART. +- reg-offset : offset to apply to the mapbase from the start of the registers. +- reg-shift : quantity to shift the register offsets by. +- used-by-rtas : set to indicate that the port is in use by the OpenFirmware + RTAS and should not be registered. + +Example: + + uart@80230000 { + compatible = "ns8250"; + reg = <0x80230000 0x100>; + clock-frequency = <3686400>; + interrupts = <10>; + reg-shift = <2>; + }; -- cgit v1.2.3 From 7423734e19e7e0a90e3379152eacca2647f4377e Mon Sep 17 00:00:00 2001 From: Jamie Iles Date: Mon, 27 Jun 2011 13:32:34 +0100 Subject: tty: of_serial: support for 32 bit accesses Some platforms e.g. TI Davinci require 32-bit accesses to the UARTs. The of_serial driver currently registers all UARTs as UPIO_MEM. Add a new attribute "reg-io-width" to allow the port to be registered with different IO width requirements. Acked-by: Alan Cox Signed-off-by: Jamie Iles Signed-off-by: Grant Likely --- Documentation/devicetree/bindings/tty/serial/of-serial.txt | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/tty/serial/of-serial.txt b/Documentation/devicetree/bindings/tty/serial/of-serial.txt index 35e53ae85eec..337a7e51faca 100644 --- a/Documentation/devicetree/bindings/tty/serial/of-serial.txt +++ b/Documentation/devicetree/bindings/tty/serial/of-serial.txt @@ -19,6 +19,9 @@ Optional properties: - current-speed : the current active speed of the UART. - reg-offset : offset to apply to the mapbase from the start of the registers. - reg-shift : quantity to shift the register offsets by. +- reg-io-width : the size (in bytes) of the IO accesses that should be + performed on the device. There are some systems that require 32-bit + accesses to the UART (e.g. TI davinci). - used-by-rtas : set to indicate that the port is in use by the OpenFirmware RTAS and should not be registered. -- cgit v1.2.3 From 5a9ebe959967b7d3579de2a53d5df470fe0c7f22 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Thu, 7 Jul 2011 14:43:12 -0500 Subject: dt: bindings: move SEC node under new crypto/ Since technically it's not powerpc arch-specific. Also rename it sec2 to differentiate it from its incompatible successor, the SEC 4. Signed-off-by: Kim Phillips Signed-off-by: Grant Likely --- .../devicetree/bindings/crypto/fsl-sec2.txt | 68 ++++++++++++++++++++++ .../devicetree/bindings/powerpc/fsl/sec.txt | 68 ---------------------- 2 files changed, 68 insertions(+), 68 deletions(-) create mode 100644 Documentation/devicetree/bindings/crypto/fsl-sec2.txt delete mode 100644 Documentation/devicetree/bindings/powerpc/fsl/sec.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec2.txt b/Documentation/devicetree/bindings/crypto/fsl-sec2.txt new file mode 100644 index 000000000000..38988ef1336b --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/fsl-sec2.txt @@ -0,0 +1,68 @@ +Freescale SoC SEC Security Engines versions 2.x-3.x + +Required properties: + +- compatible : Should contain entries for this and backward compatible + SEC versions, high to low, e.g., "fsl,sec2.1", "fsl,sec2.0" +- reg : Offset and length of the register set for the device +- interrupts : the SEC's interrupt number +- fsl,num-channels : An integer representing the number of channels + available. +- fsl,channel-fifo-len : An integer representing the number of + descriptor pointers each channel fetch fifo can hold. +- fsl,exec-units-mask : The bitmask representing what execution units + (EUs) are available. It's a single 32-bit cell. EU information + should be encoded following the SEC's Descriptor Header Dword + EU_SEL0 field documentation, i.e. as follows: + + bit 0 = reserved - should be 0 + bit 1 = set if SEC has the ARC4 EU (AFEU) + bit 2 = set if SEC has the DES/3DES EU (DEU) + bit 3 = set if SEC has the message digest EU (MDEU/MDEU-A) + bit 4 = set if SEC has the random number generator EU (RNG) + bit 5 = set if SEC has the public key EU (PKEU) + bit 6 = set if SEC has the AES EU (AESU) + bit 7 = set if SEC has the Kasumi EU (KEU) + bit 8 = set if SEC has the CRC EU (CRCU) + bit 11 = set if SEC has the message digest EU extended alg set (MDEU-B) + +remaining bits are reserved for future SEC EUs. + +- fsl,descriptor-types-mask : The bitmask representing what descriptors + are available. It's a single 32-bit cell. Descriptor type information + should be encoded following the SEC's Descriptor Header Dword DESC_TYPE + field documentation, i.e. as follows: + + bit 0 = set if SEC supports the aesu_ctr_nonsnoop desc. type + bit 1 = set if SEC supports the ipsec_esp descriptor type + bit 2 = set if SEC supports the common_nonsnoop desc. type + bit 3 = set if SEC supports the 802.11i AES ccmp desc. type + bit 4 = set if SEC supports the hmac_snoop_no_afeu desc. type + bit 5 = set if SEC supports the srtp descriptor type + bit 6 = set if SEC supports the non_hmac_snoop_no_afeu desc.type + bit 7 = set if SEC supports the pkeu_assemble descriptor type + bit 8 = set if SEC supports the aesu_key_expand_output desc.type + bit 9 = set if SEC supports the pkeu_ptmul descriptor type + bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type + bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type + + ..and so on and so forth. + +Optional properties: + +- interrupt-parent : the phandle for the interrupt controller that + services interrupts for this device. + +Example: + + /* MPC8548E */ + crypto@30000 { + compatible = "fsl,sec2.1", "fsl,sec2.0"; + reg = <0x30000 0x10000>; + interrupts = <29 2>; + interrupt-parent = <&mpic>; + fsl,num-channels = <4>; + fsl,channel-fifo-len = <24>; + fsl,exec-units-mask = <0xfe>; + fsl,descriptor-types-mask = <0x12b0ebf>; + }; diff --git a/Documentation/devicetree/bindings/powerpc/fsl/sec.txt b/Documentation/devicetree/bindings/powerpc/fsl/sec.txt deleted file mode 100644 index 2b6f2d45c45a..000000000000 --- a/Documentation/devicetree/bindings/powerpc/fsl/sec.txt +++ /dev/null @@ -1,68 +0,0 @@ -Freescale SoC SEC Security Engines - -Required properties: - -- compatible : Should contain entries for this and backward compatible - SEC versions, high to low, e.g., "fsl,sec2.1", "fsl,sec2.0" -- reg : Offset and length of the register set for the device -- interrupts : the SEC's interrupt number -- fsl,num-channels : An integer representing the number of channels - available. -- fsl,channel-fifo-len : An integer representing the number of - descriptor pointers each channel fetch fifo can hold. -- fsl,exec-units-mask : The bitmask representing what execution units - (EUs) are available. It's a single 32-bit cell. EU information - should be encoded following the SEC's Descriptor Header Dword - EU_SEL0 field documentation, i.e. as follows: - - bit 0 = reserved - should be 0 - bit 1 = set if SEC has the ARC4 EU (AFEU) - bit 2 = set if SEC has the DES/3DES EU (DEU) - bit 3 = set if SEC has the message digest EU (MDEU/MDEU-A) - bit 4 = set if SEC has the random number generator EU (RNG) - bit 5 = set if SEC has the public key EU (PKEU) - bit 6 = set if SEC has the AES EU (AESU) - bit 7 = set if SEC has the Kasumi EU (KEU) - bit 8 = set if SEC has the CRC EU (CRCU) - bit 11 = set if SEC has the message digest EU extended alg set (MDEU-B) - -remaining bits are reserved for future SEC EUs. - -- fsl,descriptor-types-mask : The bitmask representing what descriptors - are available. It's a single 32-bit cell. Descriptor type information - should be encoded following the SEC's Descriptor Header Dword DESC_TYPE - field documentation, i.e. as follows: - - bit 0 = set if SEC supports the aesu_ctr_nonsnoop desc. type - bit 1 = set if SEC supports the ipsec_esp descriptor type - bit 2 = set if SEC supports the common_nonsnoop desc. type - bit 3 = set if SEC supports the 802.11i AES ccmp desc. type - bit 4 = set if SEC supports the hmac_snoop_no_afeu desc. type - bit 5 = set if SEC supports the srtp descriptor type - bit 6 = set if SEC supports the non_hmac_snoop_no_afeu desc.type - bit 7 = set if SEC supports the pkeu_assemble descriptor type - bit 8 = set if SEC supports the aesu_key_expand_output desc.type - bit 9 = set if SEC supports the pkeu_ptmul descriptor type - bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type - bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type - - ..and so on and so forth. - -Optional properties: - -- interrupt-parent : the phandle for the interrupt controller that - services interrupts for this device. - -Example: - - /* MPC8548E */ - crypto@30000 { - compatible = "fsl,sec2.1", "fsl,sec2.0"; - reg = <0x30000 0x10000>; - interrupts = <29 2>; - interrupt-parent = <&mpic>; - fsl,num-channels = <4>; - fsl,channel-fifo-len = <24>; - fsl,exec-units-mask = <0xfe>; - fsl,descriptor-types-mask = <0x12b0ebf>; - }; -- cgit v1.2.3 From 2e39e5be1ddf9fc5fbe84fe7ae3e035bb07845e5 Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Tue, 5 Jul 2011 23:42:36 -0600 Subject: tty/serial: Add devicetree support for nVidia Tegra serial ports Acked-by: Greg Kroah-Hartman Signed-off-by: Grant Likely --- Documentation/devicetree/bindings/tty/serial/of-serial.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/tty/serial/of-serial.txt b/Documentation/devicetree/bindings/tty/serial/of-serial.txt index 337a7e51faca..b8b27b0aca10 100644 --- a/Documentation/devicetree/bindings/tty/serial/of-serial.txt +++ b/Documentation/devicetree/bindings/tty/serial/of-serial.txt @@ -8,7 +8,7 @@ Required properties: - "ns16550" - "ns16750" - "ns16850" - - "nvidia,tegra250-uart" + - "nvidia,tegra20-uart" - "ibm,qpace-nwp-serial" - "serial" if the port type is unknown. - reg : offset and length of the register set for the device. -- cgit v1.2.3