From 30015f8be08a183d4942d9849fa38e97754f36cd Mon Sep 17 00:00:00 2001 From: Xin Xie Date: Thu, 24 Mar 2011 14:04:34 -0700 Subject: ARM: apply orignal SWP emulation enable patch Picked from the upstream linux tree: * ARM: 6396/1: Add SWP/SWPB emulation for ARMv7 processors (commit 64d2dc384e41e2b7acead6804593ddaaf8aad8e1) Change-Id: Ia7fca787b68e7fda9b937005f6daaefda89fa56a Reviewed-on: http://git-master/r/29741 Reviewed-by: Niket Sirsi Tested-by: Niket Sirsi --- Documentation/arm/00-INDEX | 2 ++ Documentation/arm/swp_emulation | 27 +++++++++++++++++++++++++++ 2 files changed, 29 insertions(+) create mode 100644 Documentation/arm/swp_emulation (limited to 'Documentation') diff --git a/Documentation/arm/00-INDEX b/Documentation/arm/00-INDEX index 7f5fc3ba9c91..2d025641ec55 100644 --- a/Documentation/arm/00-INDEX +++ b/Documentation/arm/00-INDEX @@ -32,3 +32,5 @@ memory.txt - description of the virtual memory layout nwfpe/ - NWFPE floating point emulator documentation +swp_emulation + - SWP/SWPB emulation handler/logging description diff --git a/Documentation/arm/swp_emulation b/Documentation/arm/swp_emulation new file mode 100644 index 000000000000..af903d22fd93 --- /dev/null +++ b/Documentation/arm/swp_emulation @@ -0,0 +1,27 @@ +Software emulation of deprecated SWP instruction (CONFIG_SWP_EMULATE) +--------------------------------------------------------------------- + +ARMv6 architecture deprecates use of the SWP/SWPB instructions, and recommeds +moving to the load-locked/store-conditional instructions LDREX and STREX. + +ARMv7 multiprocessing extensions introduce the ability to disable these +instructions, triggering an undefined instruction exception when executed. +Trapped instructions are emulated using an LDREX/STREX or LDREXB/STREXB +sequence. If a memory access fault (an abort) occurs, a segmentation fault is +signalled to the triggering process. + +/proc/cpu/swp_emulation holds some statistics/information, including the PID of +the last process to trigger the emulation to be invocated. For example: +--- +Emulated SWP: 12 +Emulated SWPB: 0 +Aborted SWP{B}: 1 +Last process: 314 +--- + +NOTE: when accessing uncached shared regions, LDREX/STREX rely on an external +transaction monitoring block called a global monitor to maintain update +atomicity. If your system does not implement a global monitor, this option can +cause programs that perform SWP operations to uncached memory to deadlock, as +the STREX operation will always fail. + -- cgit v1.2.3