From ed18bdc875328921114139e17ade1d2569e82c85 Mon Sep 17 00:00:00 2001 From: Jonathan Austin Date: Thu, 30 Aug 2012 13:46:44 +0100 Subject: ARM: vexpress: Add Cortex-R Series UART, selectable via DEBUG_LL The Cortex-R series processors on Versatile Express have a different memory map to the RS1 and CA9X4 tiles. Most of the platform difference can be expressed in device-trees, but the UART definitions for LL_DEBUG cannot. This patch defines the UART location for R-Series processors on versatile-express, allowing low-level debug and output from the decompressor. These definitions are selectable via Kconfig Signed-off-by: Jonathan Austin CC: Pawel Moll --- arch/arm/Kconfig.debug | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'arch/arm/Kconfig.debug') diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 1d41908d5cda..f2623b25ff9a 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -476,6 +476,13 @@ choice of the tiles using the RS1 memory map, including all new A-class core tiles, FPGA-based SMMs and software models. + config DEBUG_VEXPRESS_UART0_CRX + bool "Use PL011 UART0 at 0xb0090000 (Cortex-R compliant tiles)" + depends on ARCH_VEXPRESS && !MMU + help + This option selects UART0 at 0xb0090000. This is appropriate for + Cortex-R series tiles and SMMs, such as Cortex-R5 and Cortex-R7 + config DEBUG_VT8500_UART0 bool "Use UART0 on VIA/Wondermedia SoCs" depends on ARCH_VT8500 @@ -645,7 +652,8 @@ config DEBUG_LL_INCLUDE default "debug/tegra.S" if DEBUG_TEGRA_UART default "debug/ux500.S" if DEBUG_UX500_UART default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \ - DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1 + DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1 || \ + DEBUG_VEXPRESS_UART0_CRX default "debug/vt8500.S" if DEBUG_VT8500_UART0 default "debug/zynq.S" if DEBUG_ZYNQ_UART0 || DEBUG_ZYNQ_UART1 default "mach/debug-macro.S" -- cgit v1.2.3