From 155dfc7b543345ed45521900bbd32c0db4ea266e Mon Sep 17 00:00:00 2001 From: Peter De Schrijver Date: Thu, 12 Jun 2014 18:36:38 +0300 Subject: soc/tegra: Add efuse and apbmisc bindings Add efuse and apbmisc bindings for Tegra20, Tegra30, Tegra114 and Tegra124. Signed-off-by: Peter De Schrijver Signed-off-by: Stephen Warren Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm/boot/dts/tegra124.dtsi') diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 6e6bc4e8185c..226941c07d15 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -179,6 +179,12 @@ #dma-cells = <1>; }; + apbmisc@0,70000800 { + compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"; + reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ + <0x0 0x7000E864 0x0 0x04>; /* Strapping options */ + }; + pinmux: pinmux@0,70000868 { compatible = "nvidia,tegra124-pinmux"; reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ @@ -449,6 +455,15 @@ clock-names = "pclk", "clk32k_in"; }; + fuse@0,7000f800 { + compatible = "nvidia,tegra124-efuse"; + reg = <0x0 0x7000f800 0x0 0x400>; + clocks = <&tegra_car TEGRA124_CLK_FUSE>; + clock-names = "fuse"; + resets = <&tegra_car 39>; + reset-names = "fuse"; + }; + sdhci@0,700b0000 { compatible = "nvidia,tegra124-sdhci"; reg = <0x0 0x700b0000 0x0 0x200>; -- cgit v1.2.3