From ab343e91aa00d6cc1047e8209d610c384ee824b9 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Tue, 22 Jan 2013 22:46:07 +0100 Subject: ARM: tegra: move serial clock-frequency attr into the Tegra20 dtsi No Tegra20 Platform is running PLL_P at another rate than 216MHz, nor is any using any other PLL as UART source clock. Move attribute into SoC level dtsi file to slim down board DT files. Signed-off-by: Lucas Stach Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra20-harmony.dts | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm/boot/dts/tegra20-harmony.dts') diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index 54295e341f60..96f4ccd6fb58 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -252,7 +252,6 @@ serial@70006300 { status = "okay"; - clock-frequency = <216000000>; }; i2c@7000c000 { -- cgit v1.2.3