From abf80c276dca1bf40b342b4ebf7815be0f6ba564 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 23 Jan 2013 09:43:49 -0700 Subject: ARM: tegra: move serial clock-frequency attr into the Tegra30 dtsi No Tegra30 Platform is running PLL_P at another rate than 408MHz, nor is any using any other PLL as UART source clock. Move attribute into SoC level dtsi file to slim down board DT files. Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra30-cardhu.dtsi | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm/boot/dts/tegra30-cardhu.dtsi') diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index ff6b68fe08af..17499272a4ef 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -120,13 +120,11 @@ serial@70006000 { status = "okay"; - clock-frequency = <408000000>; }; serial@70006200 { compatible = "nvidia,tegra30-hsuart"; status = "okay"; - clock-frequency = <408000000>; }; i2c@7000c000 { -- cgit v1.2.3