From e29b65dbc5d0431e8f063fab19fafaaa744d55ce Mon Sep 17 00:00:00 2001 From: Pawel Moll Date: Thu, 10 May 2012 17:12:07 +0100 Subject: ARM: vexpress: Device Tree updates * Added extra regs for A15 VGIC * Added A15 architected timer node * Split A5 and A9 TWD nodes into two separate ones for timer and watchdog; interrupt definitions fixed on the way * Fixed typo in A5 GIC compatible value All the changes courtesy of Marc Zyngier. Signed-off-by: Pawel Moll --- arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts') diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts index 941b161ab78c..7e1091d91af8 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts @@ -73,7 +73,10 @@ #address-cells = <0>; interrupt-controller; reg = <0x2c001000 0x1000>, - <0x2c002000 0x100>; + <0x2c002000 0x1000>, + <0x2c004000 0x2000>, + <0x2c006000 0x2000>; + interrupts = <1 9 0xf04>; }; memory-controller@7ffd0000 { @@ -93,6 +96,14 @@ <0 91 4>; }; + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; + }; + pmu { compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu"; interrupts = <0 68 4>, -- cgit v1.2.3