From 2d9eefa67b15a3a6fbee37d4c31282ecad216569 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Tue, 7 Jan 2014 11:23:06 +0100 Subject: tegra: video: use new modedb based settings Use new modedb based framebuffer settings by defining default_mode in the display controllers platform data. Also impelmented the fallback logic to this default_mode in case no kernel cmd line parameter was set. --- arch/arm/mach-tegra/board-apalis_t30-panel.c | 265 ++------------------------- 1 file changed, 11 insertions(+), 254 deletions(-) (limited to 'arch/arm/mach-tegra/board-apalis_t30-panel.c') diff --git a/arch/arm/mach-tegra/board-apalis_t30-panel.c b/arch/arm/mach-tegra/board-apalis_t30-panel.c index cb76ca99c083..289ed2a5a6f6 100644 --- a/arch/arm/mach-tegra/board-apalis_t30-panel.c +++ b/arch/arm/mach-tegra/board-apalis_t30-panel.c @@ -211,258 +211,6 @@ static struct resource apalis_t30_disp2_resources[] = { }; #endif /* CONFIG_TEGRA_DC */ -static struct tegra_dc_mode apalis_t30_panel_modes[] = { -#ifdef TEGRA_FB_VGA - { - /* 640x480p 60hz: EIA/CEA-861-B Format 1 */ - .pclk = 25175000, /* pixclock */ - .h_ref_to_sync = 8, - .v_ref_to_sync = 2, - .h_sync_width = 96, /* hsync_len */ - .v_sync_width = 2, /* vsync_len */ - .h_back_porch = 48, /* left_margin */ - .v_back_porch = 33, /* upper_margin */ - .h_active = 640, - .v_active = 480, - .h_front_porch = 16, /* right_margin */ - .v_front_porch = 10, /* lower_margin */ - }, - { - /* 800x480@60 (e.g. EDT ET070080DH6) */ - .pclk = 32460000, - .h_ref_to_sync = 1, - .v_ref_to_sync = 1, - .h_sync_width = 64, - .v_sync_width = 3, - .h_back_porch = 128, - .v_back_porch = 22, - .h_active = 800, - .v_active = 480, - .h_front_porch = 64, - .v_front_porch = 20, - }, - { - /* 800x600@60 */ - .pclk = 39272727, - .h_sync_width = 80, - .v_sync_width = 2, - .h_back_porch = 160, - .v_back_porch = 21, - .h_active = 800, - .v_active = 600, - .h_front_porch = 16, - .v_front_porch = 1, - }, - { - /* TouchRevolution Fusion 10 aka Chunghwa Picture Tubes - CLAA101NC05 10.1 inch 1024x600 single channel LVDS panel */ - .pclk = 48000000, - .h_sync_width = 5, - .v_sync_width = 5, - .h_back_porch = 104, - .v_back_porch = 24, - .h_active = 1024, - .v_active = 600, - .h_front_porch = 43, - .v_front_porch = 20, - }, - { - /* 1024x768@60 */ - .pclk = 78800000, - .h_sync_width = 96, - .v_sync_width = 3, - .h_back_porch = 176, - .v_back_porch = 28, - .h_active = 1024, - .v_active = 768, - .h_front_porch = 16, - .v_front_porch = 1, - }, - { - /* 1024x768@75 */ - .pclk = 82000000, - .h_sync_width = 104, - .v_sync_width = 4, - .h_back_porch = 168, - .v_back_porch = 34, - .h_active = 1024, - .v_active = 768, - .h_front_porch = 64, - .v_front_porch = 3, - }, - { - /* 1280x720@60 */ - .pclk = 74250000, - .h_ref_to_sync = 1, - .v_ref_to_sync = 1, - .h_sync_width = 40, - .v_sync_width = 5, - .h_back_porch = 220, - .v_back_porch = 20, - .h_active = 1280, - .v_active = 720, - .h_front_porch = 110, - .v_front_porch = 5, -//high active sync polarities - }, - { - /* 1280x1024@60 */ - .pclk = 108000000, -// .h_ref_to_sync = 1, -// .v_ref_to_sync = 1, - .h_sync_width = 144, - .v_sync_width = 3, - .h_back_porch = 248, - .v_back_porch = 38, - .h_active = 1280, - .v_active = 1024, - .h_front_porch = 16, - .v_front_porch = 1, -//high active sync polarities - }, - { - /* 1366x768@60 */ - .pclk = 72072000, - .h_ref_to_sync = 11, - .v_ref_to_sync = 1, - .h_sync_width = 58, - .v_sync_width = 4, - .h_back_porch = 58, - .v_back_porch = 4, - .h_active = 1366, - .v_active = 768, - .h_front_porch = 58, - .v_front_porch = 4, - }, - { - /* 1600x1200@60 */ - .pclk = 162000000, -// .h_ref_to_sync = 1, -// .v_ref_to_sync = 1, - .h_sync_width = 192, - .v_sync_width = 3, - .h_back_porch = 304, - .v_back_porch = 46, - .h_active = 1600, - .v_active = 1200, - .h_front_porch = 64, - .v_front_porch = 1, -//high active sync polarities - }, - { - .pclk = 119000000, - .h_ref_to_sync = 1, - .v_ref_to_sync = 1, - .h_sync_width = 32, - .v_sync_width = 6, - .h_back_porch = 80, - .v_back_porch = 21, - .h_active = 1680, - .v_active = 1050, - .h_front_porch = 48, - .v_front_porch = 3, - }, - { - /* 1680x1050@60 */ - .pclk = 147140000, -// .h_ref_to_sync = 1, -// .v_ref_to_sync = 1, - .h_sync_width = 184, - .v_sync_width = 3, - .h_back_porch = 288, - .v_back_porch = 33, - .h_active = 1680, - .v_active = 1050, - .h_front_porch = 104, - .v_front_porch = 1, -//high active vertical sync polarity - }, -#else /* TEGRA_FB_VGA */ - { - /* LG LP156WF1 15.6 inch full HD dual channel LVDS panel */ - .pclk = 138500000, - .h_sync_width = 32, - .v_sync_width = 5, - .h_back_porch = 80, - .v_back_porch = 46, - .h_active = 1920, - .v_active = 1080, - .h_front_porch = 48, - .v_front_porch = 6, - //low active sync polarities, high pixel clock polarity - }, - { - /* 1920x1080p 59.94/60hz EIA/CEA-861-B Format 16 */ - .pclk = 148500000, - .h_ref_to_sync = 11, - .v_ref_to_sync = 1, - .h_sync_width = 44, - .v_sync_width = 5, - .h_back_porch = 148, - .v_back_porch = 36, - .h_active = 1920, - .v_active = 1080, - .h_front_porch = 88, - .v_front_porch = 4, -//high active sync polarities - }, - { - .pclk = 154000000, - .h_ref_to_sync = 11, - .v_ref_to_sync = 1, - .h_sync_width = 32, - .v_sync_width = 6, - .h_back_porch = 80, - .v_back_porch = 26, - .h_active = 1920, - .v_active = 1200, - .h_front_porch = 48, - .v_front_porch = 3, - }, - - /* portrait modes */ - - { - .pclk = 18000000, - .h_ref_to_sync = 8, - .v_ref_to_sync = 2, - .h_sync_width = 4, - .v_sync_width = 1, - .h_back_porch = 20, - .v_back_porch = 7, - .h_active = 480, - .v_active = 640, - .h_front_porch = 8, - .v_front_porch = 8, - }, - { - .pclk = 10000000, - .h_ref_to_sync = 4, - .v_ref_to_sync = 1, - .h_sync_width = 16, - .v_sync_width = 1, - .h_back_porch = 32, - .v_back_porch = 1, - .h_active = 540, - .v_active = 960, - .h_front_porch = 32, - .v_front_porch = 2, - }, - { - .pclk = 61417000, - .h_ref_to_sync = 2, - .v_ref_to_sync = 2, - .h_sync_width = 4, - .v_sync_width = 4, - .h_back_porch = 100, - .v_back_porch = 14, - .h_active = 720, - .v_active = 1280, - .h_front_porch = 4, - .v_front_porch = 4, - }, -#endif /* TEGRA_FB_VGA */ -}; #ifdef CONFIG_TEGRA_DC static struct tegra_fb_data apalis_t30_fb_data = { @@ -511,8 +259,11 @@ static struct tegra_dc_out apalis_t30_disp1_out = { .depth = 24, .dither = TEGRA_DC_ORDERED_DITHER, - .modes = apalis_t30_panel_modes, - .n_modes = ARRAY_SIZE(apalis_t30_panel_modes), +#ifdef TEGRA_FB_VGA + .default_mode = "640x480-16@60", +#else /* TEGRA_FB_VGA */ + .default_mode = "1920x1080-16@60", +#endif /* TEGRA_FB_VGA */ .out_pins = apalis_t30_dc_out_pins, .n_out_pins = ARRAY_SIZE(apalis_t30_dc_out_pins), @@ -531,6 +282,12 @@ static struct tegra_dc_out apalis_t30_disp2_out = { .max_pixclock = KHZ2PICOS(148500), +#ifdef TEGRA_FB_VGA + .default_mode = "640x480-16@60", +#else /* TEGRA_FB_VGA */ + .default_mode = "1920x1080-16@60", +#endif /* TEGRA_FB_VGA */ + .align = TEGRA_DC_ALIGN_MSB, .order = TEGRA_DC_ORDER_RED_BLUE, -- cgit v1.2.3